drivers/rtc/rtc-ds1307.c

   1 /*
   2  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
   3  *
   4  *  Copyright (C) 2005 James Chapman (ds1337 core)
   5  *  Copyright (C) 2006 David Brownell
   6  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
   7  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/bcd.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/rtc/ds1307.h>
  21 #include <linux/rtc.h>
  22 #include <linux/slab.h>
  23 #include <linux/string.h>
  24 #include <linux/hwmon.h>
  25 #include <linux/hwmon-sysfs.h>
  26 #include <linux/clk-provider.h>
  27 #include <linux/regmap.h>
  28
  29 /*
  30  * We can't determine type by probing, but if we expect pre-Linux code
  31  * to have set the chip up as a clock (turning on the oscillator and
  32  * setting the date and time), Linux can ignore the non-clock features.
  33  * That's a natural job for a factory or repair bench.
  34  */
  35 enum ds_type {
  36         ds_1307,
  37         ds_1308,
  38         ds_1337,
  39         ds_1338,
  40         ds_1339,
  41         ds_1340,
  42         ds_1341,
  43         ds_1388,
  44         ds_3231,
  45         m41t0,
  46         m41t00,
  47         m41t11,
  48         mcp794xx,
  49         rx_8025,
  50         rx_8130,
  51         last_ds_type /* always last */
  52         /* rs5c372 too?  different address... */
  53 };
  54
  55 /* RTC registers don't differ much, except for the century flag */
  56 #define DS1307_REG_SECS         0x00    /* 00-59 */
  57 #       define DS1307_BIT_CH            0x80
  58 #       define DS1340_BIT_nEOSC         0x80
  59 #       define MCP794XX_BIT_ST          0x80
  60 #define DS1307_REG_MIN          0x01    /* 00-59 */
  61 #       define M41T0_BIT_OF             0x80
  62 #define DS1307_REG_HOUR         0x02    /* 00-23, or 1-12{am,pm} */
  63 #       define DS1307_BIT_12HR          0x40    /* in REG_HOUR */
  64 #       define DS1307_BIT_PM            0x20    /* in REG_HOUR */
  65 #       define DS1340_BIT_CENTURY_EN    0x80    /* in REG_HOUR */
  66 #       define DS1340_BIT_CENTURY       0x40    /* in REG_HOUR */
  67 #define DS1307_REG_WDAY         0x03    /* 01-07 */
  68 #       define MCP794XX_BIT_VBATEN      0x08
  69 #define DS1307_REG_MDAY         0x04    /* 01-31 */
  70 #define DS1307_REG_MONTH        0x05    /* 01-12 */
  71 #       define DS1337_BIT_CENTURY       0x80    /* in REG_MONTH */
  72 #define DS1307_REG_YEAR         0x06    /* 00-99 */
  73
  74 /*
  75  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  76  * start at 7, and they differ a LOT. Only control and status matter for
  77  * basic RTC date and time functionality; be careful using them.
  78  */
  79 #define DS1307_REG_CONTROL      0x07            /* or ds1338 */
  80 #       define DS1307_BIT_OUT           0x80
  81 #       define DS1338_BIT_OSF           0x20
  82 #       define DS1307_BIT_SQWE          0x10
  83 #       define DS1307_BIT_RS1           0x02
  84 #       define DS1307_BIT_RS0           0x01
  85 #define DS1337_REG_CONTROL      0x0e
  86 #       define DS1337_BIT_nEOSC         0x80
  87 #       define DS1339_BIT_BBSQI         0x20
  88 #       define DS3231_BIT_BBSQW         0x40 /* same as BBSQI */
  89 #       define DS1337_BIT_RS2           0x10
  90 #       define DS1337_BIT_RS1           0x08
  91 #       define DS1337_BIT_INTCN         0x04
  92 #       define DS1337_BIT_A2IE          0x02
  93 #       define DS1337_BIT_A1IE          0x01
  94 #define DS1340_REG_CONTROL      0x07
  95 #       define DS1340_BIT_OUT           0x80
  96 #       define DS1340_BIT_FT            0x40
  97 #       define DS1340_BIT_CALIB_SIGN    0x20
  98 #       define DS1340_M_CALIBRATION     0x1f
  99 #define DS1340_REG_FLAG         0x09
 100 #       define DS1340_BIT_OSF           0x80
 101 #define DS1337_REG_STATUS       0x0f
 102 #       define DS1337_BIT_OSF           0x80
 103 #       define DS3231_BIT_EN32KHZ       0x08
 104 #       define DS1337_BIT_A2I           0x02
 105 #       define DS1337_BIT_A1I           0x01
 106 #define DS1339_REG_ALARM1_SECS  0x07
 107
 108 #define DS13XX_TRICKLE_CHARGER_MAGIC    0xa0
 109
 110 #define RX8025_REG_CTRL1        0x0e
 111 #       define RX8025_BIT_2412          0x20
 112 #define RX8025_REG_CTRL2        0x0f
 113 #       define RX8025_BIT_PON           0x10
 114 #       define RX8025_BIT_VDET          0x40
 115 #       define RX8025_BIT_XST           0x20
 116
 117 struct ds1307 {
 118         enum ds_type            type;
 119         unsigned long           flags;
 120 #define HAS_NVRAM       0               /* bit 0 == sysfs file active */
 121 #define HAS_ALARM       1               /* bit 1 == irq claimed */
 122         struct device           *dev;
 123         struct regmap           *regmap;
 124         const char              *name;
 125         struct rtc_device       *rtc;
 126 #ifdef CONFIG_COMMON_CLK
 127         struct clk_hw           clks[2];
 128 #endif
 129 };
 130
 131 struct chip_desc {
 132         unsigned                alarm:1;
 133         u16                     nvram_offset;
 134         u16                     nvram_size;
 135         u8                      offset; /* register's offset */
 136         u8                      century_reg;
 137         u8                      century_enable_bit;
 138         u8                      century_bit;
 139         u8                      bbsqi_bit;
 140         irq_handler_t           irq_handler;
 141         const struct rtc_class_ops *rtc_ops;
 142         u16                     trickle_charger_reg;
 143         u8                      (*do_trickle_setup)(struct ds1307 *, u32,
 144                                                     bool);
 145 };
 146
 147 static int ds1307_get_time(struct device *dev, struct rtc_time *t);
 148 static int ds1307_set_time(struct device *dev, struct rtc_time *t);
 149 static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
 150 static irqreturn_t rx8130_irq(int irq, void *dev_id);
 151 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
 152 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
 153 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
 154 static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
 155 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
 156 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
 157 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
 158
 159 static const struct rtc_class_ops rx8130_rtc_ops = {
 160         .read_time      = ds1307_get_time,
 161         .set_time       = ds1307_set_time,
 162         .read_alarm     = rx8130_read_alarm,
 163         .set_alarm      = rx8130_set_alarm,
 164         .alarm_irq_enable = rx8130_alarm_irq_enable,
 165 };
 166
 167 static const struct rtc_class_ops mcp794xx_rtc_ops = {
 168         .read_time      = ds1307_get_time,
 169         .set_time       = ds1307_set_time,
 170         .read_alarm     = mcp794xx_read_alarm,
 171         .set_alarm      = mcp794xx_set_alarm,
 172         .alarm_irq_enable = mcp794xx_alarm_irq_enable,
 173 };
 174
 175 static const struct chip_desc chips[last_ds_type] = {
 176         [ds_1307] = {
 177                 .nvram_offset   = 8,
 178                 .nvram_size     = 56,
 179         },
 180         [ds_1308] = {
 181                 .nvram_offset   = 8,
 182                 .nvram_size     = 56,
 183         },
 184         [ds_1337] = {
 185                 .alarm          = 1,
 186                 .century_reg    = DS1307_REG_MONTH,
 187                 .century_bit    = DS1337_BIT_CENTURY,
 188         },
 189         [ds_1338] = {
 190                 .nvram_offset   = 8,
 191                 .nvram_size     = 56,
 192         },
 193         [ds_1339] = {
 194                 .alarm          = 1,
 195                 .century_reg    = DS1307_REG_MONTH,
 196                 .century_bit    = DS1337_BIT_CENTURY,
 197                 .bbsqi_bit      = DS1339_BIT_BBSQI,
 198                 .trickle_charger_reg = 0x10,
 199                 .do_trickle_setup = &do_trickle_setup_ds1339,
 200         },
 201         [ds_1340] = {
 202                 .century_reg    = DS1307_REG_HOUR,
 203                 .century_enable_bit = DS1340_BIT_CENTURY_EN,
 204                 .century_bit    = DS1340_BIT_CENTURY,
 205                 .do_trickle_setup = &do_trickle_setup_ds1339,
 206                 .trickle_charger_reg = 0x08,
 207         },
 208         [ds_1341] = {
 209                 .century_reg    = DS1307_REG_MONTH,
 210                 .century_bit    = DS1337_BIT_CENTURY,
 211         },
 212         [ds_1388] = {
 213                 .offset         = 1,
 214                 .trickle_charger_reg = 0x0a,
 215         },
 216         [ds_3231] = {
 217                 .alarm          = 1,
 218                 .century_reg    = DS1307_REG_MONTH,
 219                 .century_bit    = DS1337_BIT_CENTURY,
 220                 .bbsqi_bit      = DS3231_BIT_BBSQW,
 221         },
 222         [rx_8130] = {
 223                 .alarm          = 1,
 224                 /* this is battery backed SRAM */
 225                 .nvram_offset   = 0x20,
 226                 .nvram_size     = 4,    /* 32bit (4 word x 8 bit) */
 227                 .offset         = 0x10,
 228                 .irq_handler = rx8130_irq,
 229                 .rtc_ops = &rx8130_rtc_ops,
 230         },
 231         [m41t11] = {
 232                 /* this is battery backed SRAM */
 233                 .nvram_offset   = 8,
 234                 .nvram_size     = 56,
 235         },
 236         [mcp794xx] = {
 237                 .alarm          = 1,
 238                 /* this is battery backed SRAM */
 239                 .nvram_offset   = 0x20,
 240                 .nvram_size     = 0x40,
 241                 .irq_handler = mcp794xx_irq,
 242                 .rtc_ops = &mcp794xx_rtc_ops,
 243         },
 244 };
 245
 246 static const struct i2c_device_id ds1307_id[] = {
 247         { "ds1307", ds_1307 },
 248         { "ds1308", ds_1308 },
 249         { "ds1337", ds_1337 },
 250         { "ds1338", ds_1338 },
 251         { "ds1339", ds_1339 },
 252         { "ds1388", ds_1388 },
 253         { "ds1340", ds_1340 },
 254         { "ds1341", ds_1341 },
 255         { "ds3231", ds_3231 },
 256         { "m41t0", m41t0 },
 257         { "m41t00", m41t00 },
 258         { "m41t11", m41t11 },
 259         { "mcp7940x", mcp794xx },
 260         { "mcp7941x", mcp794xx },
 261         { "pt7c4338", ds_1307 },
 262         { "rx8025", rx_8025 },
 263         { "isl12057", ds_1337 },
 264         { "rx8130", rx_8130 },
 265         { }
 266 };
 267 MODULE_DEVICE_TABLE(i2c, ds1307_id);
 268
 269 #ifdef CONFIG_OF
 270 static const struct of_device_id ds1307_of_match[] = {
 271         {
 272                 .compatible = "dallas,ds1307",
 273                 .data = (void *)ds_1307
 274         },
 275         {
 276                 .compatible = "dallas,ds1308",
 277                 .data = (void *)ds_1308
 278         },
 279         {
 280                 .compatible = "dallas,ds1337",
 281                 .data = (void *)ds_1337
 282         },
 283         {
 284                 .compatible = "dallas,ds1338",
 285                 .data = (void *)ds_1338
 286         },
 287         {
 288                 .compatible = "dallas,ds1339",
 289                 .data = (void *)ds_1339
 290         },
 291         {
 292                 .compatible = "dallas,ds1388",
 293                 .data = (void *)ds_1388
 294         },
 295         {
 296                 .compatible = "dallas,ds1340",
 297                 .data = (void *)ds_1340
 298         },
 299         {
 300                 .compatible = "dallas,ds1341",
 301                 .data = (void *)ds_1341
 302         },
 303         {
 304                 .compatible = "maxim,ds3231",
 305                 .data = (void *)ds_3231
 306         },
 307         {
 308                 .compatible = "st,m41t0",
 309                 .data = (void *)m41t0
 310         },
 311         {
 312                 .compatible = "st,m41t00",
 313                 .data = (void *)m41t00
 314         },
 315         {
 316                 .compatible = "st,m41t11",
 317                 .data = (void *)m41t11
 318         },
 319         {
 320                 .compatible = "microchip,mcp7940x",
 321                 .data = (void *)mcp794xx
 322         },
 323         {
 324                 .compatible = "microchip,mcp7941x",
 325                 .data = (void *)mcp794xx
 326         },
 327         {
 328                 .compatible = "pericom,pt7c4338",
 329                 .data = (void *)ds_1307
 330         },
 331         {
 332                 .compatible = "epson,rx8025",
 333                 .data = (void *)rx_8025
 334         },
 335         {
 336                 .compatible = "isil,isl12057",
 337                 .data = (void *)ds_1337
 338         },
 339         {
 340                 .compatible = "epson,rx8130",
 341                 .data = (void *)rx_8130
 342         },
 343         { }
 344 };
 345 MODULE_DEVICE_TABLE(of, ds1307_of_match);
 346 #endif
 347
 348 #ifdef CONFIG_ACPI
 349 static const struct acpi_device_id ds1307_acpi_ids[] = {
 350         { .id = "DS1307", .driver_data = ds_1307 },
 351         { .id = "DS1308", .driver_data = ds_1308 },
 352         { .id = "DS1337", .driver_data = ds_1337 },
 353         { .id = "DS1338", .driver_data = ds_1338 },
 354         { .id = "DS1339", .driver_data = ds_1339 },
 355         { .id = "DS1388", .driver_data = ds_1388 },
 356         { .id = "DS1340", .driver_data = ds_1340 },
 357         { .id = "DS1341", .driver_data = ds_1341 },
 358         { .id = "DS3231", .driver_data = ds_3231 },
 359         { .id = "M41T0", .driver_data = m41t0 },
 360         { .id = "M41T00", .driver_data = m41t00 },
 361         { .id = "M41T11", .driver_data = m41t11 },
 362         { .id = "MCP7940X", .driver_data = mcp794xx },
 363         { .id = "MCP7941X", .driver_data = mcp794xx },
 364         { .id = "PT7C4338", .driver_data = ds_1307 },
 365         { .id = "RX8025", .driver_data = rx_8025 },
 366         { .id = "ISL12057", .driver_data = ds_1337 },
 367         { .id = "RX8130", .driver_data = rx_8130 },
 368         { }
 369 };
 370 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
 371 #endif
 372
 373 /*
 374  * The ds1337 and ds1339 both have two alarms, but we only use the first
 375  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
 376  * signal; ds1339 chips have only one alarm signal.
 377  */
 378 static irqreturn_t ds1307_irq(int irq, void *dev_id)
 379 {
 380         struct ds1307           *ds1307 = dev_id;
 381         struct mutex            *lock = &ds1307->rtc->ops_lock;
 382         int                     stat, ret;
 383
 384         mutex_lock(lock);
 385         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
 386         if (ret)
 387                 goto out;
 388
 389         if (stat & DS1337_BIT_A1I) {
 390                 stat &= ~DS1337_BIT_A1I;
 391                 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
 392
 393                 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 394                                          DS1337_BIT_A1IE, 0);
 395                 if (ret)
 396                         goto out;
 397
 398                 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 399         }
 400
 401 out:
 402         mutex_unlock(lock);
 403
 404         return IRQ_HANDLED;
 405 }
 406
 407 /*----------------------------------------------------------------------*/
 408
 409 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
 410 {
 411         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 412         int             tmp, ret;
 413         const struct chip_desc *chip = &chips[ds1307->type];
 414         u8 regs[7];
 415
 416         /* read the RTC date and time registers all at once */
 417         ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
 418                                sizeof(regs));
 419         if (ret) {
 420                 dev_err(dev, "%s error %d\n", "read", ret);
 421                 return ret;
 422         }
 423
 424         dev_dbg(dev, "%s: %7ph\n", "read", regs);
 425
 426         /* if oscillator fail bit is set, no data can be trusted */
 427         if (ds1307->type == m41t0 &&
 428             regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
 429                 dev_warn_once(dev, "oscillator failed, set time!\n");
 430                 return -EINVAL;
 431         }
 432
 433         t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
 434         t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
 435         tmp = regs[DS1307_REG_HOUR] & 0x3f;
 436         t->tm_hour = bcd2bin(tmp);
 437         t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
 438         t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
 439         tmp = regs[DS1307_REG_MONTH] & 0x1f;
 440         t->tm_mon = bcd2bin(tmp) - 1;
 441         t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
 442
 443         if (regs[chip->century_reg] & chip->century_bit &&
 444             IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
 445                 t->tm_year += 100;
 446
 447         dev_dbg(dev, "%s secs=%d, mins=%d, "
 448                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 449                 "read", t->tm_sec, t->tm_min,
 450                 t->tm_hour, t->tm_mday,
 451                 t->tm_mon, t->tm_year, t->tm_wday);
 452
 453         return 0;
 454 }
 455
 456 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
 457 {
 458         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 459         const struct chip_desc *chip = &chips[ds1307->type];
 460         int             result;
 461         int             tmp;
 462         u8              regs[7];
 463
 464         dev_dbg(dev, "%s secs=%d, mins=%d, "
 465                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 466                 "write", t->tm_sec, t->tm_min,
 467                 t->tm_hour, t->tm_mday,
 468                 t->tm_mon, t->tm_year, t->tm_wday);
 469
 470         if (t->tm_year < 100)
 471                 return -EINVAL;
 472
 473 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
 474         if (t->tm_year > (chip->century_bit ? 299 : 199))
 475                 return -EINVAL;
 476 #else
 477         if (t->tm_year > 199)
 478                 return -EINVAL;
 479 #endif
 480
 481         regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
 482         regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
 483         regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
 484         regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
 485         regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
 486         regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
 487
 488         /* assume 20YY not 19YY */
 489         tmp = t->tm_year - 100;
 490         regs[DS1307_REG_YEAR] = bin2bcd(tmp);
 491
 492         if (chip->century_enable_bit)
 493                 regs[chip->century_reg] |= chip->century_enable_bit;
 494         if (t->tm_year > 199 && chip->century_bit)
 495                 regs[chip->century_reg] |= chip->century_bit;
 496
 497         if (ds1307->type == mcp794xx) {
 498                 /*
 499                  * these bits were cleared when preparing the date/time
 500                  * values and need to be set again before writing the
 501                  * regsfer out to the device.
 502                  */
 503                 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
 504                 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
 505         }
 506
 507         dev_dbg(dev, "%s: %7ph\n", "write", regs);
 508
 509         result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
 510                                    sizeof(regs));
 511         if (result) {
 512                 dev_err(dev, "%s error %d\n", "write", result);
 513                 return result;
 514         }
 515         return 0;
 516 }
 517
 518 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 519 {
 520         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 521         int                     ret;
 522         u8                      regs[9];
 523
 524         if (!test_bit(HAS_ALARM, &ds1307->flags))
 525                 return -EINVAL;
 526
 527         /* read all ALARM1, ALARM2, and status registers at once */
 528         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
 529                                regs, sizeof(regs));
 530         if (ret) {
 531                 dev_err(dev, "%s error %d\n", "alarm read", ret);
 532                 return ret;
 533         }
 534
 535         dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
 536                 &regs[0], &regs[4], &regs[7]);
 537
 538         /*
 539          * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
 540          * and that all four fields are checked matches
 541          */
 542         t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
 543         t->time.tm_min = bcd2bin(regs[1] & 0x7f);
 544         t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
 545         t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
 546
 547         /* ... and status */
 548         t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
 549         t->pending = !!(regs[8] & DS1337_BIT_A1I);
 550
 551         dev_dbg(dev, "%s secs=%d, mins=%d, "
 552                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 553                 "alarm read", t->time.tm_sec, t->time.tm_min,
 554                 t->time.tm_hour, t->time.tm_mday,
 555                 t->enabled, t->pending);
 556
 557         return 0;
 558 }
 559
 560 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 561 {
 562         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 563         unsigned char           regs[9];
 564         u8                      control, status;
 565         int                     ret;
 566
 567         if (!test_bit(HAS_ALARM, &ds1307->flags))
 568                 return -EINVAL;
 569
 570         dev_dbg(dev, "%s secs=%d, mins=%d, "
 571                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 572                 "alarm set", t->time.tm_sec, t->time.tm_min,
 573                 t->time.tm_hour, t->time.tm_mday,
 574                 t->enabled, t->pending);
 575
 576         /* read current status of both alarms and the chip */
 577         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 578                                sizeof(regs));
 579         if (ret) {
 580                 dev_err(dev, "%s error %d\n", "alarm write", ret);
 581                 return ret;
 582         }
 583         control = regs[7];
 584         status = regs[8];
 585
 586         dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
 587                 &regs[0], &regs[4], control, status);
 588
 589         /* set ALARM1, using 24 hour and day-of-month modes */
 590         regs[0] = bin2bcd(t->time.tm_sec);
 591         regs[1] = bin2bcd(t->time.tm_min);
 592         regs[2] = bin2bcd(t->time.tm_hour);
 593         regs[3] = bin2bcd(t->time.tm_mday);
 594
 595         /* set ALARM2 to non-garbage */
 596         regs[4] = 0;
 597         regs[5] = 0;
 598         regs[6] = 0;
 599
 600         /* disable alarms */
 601         regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
 602         regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
 603
 604         ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 605                                 sizeof(regs));
 606         if (ret) {
 607                 dev_err(dev, "can't set alarm time\n");
 608                 return ret;
 609         }
 610
 611         /* optionally enable ALARM1 */
 612         if (t->enabled) {
 613                 dev_dbg(dev, "alarm IRQ armed\n");
 614                 regs[7] |= DS1337_BIT_A1IE;     /* only ALARM1 is used */
 615                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
 622 {
 623         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 624
 625         if (!test_bit(HAS_ALARM, &ds1307->flags))
 626                 return -ENOTTY;
 627
 628         return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 629                                   DS1337_BIT_A1IE,
 630                                   enabled ? DS1337_BIT_A1IE : 0);
 631 }
 632
 633 static const struct rtc_class_ops ds13xx_rtc_ops = {
 634         .read_time      = ds1307_get_time,
 635         .set_time       = ds1307_set_time,
 636         .read_alarm     = ds1337_read_alarm,
 637         .set_alarm      = ds1337_set_alarm,
 638         .alarm_irq_enable = ds1307_alarm_irq_enable,
 639 };
 640
 641 /*----------------------------------------------------------------------*/
 642
 643 /*
 644  * Alarm support for rx8130 devices.
 645  */
 646
 647 #define RX8130_REG_ALARM_MIN            0x07
 648 #define RX8130_REG_ALARM_HOUR           0x08
 649 #define RX8130_REG_ALARM_WEEK_OR_DAY    0x09
 650 #define RX8130_REG_EXTENSION            0x0c
 651 #define RX8130_REG_EXTENSION_WADA       BIT(3)
 652 #define RX8130_REG_FLAG                 0x0d
 653 #define RX8130_REG_FLAG_AF              BIT(3)
 654 #define RX8130_REG_CONTROL0             0x0e
 655 #define RX8130_REG_CONTROL0_AIE         BIT(3)
 656
 657 static irqreturn_t rx8130_irq(int irq, void *dev_id)
 658 {
 659         struct ds1307           *ds1307 = dev_id;
 660         struct mutex            *lock = &ds1307->rtc->ops_lock;
 661         u8 ctl[3];
 662         int ret;
 663
 664         mutex_lock(lock);
 665
 666         /* Read control registers. */
 667         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 668                                sizeof(ctl));
 669         if (ret < 0)
 670                 goto out;
 671         if (!(ctl[1] & RX8130_REG_FLAG_AF))
 672                 goto out;
 673         ctl[1] &= ~RX8130_REG_FLAG_AF;
 674         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 675
 676         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 677                                 sizeof(ctl));
 678         if (ret < 0)
 679                 goto out;
 680
 681         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 682
 683 out:
 684         mutex_unlock(lock);
 685
 686         return IRQ_HANDLED;
 687 }
 688
 689 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 690 {
 691         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 692         u8 ald[3], ctl[3];
 693         int ret;
 694
 695         if (!test_bit(HAS_ALARM, &ds1307->flags))
 696                 return -EINVAL;
 697
 698         /* Read alarm registers. */
 699         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 700                                sizeof(ald));
 701         if (ret < 0)
 702                 return ret;
 703
 704         /* Read control registers. */
 705         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 706                                sizeof(ctl));
 707         if (ret < 0)
 708                 return ret;
 709
 710         t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
 711         t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
 712
 713         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 714         t->time.tm_sec = -1;
 715         t->time.tm_min = bcd2bin(ald[0] & 0x7f);
 716         t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
 717         t->time.tm_wday = -1;
 718         t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
 719         t->time.tm_mon = -1;
 720         t->time.tm_year = -1;
 721         t->time.tm_yday = -1;
 722         t->time.tm_isdst = -1;
 723
 724         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
 725                 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 726                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
 727
 728         return 0;
 729 }
 730
 731 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 732 {
 733         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 734         u8 ald[3], ctl[3];
 735         int ret;
 736
 737         if (!test_bit(HAS_ALARM, &ds1307->flags))
 738                 return -EINVAL;
 739
 740         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 741                 "enabled=%d pending=%d\n", __func__,
 742                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 743                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 744                 t->enabled, t->pending);
 745
 746         /* Read control registers. */
 747         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 748                                sizeof(ctl));
 749         if (ret < 0)
 750                 return ret;
 751
 752         ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
 753         ctl[1] |= RX8130_REG_FLAG_AF;
 754         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 755
 756         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 757                                 sizeof(ctl));
 758         if (ret < 0)
 759                 return ret;
 760
 761         /* Hardware alarm precision is 1 minute! */
 762         ald[0] = bin2bcd(t->time.tm_min);
 763         ald[1] = bin2bcd(t->time.tm_hour);
 764         ald[2] = bin2bcd(t->time.tm_mday);
 765
 766         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 767                                 sizeof(ald));
 768         if (ret < 0)
 769                 return ret;
 770
 771         if (!t->enabled)
 772                 return 0;
 773
 774         ctl[2] |= RX8130_REG_CONTROL0_AIE;
 775
 776         return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 777                                  sizeof(ctl));
 778 }
 779
 780 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
 781 {
 782         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 783         int ret, reg;
 784
 785         if (!test_bit(HAS_ALARM, &ds1307->flags))
 786                 return -EINVAL;
 787
 788         ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
 789         if (ret < 0)
 790                 return ret;
 791
 792         if (enabled)
 793                 reg |= RX8130_REG_CONTROL0_AIE;
 794         else
 795                 reg &= ~RX8130_REG_CONTROL0_AIE;
 796
 797         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
 798 }
 799
 800 /*----------------------------------------------------------------------*/
 801
 802 /*
 803  * Alarm support for mcp794xx devices.
 804  */
 805
 806 #define MCP794XX_REG_CONTROL            0x07
 807 #       define MCP794XX_BIT_ALM0_EN     0x10
 808 #       define MCP794XX_BIT_ALM1_EN     0x20
 809 #define MCP794XX_REG_ALARM0_BASE        0x0a
 810 #define MCP794XX_REG_ALARM0_CTRL        0x0d
 811 #define MCP794XX_REG_ALARM1_BASE        0x11
 812 #define MCP794XX_REG_ALARM1_CTRL        0x14
 813 #       define MCP794XX_BIT_ALMX_IF     BIT(3)
 814 #       define MCP794XX_BIT_ALMX_C0     BIT(4)
 815 #       define MCP794XX_BIT_ALMX_C1     BIT(5)
 816 #       define MCP794XX_BIT_ALMX_C2     BIT(6)
 817 #       define MCP794XX_BIT_ALMX_POL    BIT(7)
 818 #       define MCP794XX_MSK_ALMX_MATCH  (MCP794XX_BIT_ALMX_C0 | \
 819                                          MCP794XX_BIT_ALMX_C1 | \
 820                                          MCP794XX_BIT_ALMX_C2)
 821
 822 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
 823 {
 824         struct ds1307           *ds1307 = dev_id;
 825         struct mutex            *lock = &ds1307->rtc->ops_lock;
 826         int reg, ret;
 827
 828         mutex_lock(lock);
 829
 830         /* Check and clear alarm 0 interrupt flag. */
 831         ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
 832         if (ret)
 833                 goto out;
 834         if (!(reg & MCP794XX_BIT_ALMX_IF))
 835                 goto out;
 836         reg &= ~MCP794XX_BIT_ALMX_IF;
 837         ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
 838         if (ret)
 839                 goto out;
 840
 841         /* Disable alarm 0. */
 842         ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 843                                  MCP794XX_BIT_ALM0_EN, 0);
 844         if (ret)
 845                 goto out;
 846
 847         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 848
 849 out:
 850         mutex_unlock(lock);
 851
 852         return IRQ_HANDLED;
 853 }
 854
 855 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 856 {
 857         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 858         u8 regs[10];
 859         int ret;
 860
 861         if (!test_bit(HAS_ALARM, &ds1307->flags))
 862                 return -EINVAL;
 863
 864         /* Read control and alarm 0 registers. */
 865         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 866                                sizeof(regs));
 867         if (ret)
 868                 return ret;
 869
 870         t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
 871
 872         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 873         t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
 874         t->time.tm_min = bcd2bin(regs[4] & 0x7f);
 875         t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
 876         t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
 877         t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
 878         t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
 879         t->time.tm_year = -1;
 880         t->time.tm_yday = -1;
 881         t->time.tm_isdst = -1;
 882
 883         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 884                 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
 885                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 886                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
 887                 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
 888                 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
 889                 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
 890
 891         return 0;
 892 }
 893
 894 /*
 895  * We may have a random RTC weekday, therefore calculate alarm weekday based
 896  * on current weekday we read from the RTC timekeeping regs
 897  */
 898 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
 899 {
 900         struct rtc_time tm_now;
 901         int days_now, days_alarm, ret;
 902
 903         ret = ds1307_get_time(dev, &tm_now);
 904         if (ret)
 905                 return ret;
 906
 907         days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
 908         days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
 909
 910         return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
 911 }
 912
 913 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 914 {
 915         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 916         unsigned char regs[10];
 917         int wday, ret;
 918
 919         if (!test_bit(HAS_ALARM, &ds1307->flags))
 920                 return -EINVAL;
 921
 922         wday = mcp794xx_alm_weekday(dev, &t->time);
 923         if (wday < 0)
 924                 return wday;
 925
 926         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 927                 "enabled=%d pending=%d\n", __func__,
 928                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 929                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 930                 t->enabled, t->pending);
 931
 932         /* Read control and alarm 0 registers. */
 933         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 934                                sizeof(regs));
 935         if (ret)
 936                 return ret;
 937
 938         /* Set alarm 0, using 24-hour and day-of-month modes. */
 939         regs[3] = bin2bcd(t->time.tm_sec);
 940         regs[4] = bin2bcd(t->time.tm_min);
 941         regs[5] = bin2bcd(t->time.tm_hour);
 942         regs[6] = wday;
 943         regs[7] = bin2bcd(t->time.tm_mday);
 944         regs[8] = bin2bcd(t->time.tm_mon + 1);
 945
 946         /* Clear the alarm 0 interrupt flag. */
 947         regs[6] &= ~MCP794XX_BIT_ALMX_IF;
 948         /* Set alarm match: second, minute, hour, day, date, month. */
 949         regs[6] |= MCP794XX_MSK_ALMX_MATCH;
 950         /* Disable interrupt. We will not enable until completely programmed */
 951         regs[0] &= ~MCP794XX_BIT_ALM0_EN;
 952
 953         ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 954                                 sizeof(regs));
 955         if (ret)
 956                 return ret;
 957
 958         if (!t->enabled)
 959                 return 0;
 960         regs[0] |= MCP794XX_BIT_ALM0_EN;
 961         return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
 962 }
 963
 964 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 965 {
 966         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 967
 968         if (!test_bit(HAS_ALARM, &ds1307->flags))
 969                 return -EINVAL;
 970
 971         return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 972                                   MCP794XX_BIT_ALM0_EN,
 973                                   enabled ? MCP794XX_BIT_ALM0_EN : 0);
 974 }
 975
 976 /*----------------------------------------------------------------------*/
 977
 978 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
 979                              size_t bytes)
 980 {
 981         struct ds1307 *ds1307 = priv;
 982         const struct chip_desc *chip = &chips[ds1307->type];
 983
 984         return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
 985                                 val, bytes);
 986 }
 987
 988 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
 989                               size_t bytes)
 990 {
 991         struct ds1307 *ds1307 = priv;
 992         const struct chip_desc *chip = &chips[ds1307->type];
 993
 994         return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
 995                                  val, bytes);
 996 }
 997
 998 /*----------------------------------------------------------------------*/
 999
1000 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
1001                                   u32 ohms, bool diode)
1002 {
1003         u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
1004                 DS1307_TRICKLE_CHARGER_NO_DIODE;
1005
1006         switch (ohms) {
1007         case 250:
1008                 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
1009                 break;
1010         case 2000:
1011                 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
1012                 break;
1013         case 4000:
1014                 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
1015                 break;
1016         default:
1017                 dev_warn(ds1307->dev,
1018                          "Unsupported ohm value %u in dt\n", ohms);
1019                 return 0;
1020         }
1021         return setup;
1022 }
1023
1024 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1025                               const struct chip_desc *chip)
1026 {
1027         u32 ohms;
1028         bool diode = true;
1029
1030         if (!chip->do_trickle_setup)
1031                 return 0;
1032
1033         if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1034                                      &ohms))
1035                 return 0;
1036
1037         if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1038                 diode = false;
1039
1040         return chip->do_trickle_setup(ds1307, ohms, diode);
1041 }
1042
1043 /*----------------------------------------------------------------------*/
1044
1045 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
1046
1047 /*
1048  * Temperature sensor support for ds3231 devices.
1049  */
1050
1051 #define DS3231_REG_TEMPERATURE  0x11
1052
1053 /*
1054  * A user-initiated temperature conversion is not started by this function,
1055  * so the temperature is updated once every 64 seconds.
1056  */
1057 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1058 {
1059         struct ds1307 *ds1307 = dev_get_drvdata(dev);
1060         u8 temp_buf[2];
1061         s16 temp;
1062         int ret;
1063
1064         ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1065                                temp_buf, sizeof(temp_buf));
1066         if (ret)
1067                 return ret;
1068         /*
1069          * Temperature is represented as a 10-bit code with a resolution of
1070          * 0.25 degree celsius and encoded in two's complement format.
1071          */
1072         temp = (temp_buf[0] << 8) | temp_buf[1];
1073         temp >>= 6;
1074         *mC = temp * 250;
1075
1076         return 0;
1077 }
1078
1079 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1080                                       struct device_attribute *attr, char *buf)
1081 {
1082         int ret;
1083         s32 temp;
1084
1085         ret = ds3231_hwmon_read_temp(dev, &temp);
1086         if (ret)
1087                 return ret;
1088
1089         return sprintf(buf, "%d\n", temp);
1090 }
1091 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1092                           NULL, 0);
1093
1094 static struct attribute *ds3231_hwmon_attrs[] = {
1095         &sensor_dev_attr_temp1_input.dev_attr.attr,
1096         NULL,
1097 };
1098 ATTRIBUTE_GROUPS(ds3231_hwmon);
1099
1100 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1101 {
1102         struct device *dev;
1103
1104         if (ds1307->type != ds_3231)
1105                 return;
1106
1107         dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1108                                                      ds1307,
1109                                                      ds3231_hwmon_groups);
1110         if (IS_ERR(dev)) {
1111                 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1112                          PTR_ERR(dev));
1113         }
1114 }
1115
1116 #else
1117
1118 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1119 {
1120 }
1121
1122 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1123
1124 /*----------------------------------------------------------------------*/
1125
1126 /*
1127  * Square-wave output support for DS3231
1128  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1129  */
1130 #ifdef CONFIG_COMMON_CLK
1131
1132 enum {
1133         DS3231_CLK_SQW = 0,
1134         DS3231_CLK_32KHZ,
1135 };
1136
1137 #define clk_sqw_to_ds1307(clk)  \
1138         container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1139 #define clk_32khz_to_ds1307(clk)        \
1140         container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1141
1142 static int ds3231_clk_sqw_rates[] = {
1143         1,
1144         1024,
1145         4096,
1146         8192,
1147 };
1148
1149 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1150 {
1151         struct mutex *lock = &ds1307->rtc->ops_lock;
1152         int ret;
1153
1154         mutex_lock(lock);
1155         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1156                                  mask, value);
1157         mutex_unlock(lock);
1158
1159         return ret;
1160 }
1161
1162 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1163                                                 unsigned long parent_rate)
1164 {
1165         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1166         int control, ret;
1167         int rate_sel = 0;
1168
1169         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1170         if (ret)
1171                 return ret;
1172         if (control & DS1337_BIT_RS1)
1173                 rate_sel += 1;
1174         if (control & DS1337_BIT_RS2)
1175                 rate_sel += 2;
1176
1177         return ds3231_clk_sqw_rates[rate_sel];
1178 }
1179
1180 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1181                                       unsigned long *prate)
1182 {
1183         int i;
1184
1185         for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1186                 if (ds3231_clk_sqw_rates[i] <= rate)
1187                         return ds3231_clk_sqw_rates[i];
1188         }
1189
1190         return 0;
1191 }
1192
1193 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1194                                    unsigned long parent_rate)
1195 {
1196         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1197         int control = 0;
1198         int rate_sel;
1199
1200         for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1201                         rate_sel++) {
1202                 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1203                         break;
1204         }
1205
1206         if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1207                 return -EINVAL;
1208
1209         if (rate_sel & 1)
1210                 control |= DS1337_BIT_RS1;
1211         if (rate_sel & 2)
1212                 control |= DS1337_BIT_RS2;
1213
1214         return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1215                                 control);
1216 }
1217
1218 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1219 {
1220         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1221
1222         return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1223 }
1224
1225 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1226 {
1227         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1228
1229         ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1230 }
1231
1232 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1233 {
1234         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1235         int control, ret;
1236
1237         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1238         if (ret)
1239                 return ret;
1240
1241         return !(control & DS1337_BIT_INTCN);
1242 }
1243
1244 static const struct clk_ops ds3231_clk_sqw_ops = {
1245         .prepare = ds3231_clk_sqw_prepare,
1246         .unprepare = ds3231_clk_sqw_unprepare,
1247         .is_prepared = ds3231_clk_sqw_is_prepared,
1248         .recalc_rate = ds3231_clk_sqw_recalc_rate,
1249         .round_rate = ds3231_clk_sqw_round_rate,
1250         .set_rate = ds3231_clk_sqw_set_rate,
1251 };
1252
1253 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1254                                                   unsigned long parent_rate)
1255 {
1256         return 32768;
1257 }
1258
1259 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1260 {
1261         struct mutex *lock = &ds1307->rtc->ops_lock;
1262         int ret;
1263
1264         mutex_lock(lock);
1265         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1266                                  DS3231_BIT_EN32KHZ,
1267                                  enable ? DS3231_BIT_EN32KHZ : 0);
1268         mutex_unlock(lock);
1269
1270         return ret;
1271 }
1272
1273 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1274 {
1275         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1276
1277         return ds3231_clk_32khz_control(ds1307, true);
1278 }
1279
1280 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1281 {
1282         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1283
1284         ds3231_clk_32khz_control(ds1307, false);
1285 }
1286
1287 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1288 {
1289         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1290         int status, ret;
1291
1292         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1293         if (ret)
1294                 return ret;
1295
1296         return !!(status & DS3231_BIT_EN32KHZ);
1297 }
1298
1299 static const struct clk_ops ds3231_clk_32khz_ops = {
1300         .prepare = ds3231_clk_32khz_prepare,
1301         .unprepare = ds3231_clk_32khz_unprepare,
1302         .is_prepared = ds3231_clk_32khz_is_prepared,
1303         .recalc_rate = ds3231_clk_32khz_recalc_rate,
1304 };
1305
1306 static struct clk_init_data ds3231_clks_init[] = {
1307         [DS3231_CLK_SQW] = {
1308                 .name = "ds3231_clk_sqw",
1309                 .ops = &ds3231_clk_sqw_ops,
1310         },
1311         [DS3231_CLK_32KHZ] = {
1312                 .name = "ds3231_clk_32khz",
1313                 .ops = &ds3231_clk_32khz_ops,
1314         },
1315 };
1316
1317 static int ds3231_clks_register(struct ds1307 *ds1307)
1318 {
1319         struct device_node *node = ds1307->dev->of_node;
1320         struct clk_onecell_data *onecell;
1321         int i;
1322
1323         onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1324         if (!onecell)
1325                 return -ENOMEM;
1326
1327         onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1328         onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1329                                      sizeof(onecell->clks[0]), GFP_KERNEL);
1330         if (!onecell->clks)
1331                 return -ENOMEM;
1332
1333         for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1334                 struct clk_init_data init = ds3231_clks_init[i];
1335
1336                 /*
1337                  * Interrupt signal due to alarm conditions and square-wave
1338                  * output share same pin, so don't initialize both.
1339                  */
1340                 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1341                         continue;
1342
1343                 /* optional override of the clockname */
1344                 of_property_read_string_index(node, "clock-output-names", i,
1345                                               &init.name);
1346                 ds1307->clks[i].init = &init;
1347
1348                 onecell->clks[i] = devm_clk_register(ds1307->dev,
1349                                                      &ds1307->clks[i]);
1350                 if (IS_ERR(onecell->clks[i]))
1351                         return PTR_ERR(onecell->clks[i]);
1352         }
1353
1354         if (!node)
1355                 return 0;
1356
1357         of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1358
1359         return 0;
1360 }
1361
1362 static void ds1307_clks_register(struct ds1307 *ds1307)
1363 {
1364         int ret;
1365
1366         if (ds1307->type != ds_3231)
1367                 return;
1368
1369         ret = ds3231_clks_register(ds1307);
1370         if (ret) {
1371                 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1372                          ret);
1373         }
1374 }
1375
1376 #else
1377
1378 static void ds1307_clks_register(struct ds1307 *ds1307)
1379 {
1380 }
1381
1382 #endif /* CONFIG_COMMON_CLK */
1383
1384 static const struct regmap_config regmap_config = {
1385         .reg_bits = 8,
1386         .val_bits = 8,
1387         .max_register = 0x9,
1388 };
1389
1390 static int ds1307_probe(struct i2c_client *client,
1391                         const struct i2c_device_id *id)
1392 {
1393         struct ds1307           *ds1307;
1394         int                     err = -ENODEV;
1395         int                     tmp;
1396         const struct chip_desc  *chip;
1397         bool                    want_irq;
1398         bool                    ds1307_can_wakeup_device = false;
1399         unsigned char           regs[8];
1400         struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1401         u8                      trickle_charger_setup = 0;
1402
1403         ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1404         if (!ds1307)
1405                 return -ENOMEM;
1406
1407         dev_set_drvdata(&client->dev, ds1307);
1408         ds1307->dev = &client->dev;
1409         ds1307->name = client->name;
1410
1411         ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1412         if (IS_ERR(ds1307->regmap)) {
1413                 dev_err(ds1307->dev, "regmap allocation failed\n");
1414                 return PTR_ERR(ds1307->regmap);
1415         }
1416
1417         i2c_set_clientdata(client, ds1307);
1418
1419         if (client->dev.of_node) {
1420                 ds1307->type = (enum ds_type)
1421                         of_device_get_match_data(&client->dev);
1422                 chip = &chips[ds1307->type];
1423         } else if (id) {
1424                 chip = &chips[id->driver_data];
1425                 ds1307->type = id->driver_data;
1426         } else {
1427                 const struct acpi_device_id *acpi_id;
1428
1429                 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1430                                             ds1307->dev);
1431                 if (!acpi_id)
1432                         return -ENODEV;
1433                 chip = &chips[acpi_id->driver_data];
1434                 ds1307->type = acpi_id->driver_data;
1435         }
1436
1437         want_irq = client->irq > 0 && chip->alarm;
1438
1439         if (!pdata)
1440                 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1441         else if (pdata->trickle_charger_setup)
1442                 trickle_charger_setup = pdata->trickle_charger_setup;
1443
1444         if (trickle_charger_setup && chip->trickle_charger_reg) {
1445                 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1446                 dev_dbg(ds1307->dev,
1447                         "writing trickle charger info 0x%x to 0x%x\n",
1448                         trickle_charger_setup, chip->trickle_charger_reg);
1449                 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1450                              trickle_charger_setup);
1451         }
1452
1453 #ifdef CONFIG_OF
1454 /*
1455  * For devices with no IRQ directly connected to the SoC, the RTC chip
1456  * can be forced as a wakeup source by stating that explicitly in
1457  * the device's .dts file using the "wakeup-source" boolean property.
1458  * If the "wakeup-source" property is set, don't request an IRQ.
1459  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1460  * if supported by the RTC.
1461  */
1462         if (chip->alarm && of_property_read_bool(client->dev.of_node,
1463                                                  "wakeup-source"))
1464                 ds1307_can_wakeup_device = true;
1465 #endif
1466
1467         switch (ds1307->type) {
1468         case ds_1337:
1469         case ds_1339:
1470         case ds_1341:
1471         case ds_3231:
1472                 /* get registers that the "rtc" read below won't read... */
1473                 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1474                                        regs, 2);
1475                 if (err) {
1476                         dev_dbg(ds1307->dev, "read error %d\n", err);
1477                         goto exit;
1478                 }
1479
1480                 /* oscillator off?  turn it on, so clock can tick. */
1481                 if (regs[0] & DS1337_BIT_nEOSC)
1482                         regs[0] &= ~DS1337_BIT_nEOSC;
1483
1484                 /*
1485                  * Using IRQ or defined as wakeup-source?
1486                  * Disable the square wave and both alarms.
1487                  * For some variants, be sure alarms can trigger when we're
1488                  * running on Vbackup (BBSQI/BBSQW)
1489                  */
1490                 if (want_irq || ds1307_can_wakeup_device) {
1491                         regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1492                         regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1493                 }
1494
1495                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1496                              regs[0]);
1497
1498                 /* oscillator fault?  clear flag, and warn */
1499                 if (regs[1] & DS1337_BIT_OSF) {
1500                         regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1501                                      regs[1] & ~DS1337_BIT_OSF);
1502                         dev_warn(ds1307->dev, "SET TIME!\n");
1503                 }
1504                 break;
1505
1506         case rx_8025:
1507                 err = regmap_bulk_read(ds1307->regmap,
1508                                        RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1509                 if (err) {
1510                         dev_dbg(ds1307->dev, "read error %d\n", err);
1511                         goto exit;
1512                 }
1513
1514                 /* oscillator off?  turn it on, so clock can tick. */
1515                 if (!(regs[1] & RX8025_BIT_XST)) {
1516                         regs[1] |= RX8025_BIT_XST;
1517                         regmap_write(ds1307->regmap,
1518                                      RX8025_REG_CTRL2 << 4 | 0x08,
1519                                      regs[1]);
1520                         dev_warn(ds1307->dev,
1521                                  "oscillator stop detected - SET TIME!\n");
1522                 }
1523
1524                 if (regs[1] & RX8025_BIT_PON) {
1525                         regs[1] &= ~RX8025_BIT_PON;
1526                         regmap_write(ds1307->regmap,
1527                                      RX8025_REG_CTRL2 << 4 | 0x08,
1528                                      regs[1]);
1529                         dev_warn(ds1307->dev, "power-on detected\n");
1530                 }
1531
1532                 if (regs[1] & RX8025_BIT_VDET) {
1533                         regs[1] &= ~RX8025_BIT_VDET;
1534                         regmap_write(ds1307->regmap,
1535                                      RX8025_REG_CTRL2 << 4 | 0x08,
1536                                      regs[1]);
1537                         dev_warn(ds1307->dev, "voltage drop detected\n");
1538                 }
1539
1540                 /* make sure we are running in 24hour mode */
1541                 if (!(regs[0] & RX8025_BIT_2412)) {
1542                         u8 hour;
1543
1544                         /* switch to 24 hour mode */
1545                         regmap_write(ds1307->regmap,
1546                                      RX8025_REG_CTRL1 << 4 | 0x08,
1547                                      regs[0] | RX8025_BIT_2412);
1548
1549                         err = regmap_bulk_read(ds1307->regmap,
1550                                                RX8025_REG_CTRL1 << 4 | 0x08,
1551                                                regs, 2);
1552                         if (err) {
1553                                 dev_dbg(ds1307->dev, "read error %d\n", err);
1554                                 goto exit;
1555                         }
1556
1557                         /* correct hour */
1558                         hour = bcd2bin(regs[DS1307_REG_HOUR]);
1559                         if (hour == 12)
1560                                 hour = 0;
1561                         if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1562                                 hour += 12;
1563
1564                         regmap_write(ds1307->regmap,
1565                                      DS1307_REG_HOUR << 4 | 0x08, hour);
1566                 }
1567                 break;
1568         default:
1569                 break;
1570         }
1571
1572 read_rtc:
1573         /* read RTC registers */
1574         err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1575                                sizeof(regs));
1576         if (err) {
1577                 dev_dbg(ds1307->dev, "read error %d\n", err);
1578                 goto exit;
1579         }
1580
1581         /*
1582          * minimal sanity checking; some chips (like DS1340) don't
1583          * specify the extra bits as must-be-zero, but there are
1584          * still a few values that are clearly out-of-range.
1585          */
1586         tmp = regs[DS1307_REG_SECS];
1587         switch (ds1307->type) {
1588         case ds_1307:
1589         case m41t0:
1590         case m41t00:
1591         case m41t11:
1592                 /* clock halted?  turn it on, so clock can tick. */
1593                 if (tmp & DS1307_BIT_CH) {
1594                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1595                         dev_warn(ds1307->dev, "SET TIME!\n");
1596                         goto read_rtc;
1597                 }
1598                 break;
1599         case ds_1308:
1600         case ds_1338:
1601                 /* clock halted?  turn it on, so clock can tick. */
1602                 if (tmp & DS1307_BIT_CH)
1603                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1604
1605                 /* oscillator fault?  clear flag, and warn */
1606                 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1607                         regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1608                                      regs[DS1307_REG_CONTROL] &
1609                                      ~DS1338_BIT_OSF);
1610                         dev_warn(ds1307->dev, "SET TIME!\n");
1611                         goto read_rtc;
1612                 }
1613                 break;
1614         case ds_1340:
1615                 /* clock halted?  turn it on, so clock can tick. */
1616                 if (tmp & DS1340_BIT_nEOSC)
1617                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1618
1619                 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1620                 if (err) {
1621                         dev_dbg(ds1307->dev, "read error %d\n", err);
1622                         goto exit;
1623                 }
1624
1625                 /* oscillator fault?  clear flag, and warn */
1626                 if (tmp & DS1340_BIT_OSF) {
1627                         regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1628                         dev_warn(ds1307->dev, "SET TIME!\n");
1629                 }
1630                 break;
1631         case mcp794xx:
1632                 /* make sure that the backup battery is enabled */
1633                 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1634                         regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1635                                      regs[DS1307_REG_WDAY] |
1636                                      MCP794XX_BIT_VBATEN);
1637                 }
1638
1639                 /* clock halted?  turn it on, so clock can tick. */
1640                 if (!(tmp & MCP794XX_BIT_ST)) {
1641                         regmap_write(ds1307->regmap, DS1307_REG_SECS,
1642                                      MCP794XX_BIT_ST);
1643                         dev_warn(ds1307->dev, "SET TIME!\n");
1644                         goto read_rtc;
1645                 }
1646
1647                 break;
1648         default:
1649                 break;
1650         }
1651
1652         tmp = regs[DS1307_REG_HOUR];
1653         switch (ds1307->type) {
1654         case ds_1340:
1655         case m41t0:
1656         case m41t00:
1657         case m41t11:
1658                 /*
1659                  * NOTE: ignores century bits; fix before deploying
1660                  * systems that will run through year 2100.
1661                  */
1662                 break;
1663         case rx_8025:
1664                 break;
1665         default:
1666                 if (!(tmp & DS1307_BIT_12HR))
1667                         break;
1668
1669                 /*
1670                  * Be sure we're in 24 hour mode.  Multi-master systems
1671                  * take note...
1672                  */
1673                 tmp = bcd2bin(tmp & 0x1f);
1674                 if (tmp == 12)
1675                         tmp = 0;
1676                 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1677                         tmp += 12;
1678                 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1679                              bin2bcd(tmp));
1680         }
1681
1682         if (want_irq || ds1307_can_wakeup_device) {
1683                 device_set_wakeup_capable(ds1307->dev, true);
1684                 set_bit(HAS_ALARM, &ds1307->flags);
1685         }
1686
1687         ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1688         if (IS_ERR(ds1307->rtc))
1689                 return PTR_ERR(ds1307->rtc);
1690
1691         if (ds1307_can_wakeup_device && !want_irq) {
1692                 dev_info(ds1307->dev,
1693                          "'wakeup-source' is set, request for an IRQ is disabled!\n");
1694                 /* We cannot support UIE mode if we do not have an IRQ line */
1695                 ds1307->rtc->uie_unsupported = 1;
1696         }
1697
1698         if (want_irq) {
1699                 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1700                                                 chip->irq_handler ?: ds1307_irq,
1701                                                 IRQF_SHARED | IRQF_ONESHOT,
1702                                                 ds1307->name, ds1307);
1703                 if (err) {
1704                         client->irq = 0;
1705                         device_set_wakeup_capable(ds1307->dev, false);
1706                         clear_bit(HAS_ALARM, &ds1307->flags);
1707                         dev_err(ds1307->dev, "unable to request IRQ!\n");
1708                 } else {
1709                         dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1710                 }
1711         }
1712
1713         ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1714         err = rtc_register_device(ds1307->rtc);
1715         if (err)
1716                 return err;
1717
1718         if (chip->nvram_size) {
1719                 struct nvmem_config nvmem_cfg = {
1720                         .name = "ds1307_nvram",
1721                         .word_size = 1,
1722                         .stride = 1,
1723                         .size = chip->nvram_size,
1724                         .reg_read = ds1307_nvram_read,
1725                         .reg_write = ds1307_nvram_write,
1726                         .priv = ds1307,
1727                 };
1728
1729                 ds1307->rtc->nvram_old_abi = true;
1730                 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1731         }
1732
1733         ds1307_hwmon_register(ds1307);
1734         ds1307_clks_register(ds1307);
1735
1736         return 0;
1737
1738 exit:
1739         return err;
1740 }
1741
1742 static struct i2c_driver ds1307_driver = {
1743         .driver = {
1744                 .name   = "rtc-ds1307",
1745                 .of_match_table = of_match_ptr(ds1307_of_match),
1746                 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1747         },
1748         .probe          = ds1307_probe,
1749         .id_table       = ds1307_id,
1750 };
1751
1752 module_i2c_driver(ds1307_driver);
1753
1754 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1755 MODULE_LICENSE("GPL");