1 // SPDX-License-Identifier: GPL-2.0-only
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
11 #include <linux/bcd.h>
12 #include <linux/i2c.h>
13 #include <linux/init.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/rtc/ds1307.h>
18 #include <linux/rtc.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
34 unknown_ds_type, /* always first and 0 */
50 last_ds_type /* always last */
51 /* rs5c372 too? different address... */
54 /* RTC registers don't differ much, except for the century flag */
55 #define DS1307_REG_SECS 0x00 /* 00-59 */
56 # define DS1307_BIT_CH 0x80
57 # define DS1340_BIT_nEOSC 0x80
58 # define MCP794XX_BIT_ST 0x80
59 #define DS1307_REG_MIN 0x01 /* 00-59 */
60 # define M41T0_BIT_OF 0x80
61 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66 #define DS1307_REG_WDAY 0x03 /* 01-07 */
67 # define MCP794XX_BIT_VBATEN 0x08
68 #define DS1307_REG_MDAY 0x04 /* 01-31 */
69 #define DS1307_REG_MONTH 0x05 /* 01-12 */
70 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71 #define DS1307_REG_YEAR 0x06 /* 00-99 */
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
78 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
79 # define DS1307_BIT_OUT 0x80
80 # define DS1338_BIT_OSF 0x20
81 # define DS1307_BIT_SQWE 0x10
82 # define DS1307_BIT_RS1 0x02
83 # define DS1307_BIT_RS0 0x01
84 #define DS1337_REG_CONTROL 0x0e
85 # define DS1337_BIT_nEOSC 0x80
86 # define DS1339_BIT_BBSQI 0x20
87 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
88 # define DS1337_BIT_RS2 0x10
89 # define DS1337_BIT_RS1 0x08
90 # define DS1337_BIT_INTCN 0x04
91 # define DS1337_BIT_A2IE 0x02
92 # define DS1337_BIT_A1IE 0x01
93 #define DS1340_REG_CONTROL 0x07
94 # define DS1340_BIT_OUT 0x80
95 # define DS1340_BIT_FT 0x40
96 # define DS1340_BIT_CALIB_SIGN 0x20
97 # define DS1340_M_CALIBRATION 0x1f
98 #define DS1340_REG_FLAG 0x09
99 # define DS1340_BIT_OSF 0x80
100 #define DS1337_REG_STATUS 0x0f
101 # define DS1337_BIT_OSF 0x80
102 # define DS3231_BIT_EN32KHZ 0x08
103 # define DS1337_BIT_A2I 0x02
104 # define DS1337_BIT_A1I 0x01
105 #define DS1339_REG_ALARM1_SECS 0x07
107 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
109 #define RX8025_REG_CTRL1 0x0e
110 # define RX8025_BIT_2412 0x20
111 #define RX8025_REG_CTRL2 0x0f
112 # define RX8025_BIT_PON 0x10
113 # define RX8025_BIT_VDET 0x40
114 # define RX8025_BIT_XST 0x20
116 #define RX8130_REG_ALARM_MIN 0x17
117 #define RX8130_REG_ALARM_HOUR 0x18
118 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
119 #define RX8130_REG_EXTENSION 0x1c
120 #define RX8130_REG_EXTENSION_WADA BIT(3)
121 #define RX8130_REG_FLAG 0x1d
122 #define RX8130_REG_FLAG_VLF BIT(1)
123 #define RX8130_REG_FLAG_AF BIT(3)
124 #define RX8130_REG_CONTROL0 0x1e
125 #define RX8130_REG_CONTROL0_AIE BIT(3)
126 #define RX8130_REG_CONTROL1 0x1f
127 #define RX8130_REG_CONTROL1_INIEN BIT(4)
128 #define RX8130_REG_CONTROL1_CHGEN BIT(5)
130 #define MCP794XX_REG_CONTROL 0x07
131 # define MCP794XX_BIT_ALM0_EN 0x10
132 # define MCP794XX_BIT_ALM1_EN 0x20
133 #define MCP794XX_REG_ALARM0_BASE 0x0a
134 #define MCP794XX_REG_ALARM0_CTRL 0x0d
135 #define MCP794XX_REG_ALARM1_BASE 0x11
136 #define MCP794XX_REG_ALARM1_CTRL 0x14
137 # define MCP794XX_BIT_ALMX_IF BIT(3)
138 # define MCP794XX_BIT_ALMX_C0 BIT(4)
139 # define MCP794XX_BIT_ALMX_C1 BIT(5)
140 # define MCP794XX_BIT_ALMX_C2 BIT(6)
141 # define MCP794XX_BIT_ALMX_POL BIT(7)
142 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
143 MCP794XX_BIT_ALMX_C1 | \
144 MCP794XX_BIT_ALMX_C2)
146 #define M41TXX_REG_CONTROL 0x07
147 # define M41TXX_BIT_OUT BIT(7)
148 # define M41TXX_BIT_FT BIT(6)
149 # define M41TXX_BIT_CALIB_SIGN BIT(5)
150 # define M41TXX_M_CALIBRATION GENMASK(4, 0)
152 #define DS1388_REG_WDOG_HUN_SECS 0x08
153 #define DS1388_REG_WDOG_SECS 0x09
154 #define DS1388_REG_FLAG 0x0b
155 # define DS1388_BIT_WF BIT(6)
156 # define DS1388_BIT_OSF BIT(7)
157 #define DS1388_REG_CONTROL 0x0c
158 # define DS1388_BIT_RST BIT(0)
159 # define DS1388_BIT_WDE BIT(1)
160 # define DS1388_BIT_nEOSC BIT(7)
162 /* negative offset step is -2.034ppm */
163 #define M41TXX_NEG_OFFSET_STEP_PPB 2034
164 /* positive offset step is +4.068ppm */
165 #define M41TXX_POS_OFFSET_STEP_PPB 4068
166 /* Min and max values supported with 'offset' interface by M41TXX */
167 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
168 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
173 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
174 #define HAS_ALARM 1 /* bit 1 == irq claimed */
176 struct regmap *regmap;
178 struct rtc_device *rtc;
179 #ifdef CONFIG_COMMON_CLK
180 struct clk_hw clks[2];
188 u8 offset; /* register's offset */
190 u8 century_enable_bit;
193 irq_handler_t irq_handler;
194 const struct rtc_class_ops *rtc_ops;
195 u16 trickle_charger_reg;
196 u8 (*do_trickle_setup)(struct ds1307 *, u32,
198 /* Does the RTC require trickle-resistor-ohms to select the value of
199 * the resistor between Vcc and Vbackup?
201 bool requires_trickle_resistor;
202 /* Some RTC's batteries and supercaps were charged by default, others
203 * allow charging but were not configured previously to do so.
204 * Remember this behavior to stay backwards compatible.
209 static const struct chip_desc chips[last_ds_type];
211 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
213 struct ds1307 *ds1307 = dev_get_drvdata(dev);
215 const struct chip_desc *chip = &chips[ds1307->type];
218 if (ds1307->type == rx_8130) {
219 unsigned int regflag;
220 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
222 dev_err(dev, "%s error %d\n", "read", ret);
226 if (regflag & RX8130_REG_FLAG_VLF) {
227 dev_warn_once(dev, "oscillator failed, set time!\n");
232 /* read the RTC date and time registers all at once */
233 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
236 dev_err(dev, "%s error %d\n", "read", ret);
240 dev_dbg(dev, "%s: %7ph\n", "read", regs);
242 /* if oscillator fail bit is set, no data can be trusted */
243 if (ds1307->type == m41t0 &&
244 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
245 dev_warn_once(dev, "oscillator failed, set time!\n");
249 tmp = regs[DS1307_REG_SECS];
250 switch (ds1307->type) {
255 if (tmp & DS1307_BIT_CH)
260 if (tmp & DS1307_BIT_CH)
263 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
266 if (tmp & DS1338_BIT_OSF)
270 if (tmp & DS1340_BIT_nEOSC)
273 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
276 if (tmp & DS1340_BIT_OSF)
280 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
283 if (tmp & DS1388_BIT_OSF)
287 if (!(tmp & MCP794XX_BIT_ST))
295 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
296 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
297 tmp = regs[DS1307_REG_HOUR] & 0x3f;
298 t->tm_hour = bcd2bin(tmp);
299 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
300 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
301 tmp = regs[DS1307_REG_MONTH] & 0x1f;
302 t->tm_mon = bcd2bin(tmp) - 1;
303 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
305 if (regs[chip->century_reg] & chip->century_bit &&
306 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
309 dev_dbg(dev, "%s secs=%d, mins=%d, "
310 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
311 "read", t->tm_sec, t->tm_min,
312 t->tm_hour, t->tm_mday,
313 t->tm_mon, t->tm_year, t->tm_wday);
318 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
320 struct ds1307 *ds1307 = dev_get_drvdata(dev);
321 const struct chip_desc *chip = &chips[ds1307->type];
326 dev_dbg(dev, "%s secs=%d, mins=%d, "
327 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
328 "write", t->tm_sec, t->tm_min,
329 t->tm_hour, t->tm_mday,
330 t->tm_mon, t->tm_year, t->tm_wday);
332 if (t->tm_year < 100)
335 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
336 if (t->tm_year > (chip->century_bit ? 299 : 199))
339 if (t->tm_year > 199)
343 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
344 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
345 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
346 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
347 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
348 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
350 /* assume 20YY not 19YY */
351 tmp = t->tm_year - 100;
352 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
354 if (chip->century_enable_bit)
355 regs[chip->century_reg] |= chip->century_enable_bit;
356 if (t->tm_year > 199 && chip->century_bit)
357 regs[chip->century_reg] |= chip->century_bit;
359 switch (ds1307->type) {
362 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
366 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
370 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
375 * these bits were cleared when preparing the date/time
376 * values and need to be set again before writing the
377 * regsfer out to the device.
379 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
380 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
386 dev_dbg(dev, "%s: %7ph\n", "write", regs);
388 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
391 dev_err(dev, "%s error %d\n", "write", result);
395 if (ds1307->type == rx_8130) {
396 /* clear Voltage Loss Flag as data is available now */
397 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
398 ~(u8)RX8130_REG_FLAG_VLF);
400 dev_err(dev, "%s error %d\n", "write", result);
408 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
410 struct ds1307 *ds1307 = dev_get_drvdata(dev);
414 if (!test_bit(HAS_ALARM, &ds1307->flags))
417 /* read all ALARM1, ALARM2, and status registers at once */
418 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
421 dev_err(dev, "%s error %d\n", "alarm read", ret);
425 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
426 ®s[0], ®s[4], ®s[7]);
429 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
430 * and that all four fields are checked matches
432 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
433 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
434 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
435 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
438 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
439 t->pending = !!(regs[8] & DS1337_BIT_A1I);
441 dev_dbg(dev, "%s secs=%d, mins=%d, "
442 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
443 "alarm read", t->time.tm_sec, t->time.tm_min,
444 t->time.tm_hour, t->time.tm_mday,
445 t->enabled, t->pending);
450 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
452 struct ds1307 *ds1307 = dev_get_drvdata(dev);
453 unsigned char regs[9];
457 if (!test_bit(HAS_ALARM, &ds1307->flags))
460 dev_dbg(dev, "%s secs=%d, mins=%d, "
461 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
462 "alarm set", t->time.tm_sec, t->time.tm_min,
463 t->time.tm_hour, t->time.tm_mday,
464 t->enabled, t->pending);
466 /* read current status of both alarms and the chip */
467 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
470 dev_err(dev, "%s error %d\n", "alarm write", ret);
476 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
477 ®s[0], ®s[4], control, status);
479 /* set ALARM1, using 24 hour and day-of-month modes */
480 regs[0] = bin2bcd(t->time.tm_sec);
481 regs[1] = bin2bcd(t->time.tm_min);
482 regs[2] = bin2bcd(t->time.tm_hour);
483 regs[3] = bin2bcd(t->time.tm_mday);
485 /* set ALARM2 to non-garbage */
491 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
492 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
494 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
497 dev_err(dev, "can't set alarm time\n");
501 /* optionally enable ALARM1 */
503 dev_dbg(dev, "alarm IRQ armed\n");
504 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
505 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
511 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
513 struct ds1307 *ds1307 = dev_get_drvdata(dev);
515 if (!test_bit(HAS_ALARM, &ds1307->flags))
518 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
520 enabled ? DS1337_BIT_A1IE : 0);
523 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
525 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
526 DS1307_TRICKLE_CHARGER_NO_DIODE;
528 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
532 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
535 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
538 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
541 dev_warn(ds1307->dev,
542 "Unsupported ohm value %u in dt\n", ohms);
548 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
550 /* make sure that the backup battery is enabled */
551 u8 setup = RX8130_REG_CONTROL1_INIEN;
553 setup |= RX8130_REG_CONTROL1_CHGEN;
558 static irqreturn_t rx8130_irq(int irq, void *dev_id)
560 struct ds1307 *ds1307 = dev_id;
564 rtc_lock(ds1307->rtc);
566 /* Read control registers. */
567 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
571 if (!(ctl[1] & RX8130_REG_FLAG_AF))
573 ctl[1] &= ~RX8130_REG_FLAG_AF;
574 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
576 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
581 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
584 rtc_unlock(ds1307->rtc);
589 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
591 struct ds1307 *ds1307 = dev_get_drvdata(dev);
595 if (!test_bit(HAS_ALARM, &ds1307->flags))
598 /* Read alarm registers. */
599 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
604 /* Read control registers. */
605 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
610 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
611 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
613 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
615 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
616 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
617 t->time.tm_wday = -1;
618 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
620 t->time.tm_year = -1;
621 t->time.tm_yday = -1;
622 t->time.tm_isdst = -1;
624 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
625 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
626 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
631 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
633 struct ds1307 *ds1307 = dev_get_drvdata(dev);
637 if (!test_bit(HAS_ALARM, &ds1307->flags))
640 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
641 "enabled=%d pending=%d\n", __func__,
642 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
643 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
644 t->enabled, t->pending);
646 /* Read control registers. */
647 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
652 ctl[0] &= RX8130_REG_EXTENSION_WADA;
653 ctl[1] &= ~RX8130_REG_FLAG_AF;
654 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
656 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
661 /* Hardware alarm precision is 1 minute! */
662 ald[0] = bin2bcd(t->time.tm_min);
663 ald[1] = bin2bcd(t->time.tm_hour);
664 ald[2] = bin2bcd(t->time.tm_mday);
666 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
674 ctl[2] |= RX8130_REG_CONTROL0_AIE;
676 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
679 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
681 struct ds1307 *ds1307 = dev_get_drvdata(dev);
684 if (!test_bit(HAS_ALARM, &ds1307->flags))
687 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
692 reg |= RX8130_REG_CONTROL0_AIE;
694 reg &= ~RX8130_REG_CONTROL0_AIE;
696 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
699 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
701 struct ds1307 *ds1307 = dev_id;
702 struct mutex *lock = &ds1307->rtc->ops_lock;
707 /* Check and clear alarm 0 interrupt flag. */
708 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
711 if (!(reg & MCP794XX_BIT_ALMX_IF))
713 reg &= ~MCP794XX_BIT_ALMX_IF;
714 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
718 /* Disable alarm 0. */
719 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
720 MCP794XX_BIT_ALM0_EN, 0);
724 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
732 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
734 struct ds1307 *ds1307 = dev_get_drvdata(dev);
738 if (!test_bit(HAS_ALARM, &ds1307->flags))
741 /* Read control and alarm 0 registers. */
742 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
747 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
749 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
750 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
751 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
752 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
753 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
754 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
755 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
756 t->time.tm_year = -1;
757 t->time.tm_yday = -1;
758 t->time.tm_isdst = -1;
760 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
761 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
762 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
763 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
764 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
765 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
766 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
772 * We may have a random RTC weekday, therefore calculate alarm weekday based
773 * on current weekday we read from the RTC timekeeping regs
775 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
777 struct rtc_time tm_now;
778 int days_now, days_alarm, ret;
780 ret = ds1307_get_time(dev, &tm_now);
784 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
785 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
787 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
790 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
792 struct ds1307 *ds1307 = dev_get_drvdata(dev);
793 unsigned char regs[10];
796 if (!test_bit(HAS_ALARM, &ds1307->flags))
799 wday = mcp794xx_alm_weekday(dev, &t->time);
803 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
804 "enabled=%d pending=%d\n", __func__,
805 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
806 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
807 t->enabled, t->pending);
809 /* Read control and alarm 0 registers. */
810 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
815 /* Set alarm 0, using 24-hour and day-of-month modes. */
816 regs[3] = bin2bcd(t->time.tm_sec);
817 regs[4] = bin2bcd(t->time.tm_min);
818 regs[5] = bin2bcd(t->time.tm_hour);
820 regs[7] = bin2bcd(t->time.tm_mday);
821 regs[8] = bin2bcd(t->time.tm_mon + 1);
823 /* Clear the alarm 0 interrupt flag. */
824 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
825 /* Set alarm match: second, minute, hour, day, date, month. */
826 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
827 /* Disable interrupt. We will not enable until completely programmed */
828 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
830 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
837 regs[0] |= MCP794XX_BIT_ALM0_EN;
838 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
841 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
843 struct ds1307 *ds1307 = dev_get_drvdata(dev);
845 if (!test_bit(HAS_ALARM, &ds1307->flags))
848 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
849 MCP794XX_BIT_ALM0_EN,
850 enabled ? MCP794XX_BIT_ALM0_EN : 0);
853 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
855 struct ds1307 *ds1307 = dev_get_drvdata(dev);
856 unsigned int ctrl_reg;
859 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
861 val = ctrl_reg & M41TXX_M_CALIBRATION;
863 /* check if positive */
864 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
865 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
867 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
872 static int m41txx_rtc_set_offset(struct device *dev, long offset)
874 struct ds1307 *ds1307 = dev_get_drvdata(dev);
875 unsigned int ctrl_reg;
877 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
881 ctrl_reg = DIV_ROUND_CLOSEST(offset,
882 M41TXX_POS_OFFSET_STEP_PPB);
883 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
885 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
886 M41TXX_NEG_OFFSET_STEP_PPB);
889 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
890 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
894 #ifdef CONFIG_WATCHDOG_CORE
895 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
897 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
901 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
906 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
907 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
912 * watchdog timeouts are measured in seconds. So ignore hundredths of
916 regs[1] = bin2bcd(wdt_dev->timeout);
918 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
923 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
924 DS1388_BIT_WDE | DS1388_BIT_RST,
925 DS1388_BIT_WDE | DS1388_BIT_RST);
928 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
930 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
932 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
933 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
936 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
938 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
941 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
945 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
948 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
951 wdt_dev->timeout = val;
953 regs[1] = bin2bcd(wdt_dev->timeout);
955 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
960 static const struct rtc_class_ops rx8130_rtc_ops = {
961 .read_time = ds1307_get_time,
962 .set_time = ds1307_set_time,
963 .read_alarm = rx8130_read_alarm,
964 .set_alarm = rx8130_set_alarm,
965 .alarm_irq_enable = rx8130_alarm_irq_enable,
968 static const struct rtc_class_ops mcp794xx_rtc_ops = {
969 .read_time = ds1307_get_time,
970 .set_time = ds1307_set_time,
971 .read_alarm = mcp794xx_read_alarm,
972 .set_alarm = mcp794xx_set_alarm,
973 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
976 static const struct rtc_class_ops m41txx_rtc_ops = {
977 .read_time = ds1307_get_time,
978 .set_time = ds1307_set_time,
979 .read_alarm = ds1337_read_alarm,
980 .set_alarm = ds1337_set_alarm,
981 .alarm_irq_enable = ds1307_alarm_irq_enable,
982 .read_offset = m41txx_rtc_read_offset,
983 .set_offset = m41txx_rtc_set_offset,
986 static const struct chip_desc chips[last_ds_type] = {
997 .century_reg = DS1307_REG_MONTH,
998 .century_bit = DS1337_BIT_CENTURY,
1006 .century_reg = DS1307_REG_MONTH,
1007 .century_bit = DS1337_BIT_CENTURY,
1008 .bbsqi_bit = DS1339_BIT_BBSQI,
1009 .trickle_charger_reg = 0x10,
1010 .do_trickle_setup = &do_trickle_setup_ds1339,
1011 .requires_trickle_resistor = true,
1012 .charge_default = true,
1015 .century_reg = DS1307_REG_HOUR,
1016 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1017 .century_bit = DS1340_BIT_CENTURY,
1018 .do_trickle_setup = &do_trickle_setup_ds1339,
1019 .trickle_charger_reg = 0x08,
1020 .requires_trickle_resistor = true,
1021 .charge_default = true,
1024 .century_reg = DS1307_REG_MONTH,
1025 .century_bit = DS1337_BIT_CENTURY,
1029 .trickle_charger_reg = 0x0a,
1033 .century_reg = DS1307_REG_MONTH,
1034 .century_bit = DS1337_BIT_CENTURY,
1035 .bbsqi_bit = DS3231_BIT_BBSQW,
1039 /* this is battery backed SRAM */
1040 .nvram_offset = 0x20,
1041 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1043 .irq_handler = rx8130_irq,
1044 .rtc_ops = &rx8130_rtc_ops,
1045 .trickle_charger_reg = RX8130_REG_CONTROL1,
1046 .do_trickle_setup = &do_trickle_setup_rx8130,
1049 .rtc_ops = &m41txx_rtc_ops,
1052 .rtc_ops = &m41txx_rtc_ops,
1055 /* this is battery backed SRAM */
1058 .rtc_ops = &m41txx_rtc_ops,
1062 /* this is battery backed SRAM */
1063 .nvram_offset = 0x20,
1065 .irq_handler = mcp794xx_irq,
1066 .rtc_ops = &mcp794xx_rtc_ops,
1070 static const struct i2c_device_id ds1307_id[] = {
1071 { "ds1307", ds_1307 },
1072 { "ds1308", ds_1308 },
1073 { "ds1337", ds_1337 },
1074 { "ds1338", ds_1338 },
1075 { "ds1339", ds_1339 },
1076 { "ds1388", ds_1388 },
1077 { "ds1340", ds_1340 },
1078 { "ds1341", ds_1341 },
1079 { "ds3231", ds_3231 },
1081 { "m41t00", m41t00 },
1082 { "m41t11", m41t11 },
1083 { "mcp7940x", mcp794xx },
1084 { "mcp7941x", mcp794xx },
1085 { "pt7c4338", ds_1307 },
1086 { "rx8025", rx_8025 },
1087 { "isl12057", ds_1337 },
1088 { "rx8130", rx_8130 },
1091 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1093 static const struct of_device_id ds1307_of_match[] = {
1095 .compatible = "dallas,ds1307",
1096 .data = (void *)ds_1307
1099 .compatible = "dallas,ds1308",
1100 .data = (void *)ds_1308
1103 .compatible = "dallas,ds1337",
1104 .data = (void *)ds_1337
1107 .compatible = "dallas,ds1338",
1108 .data = (void *)ds_1338
1111 .compatible = "dallas,ds1339",
1112 .data = (void *)ds_1339
1115 .compatible = "dallas,ds1388",
1116 .data = (void *)ds_1388
1119 .compatible = "dallas,ds1340",
1120 .data = (void *)ds_1340
1123 .compatible = "dallas,ds1341",
1124 .data = (void *)ds_1341
1127 .compatible = "maxim,ds3231",
1128 .data = (void *)ds_3231
1131 .compatible = "st,m41t0",
1132 .data = (void *)m41t0
1135 .compatible = "st,m41t00",
1136 .data = (void *)m41t00
1139 .compatible = "st,m41t11",
1140 .data = (void *)m41t11
1143 .compatible = "microchip,mcp7940x",
1144 .data = (void *)mcp794xx
1147 .compatible = "microchip,mcp7941x",
1148 .data = (void *)mcp794xx
1151 .compatible = "pericom,pt7c4338",
1152 .data = (void *)ds_1307
1155 .compatible = "epson,rx8025",
1156 .data = (void *)rx_8025
1159 .compatible = "isil,isl12057",
1160 .data = (void *)ds_1337
1163 .compatible = "epson,rx8130",
1164 .data = (void *)rx_8130
1168 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1171 * The ds1337 and ds1339 both have two alarms, but we only use the first
1172 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1173 * signal; ds1339 chips have only one alarm signal.
1175 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1177 struct ds1307 *ds1307 = dev_id;
1178 struct mutex *lock = &ds1307->rtc->ops_lock;
1182 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1186 if (stat & DS1337_BIT_A1I) {
1187 stat &= ~DS1337_BIT_A1I;
1188 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1190 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1191 DS1337_BIT_A1IE, 0);
1195 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1204 /*----------------------------------------------------------------------*/
1206 static const struct rtc_class_ops ds13xx_rtc_ops = {
1207 .read_time = ds1307_get_time,
1208 .set_time = ds1307_set_time,
1209 .read_alarm = ds1337_read_alarm,
1210 .set_alarm = ds1337_set_alarm,
1211 .alarm_irq_enable = ds1307_alarm_irq_enable,
1214 static ssize_t frequency_test_store(struct device *dev,
1215 struct device_attribute *attr,
1216 const char *buf, size_t count)
1218 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1222 ret = kstrtobool(buf, &freq_test_en);
1224 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1228 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1229 freq_test_en ? M41TXX_BIT_FT : 0);
1234 static ssize_t frequency_test_show(struct device *dev,
1235 struct device_attribute *attr,
1238 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1239 unsigned int ctrl_reg;
1241 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1243 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1247 static DEVICE_ATTR_RW(frequency_test);
1249 static struct attribute *rtc_freq_test_attrs[] = {
1250 &dev_attr_frequency_test.attr,
1254 static const struct attribute_group rtc_freq_test_attr_group = {
1255 .attrs = rtc_freq_test_attrs,
1258 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1262 switch (ds1307->type) {
1266 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1277 /*----------------------------------------------------------------------*/
1279 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1282 struct ds1307 *ds1307 = priv;
1283 const struct chip_desc *chip = &chips[ds1307->type];
1285 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1289 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1292 struct ds1307 *ds1307 = priv;
1293 const struct chip_desc *chip = &chips[ds1307->type];
1295 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1299 /*----------------------------------------------------------------------*/
1301 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1302 const struct chip_desc *chip)
1304 u32 ohms, chargeable;
1305 bool diode = chip->charge_default;
1307 if (!chip->do_trickle_setup)
1310 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1311 &ohms) && chip->requires_trickle_resistor)
1314 /* aux-voltage-chargeable takes precedence over the deprecated
1315 * trickle-diode-disable
1317 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1319 switch (chargeable) {
1327 dev_warn(ds1307->dev,
1328 "unsupported aux-voltage-chargeable value\n");
1331 } else if (device_property_read_bool(ds1307->dev,
1332 "trickle-diode-disable")) {
1336 return chip->do_trickle_setup(ds1307, ohms, diode);
1339 /*----------------------------------------------------------------------*/
1341 #if IS_REACHABLE(CONFIG_HWMON)
1344 * Temperature sensor support for ds3231 devices.
1347 #define DS3231_REG_TEMPERATURE 0x11
1350 * A user-initiated temperature conversion is not started by this function,
1351 * so the temperature is updated once every 64 seconds.
1353 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1355 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1360 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1361 temp_buf, sizeof(temp_buf));
1365 * Temperature is represented as a 10-bit code with a resolution of
1366 * 0.25 degree celsius and encoded in two's complement format.
1368 temp = (temp_buf[0] << 8) | temp_buf[1];
1375 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1376 struct device_attribute *attr, char *buf)
1381 ret = ds3231_hwmon_read_temp(dev, &temp);
1385 return sprintf(buf, "%d\n", temp);
1387 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1390 static struct attribute *ds3231_hwmon_attrs[] = {
1391 &sensor_dev_attr_temp1_input.dev_attr.attr,
1394 ATTRIBUTE_GROUPS(ds3231_hwmon);
1396 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1400 if (ds1307->type != ds_3231)
1403 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1405 ds3231_hwmon_groups);
1407 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1414 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1418 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1420 /*----------------------------------------------------------------------*/
1423 * Square-wave output support for DS3231
1424 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1426 #ifdef CONFIG_COMMON_CLK
1433 #define clk_sqw_to_ds1307(clk) \
1434 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1435 #define clk_32khz_to_ds1307(clk) \
1436 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1438 static int ds3231_clk_sqw_rates[] = {
1445 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1447 struct mutex *lock = &ds1307->rtc->ops_lock;
1451 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1458 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1459 unsigned long parent_rate)
1461 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1465 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1468 if (control & DS1337_BIT_RS1)
1470 if (control & DS1337_BIT_RS2)
1473 return ds3231_clk_sqw_rates[rate_sel];
1476 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1477 unsigned long *prate)
1481 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1482 if (ds3231_clk_sqw_rates[i] <= rate)
1483 return ds3231_clk_sqw_rates[i];
1489 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1490 unsigned long parent_rate)
1492 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1496 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1498 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1502 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1506 control |= DS1337_BIT_RS1;
1508 control |= DS1337_BIT_RS2;
1510 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1514 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1516 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1518 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1521 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1523 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1525 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1528 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1530 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1533 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1537 return !(control & DS1337_BIT_INTCN);
1540 static const struct clk_ops ds3231_clk_sqw_ops = {
1541 .prepare = ds3231_clk_sqw_prepare,
1542 .unprepare = ds3231_clk_sqw_unprepare,
1543 .is_prepared = ds3231_clk_sqw_is_prepared,
1544 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1545 .round_rate = ds3231_clk_sqw_round_rate,
1546 .set_rate = ds3231_clk_sqw_set_rate,
1549 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1550 unsigned long parent_rate)
1555 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1557 struct mutex *lock = &ds1307->rtc->ops_lock;
1561 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1563 enable ? DS3231_BIT_EN32KHZ : 0);
1569 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1571 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1573 return ds3231_clk_32khz_control(ds1307, true);
1576 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1578 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1580 ds3231_clk_32khz_control(ds1307, false);
1583 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1585 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1588 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1592 return !!(status & DS3231_BIT_EN32KHZ);
1595 static const struct clk_ops ds3231_clk_32khz_ops = {
1596 .prepare = ds3231_clk_32khz_prepare,
1597 .unprepare = ds3231_clk_32khz_unprepare,
1598 .is_prepared = ds3231_clk_32khz_is_prepared,
1599 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1602 static const char *ds3231_clks_names[] = {
1603 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1604 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1607 static struct clk_init_data ds3231_clks_init[] = {
1608 [DS3231_CLK_SQW] = {
1609 .ops = &ds3231_clk_sqw_ops,
1611 [DS3231_CLK_32KHZ] = {
1612 .ops = &ds3231_clk_32khz_ops,
1616 static int ds3231_clks_register(struct ds1307 *ds1307)
1618 struct device_node *node = ds1307->dev->of_node;
1619 struct clk_onecell_data *onecell;
1622 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1626 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1627 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1628 sizeof(onecell->clks[0]), GFP_KERNEL);
1632 /* optional override of the clockname */
1633 device_property_read_string_array(ds1307->dev, "clock-output-names",
1635 ARRAY_SIZE(ds3231_clks_names));
1637 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1638 struct clk_init_data init = ds3231_clks_init[i];
1641 * Interrupt signal due to alarm conditions and square-wave
1642 * output share same pin, so don't initialize both.
1644 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1647 init.name = ds3231_clks_names[i];
1648 ds1307->clks[i].init = &init;
1650 onecell->clks[i] = devm_clk_register(ds1307->dev,
1652 if (IS_ERR(onecell->clks[i]))
1653 return PTR_ERR(onecell->clks[i]);
1657 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1662 static void ds1307_clks_register(struct ds1307 *ds1307)
1666 if (ds1307->type != ds_3231)
1669 ret = ds3231_clks_register(ds1307);
1671 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1678 static void ds1307_clks_register(struct ds1307 *ds1307)
1682 #endif /* CONFIG_COMMON_CLK */
1684 #ifdef CONFIG_WATCHDOG_CORE
1685 static const struct watchdog_info ds1388_wdt_info = {
1686 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1687 .identity = "DS1388 watchdog",
1690 static const struct watchdog_ops ds1388_wdt_ops = {
1691 .owner = THIS_MODULE,
1692 .start = ds1388_wdt_start,
1693 .stop = ds1388_wdt_stop,
1694 .ping = ds1388_wdt_ping,
1695 .set_timeout = ds1388_wdt_set_timeout,
1699 static void ds1307_wdt_register(struct ds1307 *ds1307)
1701 struct watchdog_device *wdt;
1705 if (ds1307->type != ds_1388)
1708 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1712 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1713 if (!err && val & DS1388_BIT_WF)
1714 wdt->bootstatus = WDIOF_CARDRESET;
1716 wdt->info = &ds1388_wdt_info;
1717 wdt->ops = &ds1388_wdt_ops;
1719 wdt->max_timeout = 99;
1720 wdt->min_timeout = 1;
1722 watchdog_init_timeout(wdt, 0, ds1307->dev);
1723 watchdog_set_drvdata(wdt, ds1307);
1724 devm_watchdog_register_device(ds1307->dev, wdt);
1727 static void ds1307_wdt_register(struct ds1307 *ds1307)
1730 #endif /* CONFIG_WATCHDOG_CORE */
1732 static const struct regmap_config regmap_config = {
1737 static int ds1307_probe(struct i2c_client *client,
1738 const struct i2c_device_id *id)
1740 struct ds1307 *ds1307;
1744 const struct chip_desc *chip;
1746 bool ds1307_can_wakeup_device = false;
1747 unsigned char regs[8];
1748 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1749 u8 trickle_charger_setup = 0;
1751 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1755 dev_set_drvdata(&client->dev, ds1307);
1756 ds1307->dev = &client->dev;
1757 ds1307->name = client->name;
1759 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1760 if (IS_ERR(ds1307->regmap)) {
1761 dev_err(ds1307->dev, "regmap allocation failed\n");
1762 return PTR_ERR(ds1307->regmap);
1765 i2c_set_clientdata(client, ds1307);
1767 match = device_get_match_data(&client->dev);
1769 ds1307->type = (enum ds_type)match;
1770 chip = &chips[ds1307->type];
1772 chip = &chips[id->driver_data];
1773 ds1307->type = id->driver_data;
1778 want_irq = client->irq > 0 && chip->alarm;
1781 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1782 else if (pdata->trickle_charger_setup)
1783 trickle_charger_setup = pdata->trickle_charger_setup;
1785 if (trickle_charger_setup && chip->trickle_charger_reg) {
1786 dev_dbg(ds1307->dev,
1787 "writing trickle charger info 0x%x to 0x%x\n",
1788 trickle_charger_setup, chip->trickle_charger_reg);
1789 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1790 trickle_charger_setup);
1794 * For devices with no IRQ directly connected to the SoC, the RTC chip
1795 * can be forced as a wakeup source by stating that explicitly in
1796 * the device's .dts file using the "wakeup-source" boolean property.
1797 * If the "wakeup-source" property is set, don't request an IRQ.
1798 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1799 * if supported by the RTC.
1801 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1802 ds1307_can_wakeup_device = true;
1804 switch (ds1307->type) {
1809 /* get registers that the "rtc" read below won't read... */
1810 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1813 dev_dbg(ds1307->dev, "read error %d\n", err);
1817 /* oscillator off? turn it on, so clock can tick. */
1818 if (regs[0] & DS1337_BIT_nEOSC)
1819 regs[0] &= ~DS1337_BIT_nEOSC;
1822 * Using IRQ or defined as wakeup-source?
1823 * Disable the square wave and both alarms.
1824 * For some variants, be sure alarms can trigger when we're
1825 * running on Vbackup (BBSQI/BBSQW)
1827 if (want_irq || ds1307_can_wakeup_device) {
1828 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1829 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1832 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1835 /* oscillator fault? clear flag, and warn */
1836 if (regs[1] & DS1337_BIT_OSF) {
1837 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1838 regs[1] & ~DS1337_BIT_OSF);
1839 dev_warn(ds1307->dev, "SET TIME!\n");
1844 err = regmap_bulk_read(ds1307->regmap,
1845 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1847 dev_dbg(ds1307->dev, "read error %d\n", err);
1851 /* oscillator off? turn it on, so clock can tick. */
1852 if (!(regs[1] & RX8025_BIT_XST)) {
1853 regs[1] |= RX8025_BIT_XST;
1854 regmap_write(ds1307->regmap,
1855 RX8025_REG_CTRL2 << 4 | 0x08,
1857 dev_warn(ds1307->dev,
1858 "oscillator stop detected - SET TIME!\n");
1861 if (regs[1] & RX8025_BIT_PON) {
1862 regs[1] &= ~RX8025_BIT_PON;
1863 regmap_write(ds1307->regmap,
1864 RX8025_REG_CTRL2 << 4 | 0x08,
1866 dev_warn(ds1307->dev, "power-on detected\n");
1869 if (regs[1] & RX8025_BIT_VDET) {
1870 regs[1] &= ~RX8025_BIT_VDET;
1871 regmap_write(ds1307->regmap,
1872 RX8025_REG_CTRL2 << 4 | 0x08,
1874 dev_warn(ds1307->dev, "voltage drop detected\n");
1877 /* make sure we are running in 24hour mode */
1878 if (!(regs[0] & RX8025_BIT_2412)) {
1881 /* switch to 24 hour mode */
1882 regmap_write(ds1307->regmap,
1883 RX8025_REG_CTRL1 << 4 | 0x08,
1884 regs[0] | RX8025_BIT_2412);
1886 err = regmap_bulk_read(ds1307->regmap,
1887 RX8025_REG_CTRL1 << 4 | 0x08,
1890 dev_dbg(ds1307->dev, "read error %d\n", err);
1895 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1898 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1901 regmap_write(ds1307->regmap,
1902 DS1307_REG_HOUR << 4 | 0x08, hour);
1906 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1908 dev_dbg(ds1307->dev, "read error %d\n", err);
1912 /* oscillator off? turn it on, so clock can tick. */
1913 if (tmp & DS1388_BIT_nEOSC) {
1914 tmp &= ~DS1388_BIT_nEOSC;
1915 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1922 /* read RTC registers */
1923 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1926 dev_dbg(ds1307->dev, "read error %d\n", err);
1930 if (ds1307->type == mcp794xx &&
1931 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1932 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1933 regs[DS1307_REG_WDAY] |
1934 MCP794XX_BIT_VBATEN);
1937 tmp = regs[DS1307_REG_HOUR];
1938 switch (ds1307->type) {
1944 * NOTE: ignores century bits; fix before deploying
1945 * systems that will run through year 2100.
1951 if (!(tmp & DS1307_BIT_12HR))
1955 * Be sure we're in 24 hour mode. Multi-master systems
1958 tmp = bcd2bin(tmp & 0x1f);
1961 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1963 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1967 if (want_irq || ds1307_can_wakeup_device) {
1968 device_set_wakeup_capable(ds1307->dev, true);
1969 set_bit(HAS_ALARM, &ds1307->flags);
1972 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1973 if (IS_ERR(ds1307->rtc))
1974 return PTR_ERR(ds1307->rtc);
1976 if (ds1307_can_wakeup_device && !want_irq) {
1977 dev_info(ds1307->dev,
1978 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1979 /* We cannot support UIE mode if we do not have an IRQ line */
1980 ds1307->rtc->uie_unsupported = 1;
1984 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1985 chip->irq_handler ?: ds1307_irq,
1986 IRQF_SHARED | IRQF_ONESHOT,
1987 ds1307->name, ds1307);
1990 device_set_wakeup_capable(ds1307->dev, false);
1991 clear_bit(HAS_ALARM, &ds1307->flags);
1992 dev_err(ds1307->dev, "unable to request IRQ!\n");
1994 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1998 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1999 err = ds1307_add_frequency_test(ds1307);
2003 err = devm_rtc_register_device(ds1307->rtc);
2007 if (chip->nvram_size) {
2008 struct nvmem_config nvmem_cfg = {
2009 .name = "ds1307_nvram",
2012 .size = chip->nvram_size,
2013 .reg_read = ds1307_nvram_read,
2014 .reg_write = ds1307_nvram_write,
2018 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
2021 ds1307_hwmon_register(ds1307);
2022 ds1307_clks_register(ds1307);
2023 ds1307_wdt_register(ds1307);
2031 static struct i2c_driver ds1307_driver = {
2033 .name = "rtc-ds1307",
2034 .of_match_table = ds1307_of_match,
2036 .probe = ds1307_probe,
2037 .id_table = ds1307_id,
2040 module_i2c_driver(ds1307_driver);
2042 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2043 MODULE_LICENSE("GPL");