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[linux-2.6-microblaze.git] / drivers / reset / reset-lpc18xx.c
1 /*
2  * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
3  *
4  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/init.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/reboot.h>
20 #include <linux/reset-controller.h>
21 #include <linux/spinlock.h>
22
23 /* LPC18xx RGU registers */
24 #define LPC18XX_RGU_CTRL0               0x100
25 #define LPC18XX_RGU_CTRL1               0x104
26 #define LPC18XX_RGU_ACTIVE_STATUS0      0x150
27 #define LPC18XX_RGU_ACTIVE_STATUS1      0x154
28
29 #define LPC18XX_RGU_RESETS_PER_REG      32
30
31 /* Internal reset outputs */
32 #define LPC18XX_RGU_CORE_RST    0
33 #define LPC43XX_RGU_M0SUB_RST   12
34 #define LPC43XX_RGU_M0APP_RST   56
35
36 struct lpc18xx_rgu_data {
37         struct reset_controller_dev rcdev;
38         struct notifier_block restart_nb;
39         struct clk *clk_delay;
40         struct clk *clk_reg;
41         void __iomem *base;
42         spinlock_t lock;
43         u32 delay_us;
44 };
45
46 #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
47
48 static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode,
49                                void *cmd)
50 {
51         struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data,
52                                                    restart_nb);
53
54         writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
55         mdelay(2000);
56
57         pr_emerg("%s: unable to restart system\n", __func__);
58
59         return NOTIFY_DONE;
60 }
61
62 /*
63  * The LPC18xx RGU has mostly self-deasserting resets except for the
64  * two reset lines going to the internal Cortex-M0 cores.
65  *
66  * To prevent the M0 core resets from accidentally getting deasserted
67  * status register must be check and bits in control register set to
68  * preserve the state.
69  */
70 static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
71                                       unsigned long id, bool set)
72 {
73         struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
74         u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
75         u32 ctrl_offset = LPC18XX_RGU_CTRL0;
76         unsigned long flags;
77         u32 stat, rst_bit;
78
79         stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
80         ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
81         rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
82
83         spin_lock_irqsave(&rc->lock, flags);
84         stat = ~readl(rc->base + stat_offset);
85         if (set)
86                 writel(stat | rst_bit, rc->base + ctrl_offset);
87         else
88                 writel(stat & ~rst_bit, rc->base + ctrl_offset);
89         spin_unlock_irqrestore(&rc->lock, flags);
90
91         return 0;
92 }
93
94 static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
95                               unsigned long id)
96 {
97         return lpc18xx_rgu_setclear_reset(rcdev, id, true);
98 }
99
100 static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
101                                 unsigned long id)
102 {
103         return lpc18xx_rgu_setclear_reset(rcdev, id, false);
104 }
105
106 /* Only M0 cores require explicit reset deassert */
107 static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
108                              unsigned long id)
109 {
110         struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
111
112         lpc18xx_rgu_assert(rcdev, id);
113         udelay(rc->delay_us);
114
115         switch (id) {
116         case LPC43XX_RGU_M0SUB_RST:
117         case LPC43XX_RGU_M0APP_RST:
118                 lpc18xx_rgu_setclear_reset(rcdev, id, false);
119         }
120
121         return 0;
122 }
123
124 static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
125                               unsigned long id)
126 {
127         struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
128         u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
129
130         offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
131         bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
132
133         return !(readl(rc->base + offset) & bit);
134 }
135
136 static const struct reset_control_ops lpc18xx_rgu_ops = {
137         .reset          = lpc18xx_rgu_reset,
138         .assert         = lpc18xx_rgu_assert,
139         .deassert       = lpc18xx_rgu_deassert,
140         .status         = lpc18xx_rgu_status,
141 };
142
143 static int lpc18xx_rgu_probe(struct platform_device *pdev)
144 {
145         struct lpc18xx_rgu_data *rc;
146         struct resource *res;
147         u32 fcclk, firc;
148         int ret;
149
150         rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
151         if (!rc)
152                 return -ENOMEM;
153
154         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
155         rc->base = devm_ioremap_resource(&pdev->dev, res);
156         if (IS_ERR(rc->base))
157                 return PTR_ERR(rc->base);
158
159         rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
160         if (IS_ERR(rc->clk_reg)) {
161                 dev_err(&pdev->dev, "reg clock not found\n");
162                 return PTR_ERR(rc->clk_reg);
163         }
164
165         rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
166         if (IS_ERR(rc->clk_delay)) {
167                 dev_err(&pdev->dev, "delay clock not found\n");
168                 return PTR_ERR(rc->clk_delay);
169         }
170
171         ret = clk_prepare_enable(rc->clk_reg);
172         if (ret) {
173                 dev_err(&pdev->dev, "unable to enable reg clock\n");
174                 return ret;
175         }
176
177         ret = clk_prepare_enable(rc->clk_delay);
178         if (ret) {
179                 dev_err(&pdev->dev, "unable to enable delay clock\n");
180                 goto dis_clk_reg;
181         }
182
183         fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
184         firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
185         if (fcclk == 0 || firc == 0)
186                 rc->delay_us = 2;
187         else
188                 rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
189
190         spin_lock_init(&rc->lock);
191
192         rc->rcdev.owner = THIS_MODULE;
193         rc->rcdev.nr_resets = 64;
194         rc->rcdev.ops = &lpc18xx_rgu_ops;
195         rc->rcdev.of_node = pdev->dev.of_node;
196
197         platform_set_drvdata(pdev, rc);
198
199         ret = reset_controller_register(&rc->rcdev);
200         if (ret) {
201                 dev_err(&pdev->dev, "unable to register device\n");
202                 goto dis_clks;
203         }
204
205         rc->restart_nb.priority = 192,
206         rc->restart_nb.notifier_call = lpc18xx_rgu_restart,
207         ret = register_restart_handler(&rc->restart_nb);
208         if (ret)
209                 dev_warn(&pdev->dev, "failed to register restart handler\n");
210
211         return 0;
212
213 dis_clks:
214         clk_disable_unprepare(rc->clk_delay);
215 dis_clk_reg:
216         clk_disable_unprepare(rc->clk_reg);
217
218         return ret;
219 }
220
221 static const struct of_device_id lpc18xx_rgu_match[] = {
222         { .compatible = "nxp,lpc1850-rgu" },
223         { }
224 };
225
226 static struct platform_driver lpc18xx_rgu_driver = {
227         .probe  = lpc18xx_rgu_probe,
228         .driver = {
229                 .name                   = "lpc18xx-reset",
230                 .of_match_table         = lpc18xx_rgu_match,
231                 .suppress_bind_attrs    = true,
232         },
233 };
234 builtin_platform_driver(lpc18xx_rgu_driver);