1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI K3 R5F (MCU) Remote Processor driver
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/mailbox_client.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/omap-mailbox.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/remoteproc.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
25 #include "omap_remoteproc.h"
26 #include "remoteproc_internal.h"
27 #include "ti_sci_proc.h"
29 /* This address can either be for ATCM or BTCM with the other at address 0x0 */
30 #define K3_R5_TCM_DEV_ADDR 0x41010000
32 /* R5 TI-SCI Processor Configuration Flags */
33 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
34 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
35 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
36 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
37 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
38 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
39 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
40 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
41 /* Available from J7200 SoCs onwards */
42 #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
43 /* Applicable to only AM64x SoCs */
44 #define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000
46 /* R5 TI-SCI Processor Control Flags */
47 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
49 /* R5 TI-SCI Processor Status Flags */
50 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
51 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
52 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
53 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
54 /* Applicable to only AM64x SoCs */
55 #define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x00000200
58 * struct k3_r5_mem - internal memory structure
59 * @cpu_addr: MPU virtual address of the memory region
60 * @bus_addr: Bus address used to access the memory region
61 * @dev_addr: Device address from remoteproc view
62 * @size: Size of the memory region
65 void __iomem *cpu_addr;
72 * All cluster mode values are not applicable on all SoCs. The following
73 * are the modes supported on various SoCs:
74 * Split mode : AM65x, J721E, J7200 and AM64x SoCs
75 * LockStep mode : AM65x, J721E and J7200 SoCs
76 * Single-CPU mode : AM64x SoCs only
79 CLUSTER_MODE_SPLIT = 0,
80 CLUSTER_MODE_LOCKSTEP,
81 CLUSTER_MODE_SINGLECPU,
85 * struct k3_r5_soc_data - match data to handle SoC variations
86 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
87 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
88 * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode
90 struct k3_r5_soc_data {
92 bool tcm_ecc_autoinit;
97 * struct k3_r5_cluster - K3 R5F Cluster structure
98 * @dev: cached device pointer
99 * @mode: Mode to configure the Cluster - Split or LockStep
100 * @cores: list of R5 cores within the cluster
101 * @soc_data: SoC-specific feature data for a R5FSS
103 struct k3_r5_cluster {
105 enum cluster_mode mode;
106 struct list_head cores;
107 const struct k3_r5_soc_data *soc_data;
111 * struct k3_r5_core - K3 R5 core structure
112 * @elem: linked list item
113 * @dev: cached device pointer
114 * @rproc: rproc handle representing this core
115 * @mem: internal memory regions data
116 * @sram: on-chip SRAM memory regions data
117 * @num_mems: number of internal memory regions
118 * @num_sram: number of on-chip SRAM memory regions
119 * @reset: reset control handle
120 * @tsp: TI-SCI processor control handle
121 * @ti_sci: TI-SCI handle
122 * @ti_sci_id: TI-SCI device identifier
123 * @atcm_enable: flag to control ATCM enablement
124 * @btcm_enable: flag to control BTCM enablement
125 * @loczrama: flag to dictate which TCM is at device address 0x0
128 struct list_head elem;
131 struct k3_r5_mem *mem;
132 struct k3_r5_mem *sram;
135 struct reset_control *reset;
136 struct ti_sci_proc *tsp;
137 const struct ti_sci_handle *ti_sci;
145 * struct k3_r5_rproc - K3 remote processor state
146 * @dev: cached device pointer
147 * @cluster: cached pointer to parent cluster structure
148 * @mbox: mailbox channel handle
149 * @client: mailbox client to request the mailbox channel
150 * @rproc: rproc handle
151 * @core: cached pointer to r5 core structure being used
152 * @rmem: reserved memory regions data
153 * @num_rmems: number of reserved memory regions
157 struct k3_r5_cluster *cluster;
158 struct mbox_chan *mbox;
159 struct mbox_client client;
161 struct k3_r5_core *core;
162 struct k3_r5_mem *rmem;
167 * k3_r5_rproc_mbox_callback() - inbound mailbox message handler
168 * @client: mailbox client pointer used for requesting the mailbox channel
169 * @data: mailbox payload
171 * This handler is invoked by the OMAP mailbox driver whenever a mailbox
172 * message is received. Usually, the mailbox payload simply contains
173 * the index of the virtqueue that is kicked by the remote processor,
174 * and we let remoteproc core handle it.
176 * In addition to virtqueue indices, we also have some out-of-band values
177 * that indicate different events. Those values are deliberately very
178 * large so they don't coincide with virtqueue indices.
180 static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data)
182 struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc,
184 struct device *dev = kproc->rproc->dev.parent;
185 const char *name = kproc->rproc->name;
186 u32 msg = omap_mbox_message(data);
188 dev_dbg(dev, "mbox msg: 0x%x\n", msg);
193 * remoteproc detected an exception, but error recovery is not
194 * supported. So, just log this for now
196 dev_err(dev, "K3 R5F rproc %s crashed\n", name);
198 case RP_MBOX_ECHO_REPLY:
199 dev_info(dev, "received echo reply from %s\n", name);
202 /* silently handle all other valid messages */
203 if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG)
205 if (msg > kproc->rproc->max_notifyid) {
206 dev_dbg(dev, "dropping unknown message 0x%x", msg);
209 /* msg contains the index of the triggered vring */
210 if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE)
211 dev_dbg(dev, "no message was found in vqid %d\n", msg);
215 /* kick a virtqueue */
216 static void k3_r5_rproc_kick(struct rproc *rproc, int vqid)
218 struct k3_r5_rproc *kproc = rproc->priv;
219 struct device *dev = rproc->dev.parent;
220 mbox_msg_t msg = (mbox_msg_t)vqid;
223 /* send the index of the triggered virtqueue in the mailbox payload */
224 ret = mbox_send_message(kproc->mbox, (void *)msg);
226 dev_err(dev, "failed to send mailbox message, status = %d\n",
230 static int k3_r5_split_reset(struct k3_r5_core *core)
234 ret = reset_control_assert(core->reset);
236 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
241 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
244 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
246 if (reset_control_deassert(core->reset))
247 dev_warn(core->dev, "local-reset deassert back failed\n");
253 static int k3_r5_split_release(struct k3_r5_core *core)
257 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
260 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
265 ret = reset_control_deassert(core->reset);
267 dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
269 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
271 dev_warn(core->dev, "module-reset assert back failed\n");
277 static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)
279 struct k3_r5_core *core;
282 /* assert local reset on all applicable cores */
283 list_for_each_entry(core, &cluster->cores, elem) {
284 ret = reset_control_assert(core->reset);
286 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
288 core = list_prev_entry(core, elem);
289 goto unroll_local_reset;
293 /* disable PSC modules on all applicable cores */
294 list_for_each_entry(core, &cluster->cores, elem) {
295 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
298 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
300 goto unroll_module_reset;
307 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {
308 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
310 dev_warn(core->dev, "module-reset assert back failed\n");
312 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
314 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
315 if (reset_control_deassert(core->reset))
316 dev_warn(core->dev, "local-reset deassert back failed\n");
322 static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)
324 struct k3_r5_core *core;
327 /* enable PSC modules on all applicable cores */
328 list_for_each_entry_reverse(core, &cluster->cores, elem) {
329 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
332 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
334 core = list_next_entry(core, elem);
335 goto unroll_module_reset;
339 /* deassert local reset on all applicable cores */
340 list_for_each_entry_reverse(core, &cluster->cores, elem) {
341 ret = reset_control_deassert(core->reset);
343 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
345 goto unroll_local_reset;
352 list_for_each_entry_continue(core, &cluster->cores, elem) {
353 if (reset_control_assert(core->reset))
354 dev_warn(core->dev, "local-reset assert back failed\n");
356 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
358 list_for_each_entry_from(core, &cluster->cores, elem) {
359 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
361 dev_warn(core->dev, "module-reset assert back failed\n");
367 static inline int k3_r5_core_halt(struct k3_r5_core *core)
369 return ti_sci_proc_set_control(core->tsp,
370 PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
373 static inline int k3_r5_core_run(struct k3_r5_core *core)
375 return ti_sci_proc_set_control(core->tsp,
376 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
379 static int k3_r5_rproc_request_mbox(struct rproc *rproc)
381 struct k3_r5_rproc *kproc = rproc->priv;
382 struct mbox_client *client = &kproc->client;
383 struct device *dev = kproc->dev;
387 client->tx_done = NULL;
388 client->rx_callback = k3_r5_rproc_mbox_callback;
389 client->tx_block = false;
390 client->knows_txdone = false;
392 kproc->mbox = mbox_request_channel(client, 0);
393 if (IS_ERR(kproc->mbox)) {
395 dev_err(dev, "mbox_request_channel failed: %ld\n",
396 PTR_ERR(kproc->mbox));
401 * Ping the remote processor, this is only for sanity-sake for now;
402 * there is no functional effect whatsoever.
404 * Note that the reply will _not_ arrive immediately: this message
405 * will wait in the mailbox fifo until the remote processor is booted.
407 ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST);
409 dev_err(dev, "mbox_send_message failed: %d\n", ret);
410 mbox_free_channel(kproc->mbox);
418 * The R5F cores have controls for both a reset and a halt/run. The code
419 * execution from DDR requires the initial boot-strapping code to be run
420 * from the internal TCMs. This function is used to release the resets on
421 * applicable cores to allow loading into the TCMs. The .prepare() ops is
422 * invoked by remoteproc core before any firmware loading, and is followed
423 * by the .start() ops after loading to actually let the R5 cores run.
425 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
426 * execute code, but combines the TCMs from both cores. The resets for both
427 * cores need to be released to make this possible, as the TCMs are in general
428 * private to each core. Only Core0 needs to be unhalted for running the
429 * cluster in this mode. The function uses the same reset logic as LockStep
430 * mode for this (though the behavior is agnostic of the reset release order).
431 * This callback is invoked only in remoteproc mode.
433 static int k3_r5_rproc_prepare(struct rproc *rproc)
435 struct k3_r5_rproc *kproc = rproc->priv;
436 struct k3_r5_cluster *cluster = kproc->cluster;
437 struct k3_r5_core *core = kproc->core;
438 struct device *dev = kproc->dev;
439 u32 ctrl = 0, cfg = 0, stat = 0;
444 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat);
447 mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
449 /* Re-use LockStep-mode reset logic for Single-CPU mode */
450 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
451 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
452 k3_r5_lockstep_release(cluster) : k3_r5_split_release(core);
454 dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",
460 * Newer IP revisions like on J7200 SoCs support h/w auto-initialization
461 * of TCMs, so there is no need to perform the s/w memzero. This bit is
462 * configurable through System Firmware, the default value does perform
463 * auto-init, but account for it in case it is disabled
465 if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) {
466 dev_dbg(dev, "leveraging h/w init for TCM memories\n");
471 * Zero out both TCMs unconditionally (access from v8 Arm core is not
472 * affected by ATCM & BTCM enable configuration values) so that ECC
473 * can be effective on all TCM addresses.
475 dev_dbg(dev, "zeroing out ATCM memory\n");
476 memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
478 dev_dbg(dev, "zeroing out BTCM memory\n");
479 memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
485 * This function implements the .unprepare() ops and performs the complimentary
486 * operations to that of the .prepare() ops. The function is used to assert the
487 * resets on all applicable cores for the rproc device (depending on LockStep
488 * or Split mode). This completes the second portion of powering down the R5F
489 * cores. The cores themselves are only halted in the .stop() ops, and the
490 * .unprepare() ops is invoked by the remoteproc core after the remoteproc is
493 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from
494 * both cores. The access is made possible only with releasing the resets for
495 * both cores, but with only Core0 unhalted. This function re-uses the same
496 * reset assert logic as LockStep mode for this mode (though the behavior is
497 * agnostic of the reset assert order). This callback is invoked only in
500 static int k3_r5_rproc_unprepare(struct rproc *rproc)
502 struct k3_r5_rproc *kproc = rproc->priv;
503 struct k3_r5_cluster *cluster = kproc->cluster;
504 struct k3_r5_core *core = kproc->core;
505 struct device *dev = kproc->dev;
508 /* Re-use LockStep-mode reset logic for Single-CPU mode */
509 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
510 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
511 k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core);
513 dev_err(dev, "unable to disable cores, ret = %d\n", ret);
519 * The R5F start sequence includes two different operations
520 * 1. Configure the boot vector for R5F core(s)
521 * 2. Unhalt/Run the R5F core(s)
523 * The sequence is different between LockStep and Split modes. The LockStep
524 * mode requires the boot vector to be configured only for Core0, and then
525 * unhalt both the cores to start the execution - Core1 needs to be unhalted
526 * first followed by Core0. The Split-mode requires that Core0 to be maintained
527 * always in a higher power state that Core1 (implying Core1 needs to be started
528 * always only after Core0 is started).
530 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
531 * code, so only Core0 needs to be unhalted. The function uses the same logic
532 * flow as Split-mode for this. This callback is invoked only in remoteproc
535 static int k3_r5_rproc_start(struct rproc *rproc)
537 struct k3_r5_rproc *kproc = rproc->priv;
538 struct k3_r5_cluster *cluster = kproc->cluster;
539 struct device *dev = kproc->dev;
540 struct k3_r5_core *core;
544 ret = k3_r5_rproc_request_mbox(rproc);
548 boot_addr = rproc->bootaddr;
549 /* TODO: add boot_addr sanity checking */
550 dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);
552 /* boot vector need not be programmed for Core1 in LockStep mode */
554 ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0);
558 /* unhalt/run all applicable cores */
559 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
560 list_for_each_entry_reverse(core, &cluster->cores, elem) {
561 ret = k3_r5_core_run(core);
563 goto unroll_core_run;
566 ret = k3_r5_core_run(core);
574 list_for_each_entry_continue(core, &cluster->cores, elem) {
575 if (k3_r5_core_halt(core))
576 dev_warn(core->dev, "core halt back failed\n");
579 mbox_free_channel(kproc->mbox);
584 * The R5F stop function includes the following operations
585 * 1. Halt R5F core(s)
587 * The sequence is different between LockStep and Split modes, and the order
588 * of cores the operations are performed are also in general reverse to that
589 * of the start function. The LockStep mode requires each operation to be
590 * performed first on Core0 followed by Core1. The Split-mode requires that
591 * Core0 to be maintained always in a higher power state that Core1 (implying
592 * Core1 needs to be stopped first before Core0).
594 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
595 * code, so only Core0 needs to be halted. The function uses the same logic
596 * flow as Split-mode for this.
598 * Note that the R5F halt operation in general is not effective when the R5F
599 * core is running, but is needed to make sure the core won't run after
600 * deasserting the reset the subsequent time. The asserting of reset can
601 * be done here, but is preferred to be done in the .unprepare() ops - this
602 * maintains the symmetric behavior between the .start(), .stop(), .prepare()
603 * and .unprepare() ops, and also balances them well between sysfs 'state'
604 * flow and device bind/unbind or module removal. This callback is invoked
605 * only in remoteproc mode.
607 static int k3_r5_rproc_stop(struct rproc *rproc)
609 struct k3_r5_rproc *kproc = rproc->priv;
610 struct k3_r5_cluster *cluster = kproc->cluster;
611 struct k3_r5_core *core = kproc->core;
614 /* halt all applicable cores */
615 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
616 list_for_each_entry(core, &cluster->cores, elem) {
617 ret = k3_r5_core_halt(core);
619 core = list_prev_entry(core, elem);
620 goto unroll_core_halt;
624 ret = k3_r5_core_halt(core);
629 mbox_free_channel(kproc->mbox);
634 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
635 if (k3_r5_core_run(core))
636 dev_warn(core->dev, "core run back failed\n");
643 * Attach to a running R5F remote processor (IPC-only mode)
645 * The R5F attach callback only needs to request the mailbox, the remote
646 * processor is already booted, so there is no need to issue any TI-SCI
647 * commands to boot the R5F cores in IPC-only mode. This callback is invoked
648 * only in IPC-only mode.
650 static int k3_r5_rproc_attach(struct rproc *rproc)
652 struct k3_r5_rproc *kproc = rproc->priv;
653 struct device *dev = kproc->dev;
656 ret = k3_r5_rproc_request_mbox(rproc);
660 dev_info(dev, "R5F core initialized in IPC-only mode\n");
665 * Detach from a running R5F remote processor (IPC-only mode)
667 * The R5F detach callback performs the opposite operation to attach callback
668 * and only needs to release the mailbox, the R5F cores are not stopped and
669 * will be left in booted state in IPC-only mode. This callback is invoked
670 * only in IPC-only mode.
672 static int k3_r5_rproc_detach(struct rproc *rproc)
674 struct k3_r5_rproc *kproc = rproc->priv;
675 struct device *dev = kproc->dev;
677 mbox_free_channel(kproc->mbox);
678 dev_info(dev, "R5F core deinitialized in IPC-only mode\n");
683 * This function implements the .get_loaded_rsc_table() callback and is used
684 * to provide the resource table for the booted R5F in IPC-only mode. The K3 R5F
685 * firmwares follow a design-by-contract approach and are expected to have the
686 * resource table at the base of the DDR region reserved for firmware usage.
687 * This provides flexibility for the remote processor to be booted by different
688 * bootloaders that may or may not have the ability to publish the resource table
689 * address and size through a DT property. This callback is invoked only in
692 static struct resource_table *k3_r5_get_loaded_rsc_table(struct rproc *rproc,
693 size_t *rsc_table_sz)
695 struct k3_r5_rproc *kproc = rproc->priv;
696 struct device *dev = kproc->dev;
698 if (!kproc->rmem[0].cpu_addr) {
699 dev_err(dev, "memory-region #1 does not exist, loaded rsc table can't be found");
700 return ERR_PTR(-ENOMEM);
704 * NOTE: The resource table size is currently hard-coded to a maximum
705 * of 256 bytes. The most common resource table usage for K3 firmwares
706 * is to only have the vdev resource entry and an optional trace entry.
707 * The exact size could be computed based on resource table address, but
708 * the hard-coded value suffices to support the IPC-only mode.
711 return (struct resource_table *)kproc->rmem[0].cpu_addr;
715 * Internal Memory translation helper
717 * Custom function implementing the rproc .da_to_va ops to provide address
718 * translation (device address to kernel virtual address) for internal RAMs
719 * present in a DSP or IPU device). The translated addresses can be used
720 * either by the remoteproc core for loading, or by any rpmsg bus drivers.
722 static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
724 struct k3_r5_rproc *kproc = rproc->priv;
725 struct k3_r5_core *core = kproc->core;
726 void __iomem *va = NULL;
727 phys_addr_t bus_addr;
728 u32 dev_addr, offset;
735 /* handle both R5 and SoC views of ATCM and BTCM */
736 for (i = 0; i < core->num_mems; i++) {
737 bus_addr = core->mem[i].bus_addr;
738 dev_addr = core->mem[i].dev_addr;
739 size = core->mem[i].size;
741 /* handle R5-view addresses of TCMs */
742 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
743 offset = da - dev_addr;
744 va = core->mem[i].cpu_addr + offset;
745 return (__force void *)va;
748 /* handle SoC-view addresses of TCMs */
749 if (da >= bus_addr && ((da + len) <= (bus_addr + size))) {
750 offset = da - bus_addr;
751 va = core->mem[i].cpu_addr + offset;
752 return (__force void *)va;
756 /* handle any SRAM regions using SoC-view addresses */
757 for (i = 0; i < core->num_sram; i++) {
758 dev_addr = core->sram[i].dev_addr;
759 size = core->sram[i].size;
761 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
762 offset = da - dev_addr;
763 va = core->sram[i].cpu_addr + offset;
764 return (__force void *)va;
768 /* handle static DDR reserved memory regions */
769 for (i = 0; i < kproc->num_rmems; i++) {
770 dev_addr = kproc->rmem[i].dev_addr;
771 size = kproc->rmem[i].size;
773 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
774 offset = da - dev_addr;
775 va = kproc->rmem[i].cpu_addr + offset;
776 return (__force void *)va;
783 static const struct rproc_ops k3_r5_rproc_ops = {
784 .prepare = k3_r5_rproc_prepare,
785 .unprepare = k3_r5_rproc_unprepare,
786 .start = k3_r5_rproc_start,
787 .stop = k3_r5_rproc_stop,
788 .kick = k3_r5_rproc_kick,
789 .da_to_va = k3_r5_rproc_da_to_va,
793 * Internal R5F Core configuration
795 * Each R5FSS has a cluster-level setting for configuring the processor
796 * subsystem either in a safety/fault-tolerant LockStep mode or a performance
797 * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode
798 * as an alternate for LockStep mode that exercises only a single R5F core
799 * called Single-CPU mode. Each R5F core has a number of settings to either
800 * enable/disable each of the TCMs, control which TCM appears at the R5F core's
801 * address 0x0. These settings need to be configured before the resets for the
802 * corresponding core are released. These settings are all protected and managed
803 * by the System Processor.
805 * This function is used to pre-configure these settings for each R5F core, and
806 * the configuration is all done through various ti_sci_proc functions that
807 * communicate with the System Processor. The function also ensures that both
808 * the cores are halted before the .prepare() step.
810 * The function is called from k3_r5_cluster_rproc_init() and is invoked either
811 * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support
812 * for LockStep-mode is dictated by an eFUSE register bit, and the config
813 * settings retrieved from DT are adjusted accordingly as per the permitted
814 * cluster mode. Another eFUSE register bit dictates if the R5F cluster only
815 * supports a Single-CPU mode. All cluster level settings like Cluster mode and
816 * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set
817 * and retrieved using Core0.
819 * The function behavior is different based on the cluster mode. The R5F cores
820 * are configured independently as per their individual settings in Split mode.
821 * They are identically configured in LockStep mode using the primary Core0
822 * settings. However, some individual settings cannot be set in LockStep mode.
823 * This is overcome by switching to Split-mode initially and then programming
824 * both the cores with the same settings, before reconfiguing again for
827 static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc)
829 struct k3_r5_cluster *cluster = kproc->cluster;
830 struct device *dev = kproc->dev;
831 struct k3_r5_core *core0, *core, *temp;
832 u32 ctrl = 0, cfg = 0, stat = 0;
833 u32 set_cfg = 0, clr_cfg = 0;
839 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
840 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
841 cluster->mode == CLUSTER_MODE_SINGLECPU) {
847 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
852 dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",
853 boot_vec, cfg, ctrl, stat);
855 /* check if only Single-CPU mode is supported on applicable SoCs */
856 if (cluster->soc_data->single_cpu_mode) {
858 !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY);
859 if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) {
860 dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n");
861 cluster->mode = CLUSTER_MODE_SINGLECPU;
866 /* check conventional LockStep vs Split mode configuration */
867 lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
868 if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {
869 dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");
870 cluster->mode = CLUSTER_MODE_SPLIT;
874 /* always enable ARM mode and set boot vector to 0 */
877 clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;
878 if (cluster->soc_data->single_cpu_mode) {
880 * Single-CPU configuration bit can only be configured
881 * on Core0 and system firmware will NACK any requests
882 * with the bit configured, so program it only on
885 if (cluster->mode == CLUSTER_MODE_SINGLECPU)
886 set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;
889 * LockStep configuration bit is Read-only on Split-mode
890 * _only_ devices and system firmware will NACK any
891 * requests with the bit configured, so program it only
892 * on permitted devices
895 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
899 if (core->atcm_enable)
900 set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
902 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
904 if (core->btcm_enable)
905 set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
907 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
910 set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
912 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
914 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
916 * work around system firmware limitations to make sure both
917 * cores are programmed symmetrically in LockStep. LockStep
918 * and TEINIT config is only allowed with Core0.
920 list_for_each_entry(temp, &cluster->cores, elem) {
921 ret = k3_r5_core_halt(temp);
926 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
927 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;
929 ret = ti_sci_proc_set_config(temp->tsp, boot_vec,
935 set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
937 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
940 ret = k3_r5_core_halt(core);
944 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
952 static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)
954 struct device *dev = kproc->dev;
955 struct device_node *np = dev_of_node(dev);
956 struct device_node *rmem_np;
957 struct reserved_mem *rmem;
961 num_rmems = of_property_count_elems_of_size(np, "memory-region",
963 if (num_rmems <= 0) {
964 dev_err(dev, "device does not have reserved memory regions, ret = %d\n",
969 dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",
974 /* use reserved memory region 0 for vring DMA allocations */
975 ret = of_reserved_mem_device_init_by_idx(dev, np, 0);
977 dev_err(dev, "device cannot initialize DMA pool, ret = %d\n",
983 kproc->rmem = kcalloc(num_rmems, sizeof(*kproc->rmem), GFP_KERNEL);
989 /* use remaining reserved memory regions for static carveouts */
990 for (i = 0; i < num_rmems; i++) {
991 rmem_np = of_parse_phandle(np, "memory-region", i + 1);
997 rmem = of_reserved_mem_lookup(rmem_np);
999 of_node_put(rmem_np);
1003 of_node_put(rmem_np);
1005 kproc->rmem[i].bus_addr = rmem->base;
1007 * R5Fs do not have an MMU, but have a Region Address Translator
1008 * (RAT) module that provides a fixed entry translation between
1009 * the 32-bit processor addresses to 64-bit bus addresses. The
1010 * RAT is programmable only by the R5F cores. Support for RAT
1011 * is currently not supported, so 64-bit address regions are not
1012 * supported. The absence of MMUs implies that the R5F device
1013 * addresses/supported memory regions are restricted to 32-bit
1014 * bus addresses, and are identical
1016 kproc->rmem[i].dev_addr = (u32)rmem->base;
1017 kproc->rmem[i].size = rmem->size;
1018 kproc->rmem[i].cpu_addr = ioremap_wc(rmem->base, rmem->size);
1019 if (!kproc->rmem[i].cpu_addr) {
1020 dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n",
1021 i + 1, &rmem->base, &rmem->size);
1026 dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1027 i + 1, &kproc->rmem[i].bus_addr,
1028 kproc->rmem[i].size, kproc->rmem[i].cpu_addr,
1029 kproc->rmem[i].dev_addr);
1031 kproc->num_rmems = num_rmems;
1036 for (i--; i >= 0; i--)
1037 iounmap(kproc->rmem[i].cpu_addr);
1040 of_reserved_mem_device_release(dev);
1044 static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc)
1048 for (i = 0; i < kproc->num_rmems; i++)
1049 iounmap(kproc->rmem[i].cpu_addr);
1052 of_reserved_mem_device_release(kproc->dev);
1056 * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
1057 * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
1058 * cores are usable in Split-mode, but only the Core0 TCMs can be used in
1059 * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
1060 * leveraging the Core1 TCMs as well in certain modes where they would have
1061 * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on
1062 * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the
1063 * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for
1064 * the Core0 TCMs, and the dts representation reflects this increased size on
1065 * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only
1066 * half the original size in Split mode.
1068 static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc)
1070 struct k3_r5_cluster *cluster = kproc->cluster;
1071 struct k3_r5_core *core = kproc->core;
1072 struct device *cdev = core->dev;
1073 struct k3_r5_core *core0;
1075 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1076 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1077 !cluster->soc_data->tcm_is_double)
1080 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1081 if (core == core0) {
1082 WARN_ON(core->mem[0].size != SZ_64K);
1083 WARN_ON(core->mem[1].size != SZ_64K);
1085 core->mem[0].size /= 2;
1086 core->mem[1].size /= 2;
1088 dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
1089 core->mem[0].size, core->mem[1].size);
1094 * This function checks and configures a R5F core for IPC-only or remoteproc
1095 * mode. The driver is configured to be in IPC-only mode for a R5F core when
1096 * the core has been loaded and started by a bootloader. The IPC-only mode is
1097 * detected by querying the System Firmware for reset, power on and halt status
1098 * and ensuring that the core is running. Any incomplete steps at bootloader
1099 * are validated and errored out.
1101 * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings
1102 * and cluster mode parsed originally from kernel DT are updated to reflect the
1103 * actual values configured by bootloader. The driver internal device memory
1104 * addresses for TCMs are also updated.
1106 static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc)
1108 struct k3_r5_cluster *cluster = kproc->cluster;
1109 struct k3_r5_core *core = kproc->core;
1110 struct device *cdev = core->dev;
1111 bool r_state = false, c_state = false;
1112 u32 ctrl = 0, cfg = 0, stat = 0, halted = 0;
1114 u32 atcm_enable, btcm_enable, loczrama;
1115 struct k3_r5_core *core0;
1116 enum cluster_mode mode;
1119 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1121 ret = core->ti_sci->ops.dev_ops.is_on(core->ti_sci, core->ti_sci_id,
1122 &r_state, &c_state);
1124 dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n",
1128 if (r_state != c_state) {
1129 dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n",
1133 ret = reset_control_status(core->reset);
1135 dev_err(cdev, "failed to get initial local reset status, ret = %d\n",
1140 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
1143 dev_err(cdev, "failed to get initial processor status, ret = %d\n",
1147 atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0;
1148 btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0;
1149 loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0;
1150 if (cluster->soc_data->single_cpu_mode) {
1151 mode = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ?
1152 CLUSTER_MODE_SINGLECPU : CLUSTER_MODE_SPLIT;
1154 mode = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ?
1155 CLUSTER_MODE_LOCKSTEP : CLUSTER_MODE_SPLIT;
1157 halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT;
1160 * IPC-only mode detection requires both local and module resets to
1161 * be deasserted and R5F core to be unhalted. Local reset status is
1162 * irrelevant if module reset is asserted (POR value has local reset
1163 * deasserted), and is deemed as remoteproc mode
1165 if (c_state && !ret && !halted) {
1166 dev_info(cdev, "configured R5F for IPC-only mode\n");
1167 kproc->rproc->state = RPROC_DETACHED;
1169 /* override rproc ops with only required IPC-only mode ops */
1170 kproc->rproc->ops->prepare = NULL;
1171 kproc->rproc->ops->unprepare = NULL;
1172 kproc->rproc->ops->start = NULL;
1173 kproc->rproc->ops->stop = NULL;
1174 kproc->rproc->ops->attach = k3_r5_rproc_attach;
1175 kproc->rproc->ops->detach = k3_r5_rproc_detach;
1176 kproc->rproc->ops->get_loaded_rsc_table =
1177 k3_r5_get_loaded_rsc_table;
1178 } else if (!c_state) {
1179 dev_info(cdev, "configured R5F for remoteproc mode\n");
1182 dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n",
1183 !ret ? "deasserted" : "asserted",
1184 c_state ? "deasserted" : "asserted",
1185 halted ? "halted" : "unhalted");
1189 /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */
1192 cluster->mode = mode;
1193 core->atcm_enable = atcm_enable;
1194 core->btcm_enable = btcm_enable;
1195 core->loczrama = loczrama;
1196 core->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR;
1197 core->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0;
1203 static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
1205 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1206 struct device *dev = &pdev->dev;
1207 struct k3_r5_rproc *kproc;
1208 struct k3_r5_core *core, *core1;
1209 struct device *cdev;
1210 const char *fw_name;
1211 struct rproc *rproc;
1214 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1215 list_for_each_entry(core, &cluster->cores, elem) {
1217 ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
1219 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1224 rproc = rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,
1225 fw_name, sizeof(*kproc));
1231 /* K3 R5s have a Region Address Translator (RAT) but no MMU */
1232 rproc->has_iommu = false;
1233 /* error recovery is not supported at present */
1234 rproc->recovery_disabled = true;
1236 kproc = rproc->priv;
1237 kproc->cluster = cluster;
1240 kproc->rproc = rproc;
1241 core->rproc = rproc;
1243 ret = k3_r5_rproc_configure_mode(kproc);
1249 ret = k3_r5_rproc_configure(kproc);
1251 dev_err(dev, "initial configure failed, ret = %d\n",
1257 k3_r5_adjust_tcm_sizes(kproc);
1259 ret = k3_r5_reserved_mem_init(kproc);
1261 dev_err(dev, "reserved memory init failed, ret = %d\n",
1266 ret = rproc_add(rproc);
1268 dev_err(dev, "rproc_add failed, ret = %d\n", ret);
1272 /* create only one rproc in lockstep mode or single-cpu mode */
1273 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1274 cluster->mode == CLUSTER_MODE_SINGLECPU)
1281 if (rproc->state == RPROC_ATTACHED) {
1282 ret1 = rproc_detach(rproc);
1284 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n",
1292 k3_r5_reserved_mem_exit(kproc);
1297 /* undo core0 upon any failures on core1 in split-mode */
1298 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {
1299 core = list_prev_entry(core, elem);
1300 rproc = core->rproc;
1301 kproc = rproc->priv;
1307 static void k3_r5_cluster_rproc_exit(void *data)
1309 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1310 struct k3_r5_rproc *kproc;
1311 struct k3_r5_core *core;
1312 struct rproc *rproc;
1316 * lockstep mode and single-cpu modes have only one rproc associated
1317 * with first core, whereas split-mode has two rprocs associated with
1318 * each core, and requires that core1 be powered down first
1320 core = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1321 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
1322 list_first_entry(&cluster->cores, struct k3_r5_core, elem) :
1323 list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1325 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
1326 rproc = core->rproc;
1327 kproc = rproc->priv;
1329 if (rproc->state == RPROC_ATTACHED) {
1330 ret = rproc_detach(rproc);
1332 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret);
1339 k3_r5_reserved_mem_exit(kproc);
1346 static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
1347 struct k3_r5_core *core)
1349 static const char * const mem_names[] = {"atcm", "btcm"};
1350 struct device *dev = &pdev->dev;
1351 struct resource *res;
1355 num_mems = ARRAY_SIZE(mem_names);
1356 core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
1360 for (i = 0; i < num_mems; i++) {
1361 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1364 dev_err(dev, "found no memory resource for %s\n",
1368 if (!devm_request_mem_region(dev, res->start,
1371 dev_err(dev, "could not request %s region for resource\n",
1377 * TCMs are designed in general to support RAM-like backing
1378 * memories. So, map these as Normal Non-Cached memories. This
1379 * also avoids/fixes any potential alignment faults due to
1380 * unaligned data accesses when using memcpy() or memset()
1381 * functions (normally seen with device type memory).
1383 core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
1384 resource_size(res));
1385 if (!core->mem[i].cpu_addr) {
1386 dev_err(dev, "failed to map %s memory\n", mem_names[i]);
1389 core->mem[i].bus_addr = res->start;
1393 * The R5F cores can place ATCM & BTCM anywhere in its address
1394 * based on the corresponding Region Registers in the System
1395 * Control coprocessor. For now, place ATCM and BTCM at
1396 * addresses 0 and 0x41010000 (same as the bus address on AM65x
1397 * SoCs) based on loczrama setting
1399 if (!strcmp(mem_names[i], "atcm")) {
1400 core->mem[i].dev_addr = core->loczrama ?
1401 0 : K3_R5_TCM_DEV_ADDR;
1403 core->mem[i].dev_addr = core->loczrama ?
1404 K3_R5_TCM_DEV_ADDR : 0;
1406 core->mem[i].size = resource_size(res);
1408 dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1409 mem_names[i], &core->mem[i].bus_addr,
1410 core->mem[i].size, core->mem[i].cpu_addr,
1411 core->mem[i].dev_addr);
1413 core->num_mems = num_mems;
1418 static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
1419 struct k3_r5_core *core)
1421 struct device_node *np = pdev->dev.of_node;
1422 struct device *dev = &pdev->dev;
1423 struct device_node *sram_np;
1424 struct resource res;
1428 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
1429 if (num_sram <= 0) {
1430 dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
1435 core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
1439 for (i = 0; i < num_sram; i++) {
1440 sram_np = of_parse_phandle(np, "sram", i);
1444 if (!of_device_is_available(sram_np)) {
1445 of_node_put(sram_np);
1449 ret = of_address_to_resource(sram_np, 0, &res);
1450 of_node_put(sram_np);
1454 core->sram[i].bus_addr = res.start;
1455 core->sram[i].dev_addr = res.start;
1456 core->sram[i].size = resource_size(&res);
1457 core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
1458 resource_size(&res));
1459 if (!core->sram[i].cpu_addr) {
1460 dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
1465 dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1466 i, &core->sram[i].bus_addr,
1467 core->sram[i].size, core->sram[i].cpu_addr,
1468 core->sram[i].dev_addr);
1470 core->num_sram = num_sram;
1476 struct ti_sci_proc *k3_r5_core_of_get_tsp(struct device *dev,
1477 const struct ti_sci_handle *sci)
1479 struct ti_sci_proc *tsp;
1483 ret = of_property_read_u32_array(dev_of_node(dev), "ti,sci-proc-ids",
1486 return ERR_PTR(ret);
1488 tsp = devm_kzalloc(dev, sizeof(*tsp), GFP_KERNEL);
1490 return ERR_PTR(-ENOMEM);
1494 tsp->ops = &sci->ops.proc_ops;
1495 tsp->proc_id = temp[0];
1496 tsp->host_id = temp[1];
1501 static int k3_r5_core_of_init(struct platform_device *pdev)
1503 struct device *dev = &pdev->dev;
1504 struct device_node *np = dev_of_node(dev);
1505 struct k3_r5_core *core;
1508 if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))
1511 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
1519 * Use SoC Power-on-Reset values as default if no DT properties are
1520 * used to dictate the TCM configurations
1522 core->atcm_enable = 0;
1523 core->btcm_enable = 1;
1526 ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);
1527 if (ret < 0 && ret != -EINVAL) {
1528 dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",
1533 ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);
1534 if (ret < 0 && ret != -EINVAL) {
1535 dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",
1540 ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);
1541 if (ret < 0 && ret != -EINVAL) {
1542 dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);
1546 core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");
1547 if (IS_ERR(core->ti_sci)) {
1548 ret = PTR_ERR(core->ti_sci);
1549 if (ret != -EPROBE_DEFER) {
1550 dev_err(dev, "failed to get ti-sci handle, ret = %d\n",
1553 core->ti_sci = NULL;
1557 ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id);
1559 dev_err(dev, "missing 'ti,sci-dev-id' property\n");
1563 core->reset = devm_reset_control_get_exclusive(dev, NULL);
1564 if (IS_ERR_OR_NULL(core->reset)) {
1565 ret = PTR_ERR_OR_ZERO(core->reset);
1568 if (ret != -EPROBE_DEFER) {
1569 dev_err(dev, "failed to get reset handle, ret = %d\n",
1575 core->tsp = k3_r5_core_of_get_tsp(dev, core->ti_sci);
1576 if (IS_ERR(core->tsp)) {
1577 ret = PTR_ERR(core->tsp);
1578 dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n",
1583 ret = k3_r5_core_of_get_internal_memories(pdev, core);
1585 dev_err(dev, "failed to get internal memories, ret = %d\n",
1590 ret = k3_r5_core_of_get_sram_memories(pdev, core);
1592 dev_err(dev, "failed to get sram memories, ret = %d\n", ret);
1596 ret = ti_sci_proc_request(core->tsp);
1598 dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret);
1602 platform_set_drvdata(pdev, core);
1603 devres_close_group(dev, k3_r5_core_of_init);
1608 devres_release_group(dev, k3_r5_core_of_init);
1613 * free the resources explicitly since driver model is not being used
1614 * for the child R5F devices
1616 static void k3_r5_core_of_exit(struct platform_device *pdev)
1618 struct k3_r5_core *core = platform_get_drvdata(pdev);
1619 struct device *dev = &pdev->dev;
1622 ret = ti_sci_proc_release(core->tsp);
1624 dev_err(dev, "failed to release proc, ret = %d\n", ret);
1626 platform_set_drvdata(pdev, NULL);
1627 devres_release_group(dev, k3_r5_core_of_init);
1630 static void k3_r5_cluster_of_exit(void *data)
1632 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1633 struct platform_device *cpdev;
1634 struct k3_r5_core *core, *temp;
1636 list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {
1637 list_del(&core->elem);
1638 cpdev = to_platform_device(core->dev);
1639 k3_r5_core_of_exit(cpdev);
1643 static int k3_r5_cluster_of_init(struct platform_device *pdev)
1645 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1646 struct device *dev = &pdev->dev;
1647 struct device_node *np = dev_of_node(dev);
1648 struct platform_device *cpdev;
1649 struct device_node *child;
1650 struct k3_r5_core *core;
1653 for_each_available_child_of_node(np, child) {
1654 cpdev = of_find_device_by_node(child);
1657 dev_err(dev, "could not get R5 core platform device\n");
1662 ret = k3_r5_core_of_init(cpdev);
1664 dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",
1666 put_device(&cpdev->dev);
1671 core = platform_get_drvdata(cpdev);
1672 put_device(&cpdev->dev);
1673 list_add_tail(&core->elem, &cluster->cores);
1679 k3_r5_cluster_of_exit(pdev);
1683 static int k3_r5_probe(struct platform_device *pdev)
1685 struct device *dev = &pdev->dev;
1686 struct device_node *np = dev_of_node(dev);
1687 struct k3_r5_cluster *cluster;
1688 const struct k3_r5_soc_data *data;
1692 data = of_device_get_match_data(&pdev->dev);
1694 dev_err(dev, "SoC-specific data is not defined\n");
1698 cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
1704 * default to most common efuse configurations - Split-mode on AM64x
1705 * and LockStep-mode on all others
1707 cluster->mode = data->single_cpu_mode ?
1708 CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;
1709 cluster->soc_data = data;
1710 INIT_LIST_HEAD(&cluster->cores);
1712 ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);
1713 if (ret < 0 && ret != -EINVAL) {
1714 dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n",
1719 num_cores = of_get_available_child_count(np);
1720 if (num_cores != 2) {
1721 dev_err(dev, "MCU cluster requires both R5F cores to be enabled, num_cores = %d\n",
1726 platform_set_drvdata(pdev, cluster);
1728 ret = devm_of_platform_populate(dev);
1730 dev_err(dev, "devm_of_platform_populate failed, ret = %d\n",
1735 ret = k3_r5_cluster_of_init(pdev);
1737 dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret);
1741 ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);
1745 ret = k3_r5_cluster_rproc_init(pdev);
1747 dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n",
1752 ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);
1759 static const struct k3_r5_soc_data am65_j721e_soc_data = {
1760 .tcm_is_double = false,
1761 .tcm_ecc_autoinit = false,
1762 .single_cpu_mode = false,
1765 static const struct k3_r5_soc_data j7200_j721s2_soc_data = {
1766 .tcm_is_double = true,
1767 .tcm_ecc_autoinit = true,
1768 .single_cpu_mode = false,
1771 static const struct k3_r5_soc_data am64_soc_data = {
1772 .tcm_is_double = true,
1773 .tcm_ecc_autoinit = true,
1774 .single_cpu_mode = true,
1777 static const struct of_device_id k3_r5_of_match[] = {
1778 { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, },
1779 { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },
1780 { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },
1781 { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },
1782 { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },
1785 MODULE_DEVICE_TABLE(of, k3_r5_of_match);
1787 static struct platform_driver k3_r5_rproc_driver = {
1788 .probe = k3_r5_probe,
1790 .name = "k3_r5_rproc",
1791 .of_match_table = k3_r5_of_match,
1795 module_platform_driver(k3_r5_rproc_driver);
1797 MODULE_LICENSE("GPL v2");
1798 MODULE_DESCRIPTION("TI K3 R5F remote processor driver");
1799 MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");