1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
5 * Copyright (C) 2016 Linaro Ltd
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/qcom_scm.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/remoteproc.h>
25 #include <linux/soc/qcom/mdt_loader.h>
26 #include <linux/soc/qcom/smem.h>
27 #include <linux/soc/qcom/smem_state.h>
28 #include <linux/rpmsg/qcom_smd.h>
30 #include "qcom_common.h"
31 #include "remoteproc_internal.h"
32 #include "qcom_pil_info.h"
33 #include "qcom_wcnss.h"
35 #define WCNSS_CRASH_REASON_SMEM 422
36 #define WCNSS_FIRMWARE_NAME "wcnss.mdt"
37 #define WCNSS_PAS_ID 6
38 #define WCNSS_SSCTL_ID 0x13
40 #define WCNSS_SPARE_NVBIN_DLND BIT(25)
42 #define WCNSS_PMU_IRIS_XO_CFG BIT(3)
43 #define WCNSS_PMU_IRIS_XO_EN BIT(4)
44 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
45 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
47 #define WCNSS_PMU_IRIS_RESET BIT(7)
48 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
49 #define WCNSS_PMU_IRIS_XO_READ BIT(9)
50 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
52 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
53 #define WCNSS_PMU_XO_MODE_19p2 0
54 #define WCNSS_PMU_XO_MODE_48 3
56 #define WCNSS_MAX_PDS 2
62 const char *pd_names[WCNSS_MAX_PDS];
63 const struct wcnss_vreg_info *vregs;
64 size_t num_vregs, num_pd_vregs;
71 void __iomem *pmu_cfg;
72 void __iomem *spare_out;
82 struct qcom_smem_state *state;
85 struct mutex iris_lock;
86 struct qcom_iris *iris;
88 struct device *pds[WCNSS_MAX_PDS];
90 struct regulator_bulk_data *vregs;
93 struct completion start_done;
94 struct completion stop_done;
97 phys_addr_t mem_reloc;
101 struct qcom_rproc_subdev smd_subdev;
102 struct qcom_sysmon *sysmon;
105 static const struct wcnss_data riva_data = {
107 .spare_offset = 0xb4,
109 .vregs = (struct wcnss_vreg_info[]) {
110 { "vddmx", 1050000, 1150000, 0 },
111 { "vddcx", 1050000, 1150000, 0 },
112 { "vddpx", 1800000, 1800000, 0 },
117 static const struct wcnss_data pronto_v1_data = {
118 .pmu_offset = 0x1004,
119 .spare_offset = 0x1088,
121 .pd_names = { "mx", "cx" },
122 .vregs = (struct wcnss_vreg_info[]) {
123 { "vddmx", 950000, 1150000, 0 },
124 { "vddcx", .super_turbo = true},
125 { "vddpx", 1800000, 1800000, 0 },
131 static const struct wcnss_data pronto_v2_data = {
132 .pmu_offset = 0x1004,
133 .spare_offset = 0x1088,
135 .pd_names = { "mx", "cx" },
136 .vregs = (struct wcnss_vreg_info[]) {
137 { "vddmx", 1287500, 1287500, 0 },
138 { "vddcx", .super_turbo = true },
139 { "vddpx", 1800000, 1800000, 0 },
145 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
146 struct qcom_iris *iris,
149 mutex_lock(&wcnss->iris_lock);
152 wcnss->use_48mhz_xo = use_48mhz_xo;
154 mutex_unlock(&wcnss->iris_lock);
157 static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
159 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
162 ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
163 wcnss->mem_region, wcnss->mem_phys,
164 wcnss->mem_size, &wcnss->mem_reloc);
168 qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
173 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
177 /* Indicate NV download capability */
178 val = readl(wcnss->spare_out);
179 val |= WCNSS_SPARE_NVBIN_DLND;
180 writel(val, wcnss->spare_out);
183 static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
187 /* Clear PMU cfg register */
188 writel(0, wcnss->pmu_cfg);
190 val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
191 writel(val, wcnss->pmu_cfg);
194 val &= ~WCNSS_PMU_XO_MODE_MASK;
195 if (wcnss->use_48mhz_xo)
196 val |= WCNSS_PMU_XO_MODE_48 << 1;
198 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
199 writel(val, wcnss->pmu_cfg);
202 val |= WCNSS_PMU_IRIS_RESET;
203 writel(val, wcnss->pmu_cfg);
205 /* Wait for PMU.iris_reg_reset_sts */
206 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
209 /* Clear IRIS reset */
210 val &= ~WCNSS_PMU_IRIS_RESET;
211 writel(val, wcnss->pmu_cfg);
213 /* Start IRIS XO configuration */
214 val |= WCNSS_PMU_IRIS_XO_CFG;
215 writel(val, wcnss->pmu_cfg);
217 /* Wait for XO configuration to finish */
218 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
221 /* Stop IRIS XO configuration */
222 val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
223 val &= ~WCNSS_PMU_IRIS_XO_CFG;
224 writel(val, wcnss->pmu_cfg);
226 /* Add some delay for XO to settle */
230 static int wcnss_start(struct rproc *rproc)
232 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
235 mutex_lock(&wcnss->iris_lock);
237 dev_err(wcnss->dev, "no iris registered\n");
239 goto release_iris_lock;
242 for (i = 0; i < wcnss->num_pds; i++) {
243 dev_pm_genpd_set_performance_state(wcnss->pds[i], INT_MAX);
244 ret = pm_runtime_get_sync(wcnss->pds[i]);
246 pm_runtime_put_noidle(wcnss->pds[i]);
251 ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
255 ret = qcom_iris_enable(wcnss->iris);
257 goto disable_regulators;
259 wcnss_indicate_nv_download(wcnss);
260 wcnss_configure_iris(wcnss);
262 ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
265 "failed to authenticate image and release reset\n");
269 ret = wait_for_completion_timeout(&wcnss->start_done,
270 msecs_to_jiffies(5000));
271 if (wcnss->ready_irq > 0 && ret == 0) {
272 /* We have a ready_irq, but it didn't fire in time. */
273 dev_err(wcnss->dev, "start timed out\n");
274 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
282 qcom_iris_disable(wcnss->iris);
284 regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
286 for (i--; i >= 0; i--) {
287 pm_runtime_put(wcnss->pds[i]);
288 dev_pm_genpd_set_performance_state(wcnss->pds[i], 0);
291 mutex_unlock(&wcnss->iris_lock);
296 static int wcnss_stop(struct rproc *rproc)
298 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
302 qcom_smem_state_update_bits(wcnss->state,
303 BIT(wcnss->stop_bit),
304 BIT(wcnss->stop_bit));
306 ret = wait_for_completion_timeout(&wcnss->stop_done,
307 msecs_to_jiffies(5000));
309 dev_err(wcnss->dev, "timed out on wait\n");
311 qcom_smem_state_update_bits(wcnss->state,
312 BIT(wcnss->stop_bit),
316 ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
318 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
323 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
325 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
328 offset = da - wcnss->mem_reloc;
329 if (offset < 0 || offset + len > wcnss->mem_size)
332 return wcnss->mem_region + offset;
335 static const struct rproc_ops wcnss_ops = {
336 .start = wcnss_start,
338 .da_to_va = wcnss_da_to_va,
339 .parse_fw = qcom_register_dump_segments,
343 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
345 struct qcom_wcnss *wcnss = dev;
347 rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
352 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
354 struct qcom_wcnss *wcnss = dev;
358 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
359 if (!IS_ERR(msg) && len > 0 && msg[0])
360 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
362 rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
367 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
369 struct qcom_wcnss *wcnss = dev;
371 complete(&wcnss->start_done);
376 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
379 * XXX: At this point we're supposed to release the resources that we
380 * have been holding on behalf of the WCNSS. Unfortunately this
381 * interrupt comes way before the other side seems to be done.
383 * So we're currently relying on the ready interrupt firing later then
384 * this and we just disable the resources at the end of wcnss_start().
390 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
392 struct qcom_wcnss *wcnss = dev;
394 complete(&wcnss->stop_done);
399 static int wcnss_init_pds(struct qcom_wcnss *wcnss,
400 const char * const pd_names[WCNSS_MAX_PDS])
404 for (i = 0; i < WCNSS_MAX_PDS; i++) {
408 wcnss->pds[i] = dev_pm_domain_attach_by_name(wcnss->dev, pd_names[i]);
409 if (IS_ERR_OR_NULL(wcnss->pds[i])) {
410 ret = PTR_ERR(wcnss->pds[i]) ? : -ENODATA;
411 for (i--; i >= 0; i--)
412 dev_pm_domain_detach(wcnss->pds[i], false);
421 static void wcnss_release_pds(struct qcom_wcnss *wcnss)
425 for (i = 0; i < wcnss->num_pds; i++)
426 dev_pm_domain_detach(wcnss->pds[i], false);
429 static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
430 const struct wcnss_vreg_info *info,
431 int num_vregs, int num_pd_vregs)
433 struct regulator_bulk_data *bulk;
438 * If attaching the power domains suceeded we can skip requesting
439 * the regulators for the power domains. For old device trees we need to
440 * reserve extra space to manage them through the regulator interface.
443 info += num_pd_vregs;
445 num_vregs += num_pd_vregs;
447 bulk = devm_kcalloc(wcnss->dev,
448 num_vregs, sizeof(struct regulator_bulk_data),
453 for (i = 0; i < num_vregs; i++)
454 bulk[i].supply = info[i].name;
456 ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
460 for (i = 0; i < num_vregs; i++) {
461 if (info[i].max_voltage)
462 regulator_set_voltage(bulk[i].consumer,
464 info[i].max_voltage);
467 regulator_set_load(bulk[i].consumer, info[i].load_uA);
471 wcnss->num_vregs = num_vregs;
476 static int wcnss_request_irq(struct qcom_wcnss *wcnss,
477 struct platform_device *pdev,
480 irq_handler_t thread_fn)
484 ret = platform_get_irq_byname(pdev, name);
485 if (ret < 0 && optional) {
486 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
488 } else if (ret < 0) {
489 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
493 ret = devm_request_threaded_irq(&pdev->dev, ret,
495 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
498 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
503 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
505 struct device_node *node;
509 node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
511 dev_err(wcnss->dev, "no memory-region specified\n");
515 ret = of_address_to_resource(node, 0, &r);
519 wcnss->mem_phys = wcnss->mem_reloc = r.start;
520 wcnss->mem_size = resource_size(&r);
521 wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
522 if (!wcnss->mem_region) {
523 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
524 &r.start, wcnss->mem_size);
531 static int wcnss_probe(struct platform_device *pdev)
533 const char *fw_name = WCNSS_FIRMWARE_NAME;
534 const struct wcnss_data *data;
535 struct qcom_wcnss *wcnss;
536 struct resource *res;
541 data = of_device_get_match_data(&pdev->dev);
543 if (!qcom_scm_is_available())
544 return -EPROBE_DEFER;
546 if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
547 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
551 ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
553 if (ret < 0 && ret != -EINVAL)
556 rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
557 fw_name, sizeof(*wcnss));
559 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
562 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
564 wcnss = (struct qcom_wcnss *)rproc->priv;
565 wcnss->dev = &pdev->dev;
566 wcnss->rproc = rproc;
567 platform_set_drvdata(pdev, wcnss);
569 init_completion(&wcnss->start_done);
570 init_completion(&wcnss->stop_done);
572 mutex_init(&wcnss->iris_lock);
574 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
575 mmio = devm_ioremap_resource(&pdev->dev, res);
581 ret = wcnss_alloc_memory_region(wcnss);
585 wcnss->pmu_cfg = mmio + data->pmu_offset;
586 wcnss->spare_out = mmio + data->spare_offset;
589 * We might need to fallback to regulators instead of power domains
590 * for old device trees. Don't report an error in that case.
592 ret = wcnss_init_pds(wcnss, data->pd_names);
593 if (ret && (ret != -ENODATA || !data->num_pd_vregs))
596 ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs,
601 ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
604 wcnss->wdog_irq = ret;
606 ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
609 wcnss->fatal_irq = ret;
611 ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
614 wcnss->ready_irq = ret;
616 ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
619 wcnss->handover_irq = ret;
621 ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
624 wcnss->stop_ack_irq = ret;
626 if (wcnss->stop_ack_irq) {
627 wcnss->state = devm_qcom_smem_state_get(&pdev->dev, "stop",
629 if (IS_ERR(wcnss->state)) {
630 ret = PTR_ERR(wcnss->state);
635 qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
636 wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
637 if (IS_ERR(wcnss->sysmon)) {
638 ret = PTR_ERR(wcnss->sysmon);
642 ret = rproc_add(rproc);
646 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
649 wcnss_release_pds(wcnss);
656 static int wcnss_remove(struct platform_device *pdev)
658 struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
660 of_platform_depopulate(&pdev->dev);
662 rproc_del(wcnss->rproc);
664 qcom_remove_sysmon_subdev(wcnss->sysmon);
665 qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
666 wcnss_release_pds(wcnss);
667 rproc_free(wcnss->rproc);
672 static const struct of_device_id wcnss_of_match[] = {
673 { .compatible = "qcom,riva-pil", &riva_data },
674 { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
675 { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
678 MODULE_DEVICE_TABLE(of, wcnss_of_match);
680 static struct platform_driver wcnss_driver = {
681 .probe = wcnss_probe,
682 .remove = wcnss_remove,
684 .name = "qcom-wcnss-pil",
685 .of_match_table = wcnss_of_match,
689 static int __init wcnss_init(void)
693 ret = platform_driver_register(&wcnss_driver);
697 ret = platform_driver_register(&qcom_iris_driver);
699 platform_driver_unregister(&wcnss_driver);
703 module_init(wcnss_init);
705 static void __exit wcnss_exit(void)
707 platform_driver_unregister(&qcom_iris_driver);
708 platform_driver_unregister(&wcnss_driver);
710 module_exit(wcnss_exit);
712 MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
713 MODULE_LICENSE("GPL v2");