2 * Qualcomm Peripheral Image Loader
4 * Copyright (C) 2016 Linaro Ltd.
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/remoteproc.h>
31 #include <linux/reset.h>
32 #include <linux/soc/qcom/mdt_loader.h>
33 #include <linux/soc/qcom/smem.h>
34 #include <linux/soc/qcom/smem_state.h>
36 #include "remoteproc_internal.h"
37 #include "qcom_common.h"
39 #include <linux/qcom_scm.h>
41 #define MPSS_CRASH_REASON_SMEM 421
43 /* RMB Status Register Values */
44 #define RMB_PBL_SUCCESS 0x1
46 #define RMB_MBA_XPU_UNLOCKED 0x1
47 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
48 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
49 #define RMB_MBA_AUTH_COMPLETE 0x4
51 /* PBL/MBA interface registers */
52 #define RMB_MBA_IMAGE_REG 0x00
53 #define RMB_PBL_STATUS_REG 0x04
54 #define RMB_MBA_COMMAND_REG 0x08
55 #define RMB_MBA_STATUS_REG 0x0C
56 #define RMB_PMI_META_DATA_REG 0x10
57 #define RMB_PMI_CODE_START_REG 0x14
58 #define RMB_PMI_CODE_LENGTH_REG 0x18
60 #define RMB_CMD_META_DATA_READY 0x1
61 #define RMB_CMD_LOAD_READY 0x2
63 /* QDSP6SS Register Offsets */
64 #define QDSP6SS_RESET_REG 0x014
65 #define QDSP6SS_GFMUX_CTL_REG 0x020
66 #define QDSP6SS_PWR_CTL_REG 0x030
68 /* AXI Halt Register Offsets */
69 #define AXI_HALTREQ_REG 0x0
70 #define AXI_HALTACK_REG 0x4
71 #define AXI_IDLE_REG 0x8
73 #define HALT_ACK_TIMEOUT_MS 100
76 #define Q6SS_STOP_CORE BIT(0)
77 #define Q6SS_CORE_ARES BIT(1)
78 #define Q6SS_BUS_ARES_ENABLE BIT(2)
80 /* QDSP6SS_GFMUX_CTL */
81 #define Q6SS_CLK_ENABLE BIT(1)
84 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
85 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
86 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
87 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
88 #define Q6SS_ETB_SLP_NRET_N BIT(17)
89 #define Q6SS_L2DATA_STBY_N BIT(18)
90 #define Q6SS_SLP_RET_N BIT(19)
91 #define Q6SS_CLAMP_IO BIT(20)
92 #define QDSS_BHS_ON BIT(21)
93 #define QDSS_LDO_BYP BIT(22)
96 struct regulator *reg;
101 struct qcom_mss_reg_res {
107 struct rproc_hexagon_res {
108 const char *hexagon_mba_image;
109 struct qcom_mss_reg_res *proxy_supply;
110 struct qcom_mss_reg_res *active_supply;
111 char **proxy_clk_names;
112 char **active_clk_names;
119 void __iomem *reg_base;
120 void __iomem *rmb_base;
122 struct regmap *halt_map;
127 struct reset_control *mss_restart;
129 struct qcom_smem_state *state;
132 struct clk *active_clks[8];
133 struct clk *proxy_clks[4];
134 int active_clk_count;
137 struct reg_info active_regs[1];
138 struct reg_info proxy_regs[3];
139 int active_reg_count;
142 struct completion start_done;
143 struct completion stop_done;
146 phys_addr_t mba_phys;
150 phys_addr_t mpss_phys;
151 phys_addr_t mpss_reloc;
155 struct qcom_rproc_subdev smd_subdev;
156 struct qcom_rproc_ssr ssr_subdev;
159 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
160 const struct qcom_mss_reg_res *reg_res)
168 for (i = 0; reg_res[i].supply; i++) {
169 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
170 if (IS_ERR(regs[i].reg)) {
171 rc = PTR_ERR(regs[i].reg);
172 if (rc != -EPROBE_DEFER)
173 dev_err(dev, "Failed to get %s\n regulator",
178 regs[i].uV = reg_res[i].uV;
179 regs[i].uA = reg_res[i].uA;
185 static int q6v5_regulator_enable(struct q6v5 *qproc,
186 struct reg_info *regs, int count)
191 for (i = 0; i < count; i++) {
192 if (regs[i].uV > 0) {
193 ret = regulator_set_voltage(regs[i].reg,
194 regs[i].uV, INT_MAX);
197 "Failed to request voltage for %d.\n",
203 if (regs[i].uA > 0) {
204 ret = regulator_set_load(regs[i].reg,
208 "Failed to set regulator mode\n");
213 ret = regulator_enable(regs[i].reg);
215 dev_err(qproc->dev, "Regulator enable failed\n");
222 for (; i >= 0; i--) {
224 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
227 regulator_set_load(regs[i].reg, 0);
229 regulator_disable(regs[i].reg);
235 static void q6v5_regulator_disable(struct q6v5 *qproc,
236 struct reg_info *regs, int count)
240 for (i = 0; i < count; i++) {
242 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
245 regulator_set_load(regs[i].reg, 0);
247 regulator_disable(regs[i].reg);
251 static int q6v5_clk_enable(struct device *dev,
252 struct clk **clks, int count)
257 for (i = 0; i < count; i++) {
258 rc = clk_prepare_enable(clks[i]);
260 dev_err(dev, "Clock enable failed\n");
267 for (i--; i >= 0; i--)
268 clk_disable_unprepare(clks[i]);
273 static void q6v5_clk_disable(struct device *dev,
274 struct clk **clks, int count)
278 for (i = 0; i < count; i++)
279 clk_disable_unprepare(clks[i]);
282 static struct resource_table *q6v5_find_rsc_table(struct rproc *rproc,
283 const struct firmware *fw,
286 static struct resource_table table = { .ver = 1, };
288 *tablesz = sizeof(table);
292 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
294 struct q6v5 *qproc = rproc->priv;
296 memcpy(qproc->mba_region, fw->data, fw->size);
301 static const struct rproc_fw_ops q6v5_fw_ops = {
302 .find_rsc_table = q6v5_find_rsc_table,
306 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
308 unsigned long timeout;
311 timeout = jiffies + msecs_to_jiffies(ms);
313 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
317 if (time_after(jiffies, timeout))
326 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
329 unsigned long timeout;
332 timeout = jiffies + msecs_to_jiffies(ms);
334 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
340 else if (status && val == status)
343 if (time_after(jiffies, timeout))
352 static int q6v5proc_reset(struct q6v5 *qproc)
357 /* Assert resets, stop core */
358 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
359 val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE);
360 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
362 /* Enable power block headswitch, and wait for it to stabilize */
363 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
364 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
365 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
369 * Turn on memories. L2 banks should be done individually
370 * to minimize inrush current.
372 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
373 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
374 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
375 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
376 val |= Q6SS_L2DATA_SLP_NRET_N_2;
377 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
378 val |= Q6SS_L2DATA_SLP_NRET_N_1;
379 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
380 val |= Q6SS_L2DATA_SLP_NRET_N_0;
381 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
383 /* Remove IO clamp */
384 val &= ~Q6SS_CLAMP_IO;
385 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
387 /* Bring core out of reset */
388 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
389 val &= ~Q6SS_CORE_ARES;
390 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
392 /* Turn on core clock */
393 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
394 val |= Q6SS_CLK_ENABLE;
395 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
397 /* Start core execution */
398 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
399 val &= ~Q6SS_STOP_CORE;
400 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
402 /* Wait for PBL status */
403 ret = q6v5_rmb_pbl_wait(qproc, 1000);
404 if (ret == -ETIMEDOUT) {
405 dev_err(qproc->dev, "PBL boot timed out\n");
406 } else if (ret != RMB_PBL_SUCCESS) {
407 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
416 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
417 struct regmap *halt_map,
420 unsigned long timeout;
424 /* Check if we're already idle */
425 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
429 /* Assert halt request */
430 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
433 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
435 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
436 if (ret || val || time_after(jiffies, timeout))
442 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
444 dev_err(qproc->dev, "port failed halt\n");
446 /* Clear halt request (port will remain halted until reset) */
447 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
450 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
452 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
457 ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs);
459 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
463 memcpy(ptr, fw->data, fw->size);
465 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
466 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
468 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
469 if (ret == -ETIMEDOUT)
470 dev_err(qproc->dev, "MPSS header authentication timed out\n");
472 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
474 dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs);
476 return ret < 0 ? ret : 0;
479 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
481 if (phdr->p_type != PT_LOAD)
484 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
493 static int q6v5_mpss_load(struct q6v5 *qproc)
495 const struct elf32_phdr *phdrs;
496 const struct elf32_phdr *phdr;
497 const struct firmware *seg_fw;
498 const struct firmware *fw;
499 struct elf32_hdr *ehdr;
500 phys_addr_t mpss_reloc;
501 phys_addr_t boot_addr;
502 phys_addr_t min_addr = (phys_addr_t)ULLONG_MAX;
503 phys_addr_t max_addr = 0;
504 bool relocate = false;
512 ret = request_firmware(&fw, "modem.mdt", qproc->dev);
514 dev_err(qproc->dev, "unable to load modem.mdt\n");
518 /* Initialize the RMB validator */
519 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
521 ret = q6v5_mpss_init_image(qproc, fw);
523 goto release_firmware;
525 ehdr = (struct elf32_hdr *)fw->data;
526 phdrs = (struct elf32_phdr *)(ehdr + 1);
528 for (i = 0; i < ehdr->e_phnum; i++) {
531 if (!q6v5_phdr_valid(phdr))
534 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
537 if (phdr->p_paddr < min_addr)
538 min_addr = phdr->p_paddr;
540 if (phdr->p_paddr + phdr->p_memsz > max_addr)
541 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
544 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
546 for (i = 0; i < ehdr->e_phnum; i++) {
549 if (!q6v5_phdr_valid(phdr))
552 offset = phdr->p_paddr - mpss_reloc;
553 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
554 dev_err(qproc->dev, "segment outside memory range\n");
556 goto release_firmware;
559 ptr = qproc->mpss_region + offset;
561 if (phdr->p_filesz) {
562 snprintf(seg_name, sizeof(seg_name), "modem.b%02d", i);
563 ret = request_firmware(&seg_fw, seg_name, qproc->dev);
565 dev_err(qproc->dev, "failed to load %s\n", seg_name);
566 goto release_firmware;
569 memcpy(ptr, seg_fw->data, seg_fw->size);
571 release_firmware(seg_fw);
574 if (phdr->p_memsz > phdr->p_filesz) {
575 memset(ptr + phdr->p_filesz, 0,
576 phdr->p_memsz - phdr->p_filesz);
579 size = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
581 boot_addr = relocate ? qproc->mpss_phys : min_addr;
582 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
583 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
586 size += phdr->p_memsz;
587 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
590 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
591 if (ret == -ETIMEDOUT)
592 dev_err(qproc->dev, "MPSS authentication timed out\n");
594 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
597 release_firmware(fw);
599 return ret < 0 ? ret : 0;
602 static int q6v5_start(struct rproc *rproc)
604 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
607 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
608 qproc->proxy_reg_count);
610 dev_err(qproc->dev, "failed to enable proxy supplies\n");
614 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
615 qproc->proxy_clk_count);
617 dev_err(qproc->dev, "failed to enable proxy clocks\n");
618 goto disable_proxy_reg;
621 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
622 qproc->active_reg_count);
624 dev_err(qproc->dev, "failed to enable supplies\n");
625 goto disable_proxy_clk;
627 ret = reset_control_deassert(qproc->mss_restart);
629 dev_err(qproc->dev, "failed to deassert mss restart\n");
633 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
634 qproc->active_clk_count);
636 dev_err(qproc->dev, "failed to enable clocks\n");
640 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
642 ret = q6v5proc_reset(qproc);
646 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
647 if (ret == -ETIMEDOUT) {
648 dev_err(qproc->dev, "MBA boot timed out\n");
650 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
651 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
652 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
657 dev_info(qproc->dev, "MBA booted, loading mpss\n");
659 ret = q6v5_mpss_load(qproc);
663 ret = wait_for_completion_timeout(&qproc->start_done,
664 msecs_to_jiffies(5000));
666 dev_err(qproc->dev, "start timed out\n");
671 qproc->running = true;
673 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
674 qproc->proxy_clk_count);
675 q6v5_regulator_disable(qproc, qproc->proxy_regs,
676 qproc->proxy_reg_count);
681 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
682 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
683 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
684 q6v5_clk_disable(qproc->dev, qproc->active_clks,
685 qproc->active_clk_count);
687 reset_control_assert(qproc->mss_restart);
689 q6v5_regulator_disable(qproc, qproc->active_regs,
690 qproc->active_reg_count);
692 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
693 qproc->proxy_clk_count);
695 q6v5_regulator_disable(qproc, qproc->proxy_regs,
696 qproc->proxy_reg_count);
701 static int q6v5_stop(struct rproc *rproc)
703 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
706 qproc->running = false;
708 qcom_smem_state_update_bits(qproc->state,
709 BIT(qproc->stop_bit), BIT(qproc->stop_bit));
711 ret = wait_for_completion_timeout(&qproc->stop_done,
712 msecs_to_jiffies(5000));
714 dev_err(qproc->dev, "timed out on wait\n");
716 qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
718 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
719 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
720 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
722 reset_control_assert(qproc->mss_restart);
723 q6v5_clk_disable(qproc->dev, qproc->active_clks,
724 qproc->active_clk_count);
725 q6v5_regulator_disable(qproc, qproc->active_regs,
726 qproc->active_reg_count);
731 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
733 struct q6v5 *qproc = rproc->priv;
736 offset = da - qproc->mpss_reloc;
737 if (offset < 0 || offset + len > qproc->mpss_size)
740 return qproc->mpss_region + offset;
743 static const struct rproc_ops q6v5_ops = {
746 .da_to_va = q6v5_da_to_va,
749 static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
751 struct q6v5 *qproc = dev;
755 /* Sometimes the stop triggers a watchdog rather than a stop-ack */
756 if (!qproc->running) {
757 complete(&qproc->stop_done);
761 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
762 if (!IS_ERR(msg) && len > 0 && msg[0])
763 dev_err(qproc->dev, "watchdog received: %s\n", msg);
765 dev_err(qproc->dev, "watchdog without message\n");
767 rproc_report_crash(qproc->rproc, RPROC_WATCHDOG);
775 static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
777 struct q6v5 *qproc = dev;
781 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
782 if (!IS_ERR(msg) && len > 0 && msg[0])
783 dev_err(qproc->dev, "fatal error received: %s\n", msg);
785 dev_err(qproc->dev, "fatal error without message\n");
787 rproc_report_crash(qproc->rproc, RPROC_FATAL_ERROR);
795 static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
797 struct q6v5 *qproc = dev;
799 complete(&qproc->start_done);
803 static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
805 struct q6v5 *qproc = dev;
807 complete(&qproc->stop_done);
811 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
813 struct of_phandle_args args;
814 struct resource *res;
817 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
818 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
819 if (IS_ERR(qproc->reg_base))
820 return PTR_ERR(qproc->reg_base);
822 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
823 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
824 if (IS_ERR(qproc->rmb_base))
825 return PTR_ERR(qproc->rmb_base);
827 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
828 "qcom,halt-regs", 3, 0, &args);
830 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
834 qproc->halt_map = syscon_node_to_regmap(args.np);
835 of_node_put(args.np);
836 if (IS_ERR(qproc->halt_map))
837 return PTR_ERR(qproc->halt_map);
839 qproc->halt_q6 = args.args[0];
840 qproc->halt_modem = args.args[1];
841 qproc->halt_nc = args.args[2];
846 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
854 for (i = 0; clk_names[i]; i++) {
855 clks[i] = devm_clk_get(dev, clk_names[i]);
856 if (IS_ERR(clks[i])) {
857 int rc = PTR_ERR(clks[i]);
859 if (rc != -EPROBE_DEFER)
860 dev_err(dev, "Failed to get %s clock\n",
869 static int q6v5_init_reset(struct q6v5 *qproc)
871 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
873 if (IS_ERR(qproc->mss_restart)) {
874 dev_err(qproc->dev, "failed to acquire mss restart\n");
875 return PTR_ERR(qproc->mss_restart);
881 static int q6v5_request_irq(struct q6v5 *qproc,
882 struct platform_device *pdev,
884 irq_handler_t thread_fn)
888 ret = platform_get_irq_byname(pdev, name);
890 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
894 ret = devm_request_threaded_irq(&pdev->dev, ret,
896 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
899 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
904 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
906 struct device_node *child;
907 struct device_node *node;
911 child = of_get_child_by_name(qproc->dev->of_node, "mba");
912 node = of_parse_phandle(child, "memory-region", 0);
913 ret = of_address_to_resource(node, 0, &r);
915 dev_err(qproc->dev, "unable to resolve mba region\n");
919 qproc->mba_phys = r.start;
920 qproc->mba_size = resource_size(&r);
921 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
922 if (!qproc->mba_region) {
923 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
924 &r.start, qproc->mba_size);
928 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
929 node = of_parse_phandle(child, "memory-region", 0);
930 ret = of_address_to_resource(node, 0, &r);
932 dev_err(qproc->dev, "unable to resolve mpss region\n");
936 qproc->mpss_phys = qproc->mpss_reloc = r.start;
937 qproc->mpss_size = resource_size(&r);
938 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
939 if (!qproc->mpss_region) {
940 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
941 &r.start, qproc->mpss_size);
948 static int q6v5_probe(struct platform_device *pdev)
950 const struct rproc_hexagon_res *desc;
955 desc = of_device_get_match_data(&pdev->dev);
959 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
960 desc->hexagon_mba_image, sizeof(*qproc));
962 dev_err(&pdev->dev, "failed to allocate rproc\n");
966 rproc->fw_ops = &q6v5_fw_ops;
968 qproc = (struct q6v5 *)rproc->priv;
969 qproc->dev = &pdev->dev;
970 qproc->rproc = rproc;
971 platform_set_drvdata(pdev, qproc);
973 init_completion(&qproc->start_done);
974 init_completion(&qproc->stop_done);
976 ret = q6v5_init_mem(qproc, pdev);
980 ret = q6v5_alloc_memory_region(qproc);
984 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
985 desc->proxy_clk_names);
987 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
990 qproc->proxy_clk_count = ret;
992 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
993 desc->active_clk_names);
995 dev_err(&pdev->dev, "Failed to get active clocks.\n");
998 qproc->active_clk_count = ret;
1000 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1001 desc->proxy_supply);
1003 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1006 qproc->proxy_reg_count = ret;
1008 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1009 desc->active_supply);
1011 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1014 qproc->active_reg_count = ret;
1016 ret = q6v5_init_reset(qproc);
1020 ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
1024 ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
1028 ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
1032 ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
1036 qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit);
1037 if (IS_ERR(qproc->state)) {
1038 ret = PTR_ERR(qproc->state);
1042 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1043 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1045 ret = rproc_add(rproc);
1057 static int q6v5_remove(struct platform_device *pdev)
1059 struct q6v5 *qproc = platform_get_drvdata(pdev);
1061 rproc_del(qproc->rproc);
1063 qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
1064 qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
1065 rproc_free(qproc->rproc);
1070 static const struct rproc_hexagon_res msm8916_mss = {
1071 .hexagon_mba_image = "mba.mbn",
1072 .proxy_supply = (struct qcom_mss_reg_res[]) {
1087 .proxy_clk_names = (char*[]){
1091 .active_clk_names = (char*[]){
1099 static const struct rproc_hexagon_res msm8974_mss = {
1100 .hexagon_mba_image = "mba.b00",
1101 .proxy_supply = (struct qcom_mss_reg_res[]) {
1116 .active_supply = (struct qcom_mss_reg_res[]) {
1124 .proxy_clk_names = (char*[]){
1128 .active_clk_names = (char*[]){
1136 static const struct of_device_id q6v5_of_match[] = {
1137 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1138 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1139 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1142 MODULE_DEVICE_TABLE(of, q6v5_of_match);
1144 static struct platform_driver q6v5_driver = {
1145 .probe = q6v5_probe,
1146 .remove = q6v5_remove,
1148 .name = "qcom-q6v5-pil",
1149 .of_match_table = q6v5_of_match,
1152 module_platform_driver(q6v5_driver);
1154 MODULE_DESCRIPTION("Peripheral Image Loader for Hexagon");
1155 MODULE_LICENSE("GPL v2");