drivers/remoteproc/qcom_q6v5_mss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm self-authenticating modem subsystem remoteproc driver
   4  *
   5  * Copyright (C) 2016 Linaro Ltd.
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/devcoredump.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/remoteproc.h>
  26 #include <linux/reset.h>
  27 #include <linux/soc/qcom/mdt_loader.h>
  28 #include <linux/iopoll.h>
  29 #include <linux/slab.h>
  30
  31 #include "remoteproc_internal.h"
  32 #include "qcom_common.h"
  33 #include "qcom_pil_info.h"
  34 #include "qcom_q6v5.h"
  35
  36 #include <linux/qcom_scm.h>
  37
  38 #define MPSS_CRASH_REASON_SMEM          421
  39
  40 #define MBA_LOG_SIZE                    SZ_4K
  41
  42 /* RMB Status Register Values */
  43 #define RMB_PBL_SUCCESS                 0x1
  44
  45 #define RMB_MBA_XPU_UNLOCKED            0x1
  46 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  47 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  48 #define RMB_MBA_AUTH_COMPLETE           0x4
  49
  50 /* PBL/MBA interface registers */
  51 #define RMB_MBA_IMAGE_REG               0x00
  52 #define RMB_PBL_STATUS_REG              0x04
  53 #define RMB_MBA_COMMAND_REG             0x08
  54 #define RMB_MBA_STATUS_REG              0x0C
  55 #define RMB_PMI_META_DATA_REG           0x10
  56 #define RMB_PMI_CODE_START_REG          0x14
  57 #define RMB_PMI_CODE_LENGTH_REG         0x18
  58 #define RMB_MBA_MSS_STATUS              0x40
  59 #define RMB_MBA_ALT_RESET               0x44
  60
  61 #define RMB_CMD_META_DATA_READY         0x1
  62 #define RMB_CMD_LOAD_READY              0x2
  63
  64 /* QDSP6SS Register Offsets */
  65 #define QDSP6SS_RESET_REG               0x014
  66 #define QDSP6SS_GFMUX_CTL_REG           0x020
  67 #define QDSP6SS_PWR_CTL_REG             0x030
  68 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  69 #define QDSP6V6SS_MEM_PWR_CTL           0x034
  70 #define QDSP6SS_STRAP_ACC               0x110
  71
  72 /* AXI Halt Register Offsets */
  73 #define AXI_HALTREQ_REG                 0x0
  74 #define AXI_HALTACK_REG                 0x4
  75 #define AXI_IDLE_REG                    0x8
  76 #define AXI_GATING_VALID_OVERRIDE       BIT(0)
  77
  78 #define HALT_ACK_TIMEOUT_US             100000
  79
  80 /* QACCEPT Register Offsets */
  81 #define QACCEPT_ACCEPT_REG              0x0
  82 #define QACCEPT_ACTIVE_REG              0x4
  83 #define QACCEPT_DENY_REG                0x8
  84 #define QACCEPT_REQ_REG                 0xC
  85
  86 #define QACCEPT_TIMEOUT_US              50
  87
  88 /* QDSP6SS_RESET */
  89 #define Q6SS_STOP_CORE                  BIT(0)
  90 #define Q6SS_CORE_ARES                  BIT(1)
  91 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  92
  93 /* QDSP6SS CBCR */
  94 #define Q6SS_CBCR_CLKEN                 BIT(0)
  95 #define Q6SS_CBCR_CLKOFF                BIT(31)
  96 #define Q6SS_CBCR_TIMEOUT_US            200
  97
  98 /* QDSP6SS_GFMUX_CTL */
  99 #define Q6SS_CLK_ENABLE                 BIT(1)
 100
 101 /* QDSP6SS_PWR_CTL */
 102 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
 103 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
 104 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
 105 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
 106 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
 107 #define Q6SS_L2DATA_STBY_N              BIT(18)
 108 #define Q6SS_SLP_RET_N                  BIT(19)
 109 #define Q6SS_CLAMP_IO                   BIT(20)
 110 #define QDSS_BHS_ON                     BIT(21)
 111 #define QDSS_LDO_BYP                    BIT(22)
 112
 113 /* QDSP6v56 parameters */
 114 #define QDSP6v56_LDO_BYP                BIT(25)
 115 #define QDSP6v56_BHS_ON         BIT(24)
 116 #define QDSP6v56_CLAMP_WL               BIT(21)
 117 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
 118 #define QDSP6SS_XO_CBCR         0x0038
 119 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 120
 121 /* QDSP6v65 parameters */
 122 #define QDSP6SS_CORE_CBCR               0x20
 123 #define QDSP6SS_SLEEP                   0x3C
 124 #define QDSP6SS_BOOT_CORE_START         0x400
 125 #define QDSP6SS_BOOT_CMD                0x404
 126 #define BOOT_FSM_TIMEOUT                10000
 127
 128 struct reg_info {
 129         struct regulator *reg;
 130         int uV;
 131         int uA;
 132 };
 133
 134 struct qcom_mss_reg_res {
 135         const char *supply;
 136         int uV;
 137         int uA;
 138 };
 139
 140 struct rproc_hexagon_res {
 141         const char *hexagon_mba_image;
 142         struct qcom_mss_reg_res *proxy_supply;
 143         struct qcom_mss_reg_res *fallback_proxy_supply;
 144         struct qcom_mss_reg_res *active_supply;
 145         char **proxy_clk_names;
 146         char **reset_clk_names;
 147         char **active_clk_names;
 148         char **proxy_pd_names;
 149         int version;
 150         bool need_mem_protection;
 151         bool has_alt_reset;
 152         bool has_mba_logs;
 153         bool has_spare_reg;
 154         bool has_qaccept_regs;
 155         bool has_ext_cntl_regs;
 156         bool has_vq6;
 157 };
 158
 159 struct q6v5 {
 160         struct device *dev;
 161         struct rproc *rproc;
 162
 163         void __iomem *reg_base;
 164         void __iomem *rmb_base;
 165
 166         struct regmap *halt_map;
 167         struct regmap *conn_map;
 168
 169         u32 halt_q6;
 170         u32 halt_modem;
 171         u32 halt_nc;
 172         u32 halt_vq6;
 173         u32 conn_box;
 174
 175         u32 qaccept_mdm;
 176         u32 qaccept_cx;
 177         u32 qaccept_axi;
 178
 179         u32 axim1_clk_off;
 180         u32 crypto_clk_off;
 181         u32 force_clk_on;
 182         u32 rscc_disable;
 183
 184         struct reset_control *mss_restart;
 185         struct reset_control *pdc_reset;
 186
 187         struct qcom_q6v5 q6v5;
 188
 189         struct clk *active_clks[8];
 190         struct clk *reset_clks[4];
 191         struct clk *proxy_clks[4];
 192         struct device *proxy_pds[3];
 193         int active_clk_count;
 194         int reset_clk_count;
 195         int proxy_clk_count;
 196         int proxy_pd_count;
 197
 198         struct reg_info active_regs[1];
 199         struct reg_info proxy_regs[1];
 200         struct reg_info fallback_proxy_regs[2];
 201         int active_reg_count;
 202         int proxy_reg_count;
 203         int fallback_proxy_reg_count;
 204
 205         bool dump_mba_loaded;
 206         size_t current_dump_size;
 207         size_t total_dump_size;
 208
 209         phys_addr_t mba_phys;
 210         size_t mba_size;
 211         size_t dp_size;
 212
 213         phys_addr_t mpss_phys;
 214         phys_addr_t mpss_reloc;
 215         size_t mpss_size;
 216
 217         struct qcom_rproc_glink glink_subdev;
 218         struct qcom_rproc_subdev smd_subdev;
 219         struct qcom_rproc_ssr ssr_subdev;
 220         struct qcom_sysmon *sysmon;
 221         bool need_mem_protection;
 222         bool has_alt_reset;
 223         bool has_mba_logs;
 224         bool has_spare_reg;
 225         bool has_qaccept_regs;
 226         bool has_ext_cntl_regs;
 227         bool has_vq6;
 228         int mpss_perm;
 229         int mba_perm;
 230         const char *hexagon_mdt_image;
 231         int version;
 232 };
 233
 234 enum {
 235         MSS_MSM8916,
 236         MSS_MSM8974,
 237         MSS_MSM8996,
 238         MSS_MSM8998,
 239         MSS_SC7180,
 240         MSS_SC7280,
 241         MSS_SDM845,
 242 };
 243
 244 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 245                                const struct qcom_mss_reg_res *reg_res)
 246 {
 247         int rc;
 248         int i;
 249
 250         if (!reg_res)
 251                 return 0;
 252
 253         for (i = 0; reg_res[i].supply; i++) {
 254                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 255                 if (IS_ERR(regs[i].reg)) {
 256                         rc = PTR_ERR(regs[i].reg);
 257                         if (rc != -EPROBE_DEFER)
 258                                 dev_err(dev, "Failed to get %s\n regulator",
 259                                         reg_res[i].supply);
 260                         return rc;
 261                 }
 262
 263                 regs[i].uV = reg_res[i].uV;
 264                 regs[i].uA = reg_res[i].uA;
 265         }
 266
 267         return i;
 268 }
 269
 270 static int q6v5_regulator_enable(struct q6v5 *qproc,
 271                                  struct reg_info *regs, int count)
 272 {
 273         int ret;
 274         int i;
 275
 276         for (i = 0; i < count; i++) {
 277                 if (regs[i].uV > 0) {
 278                         ret = regulator_set_voltage(regs[i].reg,
 279                                         regs[i].uV, INT_MAX);
 280                         if (ret) {
 281                                 dev_err(qproc->dev,
 282                                         "Failed to request voltage for %d.\n",
 283                                                 i);
 284                                 goto err;
 285                         }
 286                 }
 287
 288                 if (regs[i].uA > 0) {
 289                         ret = regulator_set_load(regs[i].reg,
 290                                                  regs[i].uA);
 291                         if (ret < 0) {
 292                                 dev_err(qproc->dev,
 293                                         "Failed to set regulator mode\n");
 294                                 goto err;
 295                         }
 296                 }
 297
 298                 ret = regulator_enable(regs[i].reg);
 299                 if (ret) {
 300                         dev_err(qproc->dev, "Regulator enable failed\n");
 301                         goto err;
 302                 }
 303         }
 304
 305         return 0;
 306 err:
 307         for (; i >= 0; i--) {
 308                 if (regs[i].uV > 0)
 309                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 310
 311                 if (regs[i].uA > 0)
 312                         regulator_set_load(regs[i].reg, 0);
 313
 314                 regulator_disable(regs[i].reg);
 315         }
 316
 317         return ret;
 318 }
 319
 320 static void q6v5_regulator_disable(struct q6v5 *qproc,
 321                                    struct reg_info *regs, int count)
 322 {
 323         int i;
 324
 325         for (i = 0; i < count; i++) {
 326                 if (regs[i].uV > 0)
 327                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 328
 329                 if (regs[i].uA > 0)
 330                         regulator_set_load(regs[i].reg, 0);
 331
 332                 regulator_disable(regs[i].reg);
 333         }
 334 }
 335
 336 static int q6v5_clk_enable(struct device *dev,
 337                            struct clk **clks, int count)
 338 {
 339         int rc;
 340         int i;
 341
 342         for (i = 0; i < count; i++) {
 343                 rc = clk_prepare_enable(clks[i]);
 344                 if (rc) {
 345                         dev_err(dev, "Clock enable failed\n");
 346                         goto err;
 347                 }
 348         }
 349
 350         return 0;
 351 err:
 352         for (i--; i >= 0; i--)
 353                 clk_disable_unprepare(clks[i]);
 354
 355         return rc;
 356 }
 357
 358 static void q6v5_clk_disable(struct device *dev,
 359                              struct clk **clks, int count)
 360 {
 361         int i;
 362
 363         for (i = 0; i < count; i++)
 364                 clk_disable_unprepare(clks[i]);
 365 }
 366
 367 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 368                            size_t pd_count)
 369 {
 370         int ret;
 371         int i;
 372
 373         for (i = 0; i < pd_count; i++) {
 374                 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 375                 ret = pm_runtime_get_sync(pds[i]);
 376                 if (ret < 0) {
 377                         pm_runtime_put_noidle(pds[i]);
 378                         dev_pm_genpd_set_performance_state(pds[i], 0);
 379                         goto unroll_pd_votes;
 380                 }
 381         }
 382
 383         return 0;
 384
 385 unroll_pd_votes:
 386         for (i--; i >= 0; i--) {
 387                 dev_pm_genpd_set_performance_state(pds[i], 0);
 388                 pm_runtime_put(pds[i]);
 389         }
 390
 391         return ret;
 392 }
 393
 394 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 395                              size_t pd_count)
 396 {
 397         int i;
 398
 399         for (i = 0; i < pd_count; i++) {
 400                 dev_pm_genpd_set_performance_state(pds[i], 0);
 401                 pm_runtime_put(pds[i]);
 402         }
 403 }
 404
 405 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 406                                    bool local, bool remote, phys_addr_t addr,
 407                                    size_t size)
 408 {
 409         struct qcom_scm_vmperm next[2];
 410         int perms = 0;
 411
 412         if (!qproc->need_mem_protection)
 413                 return 0;
 414
 415         if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
 416             remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
 417                 return 0;
 418
 419         if (local) {
 420                 next[perms].vmid = QCOM_SCM_VMID_HLOS;
 421                 next[perms].perm = QCOM_SCM_PERM_RWX;
 422                 perms++;
 423         }
 424
 425         if (remote) {
 426                 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
 427                 next[perms].perm = QCOM_SCM_PERM_RW;
 428                 perms++;
 429         }
 430
 431         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 432                                    current_perm, next, perms);
 433 }
 434
 435 static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region)
 436 {
 437         const struct firmware *dp_fw;
 438
 439         if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
 440                 return;
 441
 442         if (SZ_1M + dp_fw->size <= qproc->mba_size) {
 443                 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
 444                 qproc->dp_size = dp_fw->size;
 445         }
 446
 447         release_firmware(dp_fw);
 448 }
 449
 450 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 451 {
 452         struct q6v5 *qproc = rproc->priv;
 453         void *mba_region;
 454
 455         /* MBA is restricted to a maximum size of 1M */
 456         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 457                 dev_err(qproc->dev, "MBA firmware load failed\n");
 458                 return -EINVAL;
 459         }
 460
 461         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 462         if (!mba_region) {
 463                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 464                         &qproc->mba_phys, qproc->mba_size);
 465                 return -EBUSY;
 466         }
 467
 468         memcpy(mba_region, fw->data, fw->size);
 469         q6v5_debug_policy_load(qproc, mba_region);
 470         memunmap(mba_region);
 471
 472         return 0;
 473 }
 474
 475 static int q6v5_reset_assert(struct q6v5 *qproc)
 476 {
 477         int ret;
 478
 479         if (qproc->has_alt_reset) {
 480                 reset_control_assert(qproc->pdc_reset);
 481                 ret = reset_control_reset(qproc->mss_restart);
 482                 reset_control_deassert(qproc->pdc_reset);
 483         } else if (qproc->has_spare_reg) {
 484                 /*
 485                  * When the AXI pipeline is being reset with the Q6 modem partly
 486                  * operational there is possibility of AXI valid signal to
 487                  * glitch, leading to spurious transactions and Q6 hangs. A work
 488                  * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
 489                  * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
 490                  * is withdrawn post MSS assert followed by a MSS deassert,
 491                  * while holding the PDC reset.
 492                  */
 493                 reset_control_assert(qproc->pdc_reset);
 494                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 495                                    AXI_GATING_VALID_OVERRIDE, 1);
 496                 reset_control_assert(qproc->mss_restart);
 497                 reset_control_deassert(qproc->pdc_reset);
 498                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 499                                    AXI_GATING_VALID_OVERRIDE, 0);
 500                 ret = reset_control_deassert(qproc->mss_restart);
 501         } else if (qproc->has_ext_cntl_regs) {
 502                 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 503                 reset_control_assert(qproc->pdc_reset);
 504                 reset_control_assert(qproc->mss_restart);
 505                 reset_control_deassert(qproc->pdc_reset);
 506                 ret = reset_control_deassert(qproc->mss_restart);
 507         } else {
 508                 ret = reset_control_assert(qproc->mss_restart);
 509         }
 510
 511         return ret;
 512 }
 513
 514 static int q6v5_reset_deassert(struct q6v5 *qproc)
 515 {
 516         int ret;
 517
 518         if (qproc->has_alt_reset) {
 519                 reset_control_assert(qproc->pdc_reset);
 520                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 521                 ret = reset_control_reset(qproc->mss_restart);
 522                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 523                 reset_control_deassert(qproc->pdc_reset);
 524         } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
 525                 ret = reset_control_reset(qproc->mss_restart);
 526         } else {
 527                 ret = reset_control_deassert(qproc->mss_restart);
 528         }
 529
 530         return ret;
 531 }
 532
 533 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 534 {
 535         unsigned long timeout;
 536         s32 val;
 537
 538         timeout = jiffies + msecs_to_jiffies(ms);
 539         for (;;) {
 540                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 541                 if (val)
 542                         break;
 543
 544                 if (time_after(jiffies, timeout))
 545                         return -ETIMEDOUT;
 546
 547                 msleep(1);
 548         }
 549
 550         return val;
 551 }
 552
 553 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 554 {
 555
 556         unsigned long timeout;
 557         s32 val;
 558
 559         timeout = jiffies + msecs_to_jiffies(ms);
 560         for (;;) {
 561                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 562                 if (val < 0)
 563                         break;
 564
 565                 if (!status && val)
 566                         break;
 567                 else if (status && val == status)
 568                         break;
 569
 570                 if (time_after(jiffies, timeout))
 571                         return -ETIMEDOUT;
 572
 573                 msleep(1);
 574         }
 575
 576         return val;
 577 }
 578
 579 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
 580 {
 581         struct rproc *rproc = qproc->rproc;
 582         void *data;
 583         void *mba_region;
 584
 585         if (!qproc->has_mba_logs)
 586                 return;
 587
 588         if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
 589                                     qproc->mba_size))
 590                 return;
 591
 592         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 593         if (!mba_region)
 594                 return;
 595
 596         data = vmalloc(MBA_LOG_SIZE);
 597         if (data) {
 598                 memcpy(data, mba_region, MBA_LOG_SIZE);
 599                 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
 600         }
 601         memunmap(mba_region);
 602 }
 603
 604 static int q6v5proc_reset(struct q6v5 *qproc)
 605 {
 606         u32 val;
 607         int ret;
 608         int i;
 609
 610         if (qproc->version == MSS_SDM845) {
 611                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 612                 val |= Q6SS_CBCR_CLKEN;
 613                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 614
 615                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 616                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 617                                          Q6SS_CBCR_TIMEOUT_US);
 618                 if (ret) {
 619                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 620                         return -ETIMEDOUT;
 621                 }
 622
 623                 /* De-assert QDSP6 stop core */
 624                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 625                 /* Trigger boot FSM */
 626                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 627
 628                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 629                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 630                 if (ret) {
 631                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 632                         /* Reset the modem so that boot FSM is in reset state */
 633                         q6v5_reset_deassert(qproc);
 634                         return ret;
 635                 }
 636
 637                 goto pbl_wait;
 638         } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
 639                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 640                 val |= Q6SS_CBCR_CLKEN;
 641                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 642
 643                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 644                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 645                                          Q6SS_CBCR_TIMEOUT_US);
 646                 if (ret) {
 647                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 648                         return -ETIMEDOUT;
 649                 }
 650
 651                 /* Turn on the XO clock needed for PLL setup */
 652                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 653                 val |= Q6SS_CBCR_CLKEN;
 654                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 655
 656                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 657                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 658                                          Q6SS_CBCR_TIMEOUT_US);
 659                 if (ret) {
 660                         dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
 661                         return -ETIMEDOUT;
 662                 }
 663
 664                 /* Configure Q6 core CBCR to auto-enable after reset sequence */
 665                 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
 666                 val |= Q6SS_CBCR_CLKEN;
 667                 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
 668
 669                 /* De-assert the Q6 stop core signal */
 670                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 671
 672                 /* Wait for 10 us for any staggering logic to settle */
 673                 usleep_range(10, 20);
 674
 675                 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
 676                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 677
 678                 /* Poll the MSS_STATUS for FSM completion */
 679                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 680                                          val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 681                 if (ret) {
 682                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 683                         /* Reset the modem so that boot FSM is in reset state */
 684                         q6v5_reset_deassert(qproc);
 685                         return ret;
 686                 }
 687                 goto pbl_wait;
 688         } else if (qproc->version == MSS_MSM8996 ||
 689                    qproc->version == MSS_MSM8998) {
 690                 int mem_pwr_ctl;
 691
 692                 /* Override the ACC value if required */
 693                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 694                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 695
 696                 /* Assert resets, stop core */
 697                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 698                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 699                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 700
 701                 /* BHS require xo cbcr to be enabled */
 702                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 703                 val |= Q6SS_CBCR_CLKEN;
 704                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 705
 706                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 707                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 708                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 709                                          Q6SS_CBCR_TIMEOUT_US);
 710                 if (ret) {
 711                         dev_err(qproc->dev,
 712                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 713                         return ret;
 714                 }
 715                 /* Enable power block headswitch and wait for it to stabilize */
 716                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 717                 val |= QDSP6v56_BHS_ON;
 718                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 719                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 720                 udelay(1);
 721
 722                 /* Put LDO in bypass mode */
 723                 val |= QDSP6v56_LDO_BYP;
 724                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 725
 726                 /* Deassert QDSP6 compiler memory clamp */
 727                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 728                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 729                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 730
 731                 /* Deassert memory peripheral sleep and L2 memory standby */
 732                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 733                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 734
 735                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 736                 if (qproc->version == MSS_MSM8996) {
 737                         mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
 738                         i = 19;
 739                 } else {
 740                         /* MSS_MSM8998 */
 741                         mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
 742                         i = 28;
 743                 }
 744                 val = readl(qproc->reg_base + mem_pwr_ctl);
 745                 for (; i >= 0; i--) {
 746                         val |= BIT(i);
 747                         writel(val, qproc->reg_base + mem_pwr_ctl);
 748                         /*
 749                          * Read back value to ensure the write is done then
 750                          * wait for 1us for both memory peripheral and data
 751                          * array to turn on.
 752                          */
 753                         val |= readl(qproc->reg_base + mem_pwr_ctl);
 754                         udelay(1);
 755                 }
 756                 /* Remove word line clamp */
 757                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 758                 val &= ~QDSP6v56_CLAMP_WL;
 759                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 760         } else {
 761                 /* Assert resets, stop core */
 762                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 763                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 764                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 765
 766                 /* Enable power block headswitch and wait for it to stabilize */
 767                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 768                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 769                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 770                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 771                 udelay(1);
 772                 /*
 773                  * Turn on memories. L2 banks should be done individually
 774                  * to minimize inrush current.
 775                  */
 776                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 777                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 778                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 779                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 780                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 781                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 782                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 783                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 784                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 785                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 786         }
 787         /* Remove IO clamp */
 788         val &= ~Q6SS_CLAMP_IO;
 789         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 790
 791         /* Bring core out of reset */
 792         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 793         val &= ~Q6SS_CORE_ARES;
 794         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 795
 796         /* Turn on core clock */
 797         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 798         val |= Q6SS_CLK_ENABLE;
 799         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 800
 801         /* Start core execution */
 802         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 803         val &= ~Q6SS_STOP_CORE;
 804         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 805
 806 pbl_wait:
 807         /* Wait for PBL status */
 808         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 809         if (ret == -ETIMEDOUT) {
 810                 dev_err(qproc->dev, "PBL boot timed out\n");
 811         } else if (ret != RMB_PBL_SUCCESS) {
 812                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 813                 ret = -EINVAL;
 814         } else {
 815                 ret = 0;
 816         }
 817
 818         return ret;
 819 }
 820
 821 static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 822 {
 823         unsigned int val;
 824         int ret;
 825
 826         if (!qproc->has_qaccept_regs)
 827                 return 0;
 828
 829         if (qproc->has_ext_cntl_regs) {
 830                 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 831                 regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
 832
 833                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
 834                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
 835                 if (ret) {
 836                         dev_err(qproc->dev, "failed to enable axim1 clock\n");
 837                         return -ETIMEDOUT;
 838                 }
 839         }
 840
 841         regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 842
 843         /* Wait for accept */
 844         ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
 845                                        QACCEPT_TIMEOUT_US);
 846         if (ret) {
 847                 dev_err(qproc->dev, "qchannel enable failed\n");
 848                 return -ETIMEDOUT;
 849         }
 850
 851         return 0;
 852 }
 853
 854 static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 855 {
 856         int ret;
 857         unsigned int val, retry;
 858         unsigned int nretry = 10;
 859         bool takedown_complete = false;
 860
 861         if (!qproc->has_qaccept_regs)
 862                 return;
 863
 864         while (!takedown_complete && nretry) {
 865                 nretry--;
 866
 867                 /* Wait for active transactions to complete */
 868                 regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
 869                                          QACCEPT_TIMEOUT_US);
 870
 871                 /* Request Q-channel transaction takedown */
 872                 regmap_write(map, offset + QACCEPT_REQ_REG, 0);
 873
 874                 /*
 875                  * If the request is denied, reset the Q-channel takedown request,
 876                  * wait for active transactions to complete and retry takedown.
 877                  */
 878                 retry = 10;
 879                 while (retry) {
 880                         usleep_range(5, 10);
 881                         retry--;
 882                         ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
 883                         if (!ret && val) {
 884                                 regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 885                                 break;
 886                         }
 887
 888                         ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
 889                         if (!ret && !val) {
 890                                 takedown_complete = true;
 891                                 break;
 892                         }
 893                 }
 894
 895                 if (!retry)
 896                         break;
 897         }
 898
 899         /* Rely on mss_restart to clear out pending transactions on takedown failure */
 900         if (!takedown_complete)
 901                 dev_err(qproc->dev, "qchannel takedown failed\n");
 902 }
 903
 904 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 905                                    struct regmap *halt_map,
 906                                    u32 offset)
 907 {
 908         unsigned int val;
 909         int ret;
 910
 911         /* Check if we're already idle */
 912         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 913         if (!ret && val)
 914                 return;
 915
 916         /* Assert halt request */
 917         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 918
 919         /* Wait for halt */
 920         regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
 921                                  val, 1000, HALT_ACK_TIMEOUT_US);
 922
 923         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 924         if (ret || !val)
 925                 dev_err(qproc->dev, "port failed halt\n");
 926
 927         /* Clear halt request (port will remain halted until reset) */
 928         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 929 }
 930
 931 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 932 {
 933         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 934         dma_addr_t phys;
 935         void *metadata;
 936         int mdata_perm;
 937         int xferop_ret;
 938         size_t size;
 939         void *ptr;
 940         int ret;
 941
 942         metadata = qcom_mdt_read_metadata(fw, &size);
 943         if (IS_ERR(metadata))
 944                 return PTR_ERR(metadata);
 945
 946         ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
 947         if (!ptr) {
 948                 kfree(metadata);
 949                 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 950                 return -ENOMEM;
 951         }
 952
 953         memcpy(ptr, metadata, size);
 954
 955         /* Hypervisor mapping to access metadata by modem */
 956         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 957         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
 958                                       phys, size);
 959         if (ret) {
 960                 dev_err(qproc->dev,
 961                         "assigning Q6 access to metadata failed: %d\n", ret);
 962                 ret = -EAGAIN;
 963                 goto free_dma_attrs;
 964         }
 965
 966         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 967         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 968
 969         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 970         if (ret == -ETIMEDOUT)
 971                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 972         else if (ret < 0)
 973                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
 974
 975         /* Metadata authentication done, remove modem access */
 976         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
 977                                              phys, size);
 978         if (xferop_ret)
 979                 dev_warn(qproc->dev,
 980                          "mdt buffer not reclaimed system may become unstable\n");
 981
 982 free_dma_attrs:
 983         dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
 984         kfree(metadata);
 985
 986         return ret < 0 ? ret : 0;
 987 }
 988
 989 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
 990 {
 991         if (phdr->p_type != PT_LOAD)
 992                 return false;
 993
 994         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 995                 return false;
 996
 997         if (!phdr->p_memsz)
 998                 return false;
 999
1000         return true;
1001 }
1002
1003 static int q6v5_mba_load(struct q6v5 *qproc)
1004 {
1005         int ret;
1006         int xfermemop_ret;
1007         bool mba_load_err = false;
1008
1009         ret = qcom_q6v5_prepare(&qproc->q6v5);
1010         if (ret)
1011                 return ret;
1012
1013         ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1014         if (ret < 0) {
1015                 dev_err(qproc->dev, "failed to enable proxy power domains\n");
1016                 goto disable_irqs;
1017         }
1018
1019         ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
1020                                     qproc->fallback_proxy_reg_count);
1021         if (ret) {
1022                 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
1023                 goto disable_proxy_pds;
1024         }
1025
1026         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
1027                                     qproc->proxy_reg_count);
1028         if (ret) {
1029                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
1030                 goto disable_fallback_proxy_reg;
1031         }
1032
1033         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
1034                               qproc->proxy_clk_count);
1035         if (ret) {
1036                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
1037                 goto disable_proxy_reg;
1038         }
1039
1040         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
1041                                     qproc->active_reg_count);
1042         if (ret) {
1043                 dev_err(qproc->dev, "failed to enable supplies\n");
1044                 goto disable_proxy_clk;
1045         }
1046
1047         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
1048                               qproc->reset_clk_count);
1049         if (ret) {
1050                 dev_err(qproc->dev, "failed to enable reset clocks\n");
1051                 goto disable_vdd;
1052         }
1053
1054         ret = q6v5_reset_deassert(qproc);
1055         if (ret) {
1056                 dev_err(qproc->dev, "failed to deassert mss restart\n");
1057                 goto disable_reset_clks;
1058         }
1059
1060         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
1061                               qproc->active_clk_count);
1062         if (ret) {
1063                 dev_err(qproc->dev, "failed to enable clocks\n");
1064                 goto assert_reset;
1065         }
1066
1067         ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1068         if (ret) {
1069                 dev_err(qproc->dev, "failed to enable axi bridge\n");
1070                 goto disable_active_clks;
1071         }
1072
1073         /*
1074          * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
1075          * the Q6 access to this region.
1076          */
1077         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1078                                       qproc->mpss_phys, qproc->mpss_size);
1079         if (ret) {
1080                 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
1081                 goto disable_active_clks;
1082         }
1083
1084         /* Assign MBA image access in DDR to q6 */
1085         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
1086                                       qproc->mba_phys, qproc->mba_size);
1087         if (ret) {
1088                 dev_err(qproc->dev,
1089                         "assigning Q6 access to mba memory failed: %d\n", ret);
1090                 goto disable_active_clks;
1091         }
1092
1093         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
1094         if (qproc->dp_size) {
1095                 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1096                 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1097         }
1098
1099         ret = q6v5proc_reset(qproc);
1100         if (ret)
1101                 goto reclaim_mba;
1102
1103         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
1104         if (ret == -ETIMEDOUT) {
1105                 dev_err(qproc->dev, "MBA boot timed out\n");
1106                 goto halt_axi_ports;
1107         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
1108                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
1109                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1110                 ret = -EINVAL;
1111                 goto halt_axi_ports;
1112         }
1113
1114         qproc->dump_mba_loaded = true;
1115         return 0;
1116
1117 halt_axi_ports:
1118         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1119         if (qproc->has_vq6)
1120                 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1121         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1122         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1123         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1124         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1125         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1126         mba_load_err = true;
1127 reclaim_mba:
1128         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1129                                                 false, qproc->mba_phys,
1130                                                 qproc->mba_size);
1131         if (xfermemop_ret) {
1132                 dev_err(qproc->dev,
1133                         "Failed to reclaim mba buffer, system may become unstable\n");
1134         } else if (mba_load_err) {
1135                 q6v5_dump_mba_logs(qproc);
1136         }
1137
1138 disable_active_clks:
1139         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1140                          qproc->active_clk_count);
1141 assert_reset:
1142         q6v5_reset_assert(qproc);
1143 disable_reset_clks:
1144         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1145                          qproc->reset_clk_count);
1146 disable_vdd:
1147         q6v5_regulator_disable(qproc, qproc->active_regs,
1148                                qproc->active_reg_count);
1149 disable_proxy_clk:
1150         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1151                          qproc->proxy_clk_count);
1152 disable_proxy_reg:
1153         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1154                                qproc->proxy_reg_count);
1155 disable_fallback_proxy_reg:
1156         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1157                                qproc->fallback_proxy_reg_count);
1158 disable_proxy_pds:
1159         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1160 disable_irqs:
1161         qcom_q6v5_unprepare(&qproc->q6v5);
1162
1163         return ret;
1164 }
1165
1166 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1167 {
1168         int ret;
1169         u32 val;
1170
1171         qproc->dump_mba_loaded = false;
1172         qproc->dp_size = 0;
1173
1174         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1175         if (qproc->has_vq6)
1176                 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1177         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1178         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1179         if (qproc->version == MSS_MSM8996) {
1180                 /*
1181                  * To avoid high MX current during LPASS/MSS restart.
1182                  */
1183                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1184                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1185                         QDSP6v56_CLAMP_QMC_MEM;
1186                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1187         }
1188
1189         if (qproc->has_ext_cntl_regs) {
1190                 regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
1191
1192                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
1193                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
1194                 if (ret)
1195                         dev_err(qproc->dev, "failed to enable axim1 clock\n");
1196
1197                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
1198                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
1199                 if (ret)
1200                         dev_err(qproc->dev, "failed to enable crypto clock\n");
1201         }
1202
1203         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1204         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1205         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1206
1207         q6v5_reset_assert(qproc);
1208
1209         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1210                          qproc->reset_clk_count);
1211         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1212                          qproc->active_clk_count);
1213         q6v5_regulator_disable(qproc, qproc->active_regs,
1214                                qproc->active_reg_count);
1215
1216         /* In case of failure or coredump scenario where reclaiming MBA memory
1217          * could not happen reclaim it here.
1218          */
1219         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1220                                       qproc->mba_phys,
1221                                       qproc->mba_size);
1222         WARN_ON(ret);
1223
1224         ret = qcom_q6v5_unprepare(&qproc->q6v5);
1225         if (ret) {
1226                 q6v5_pds_disable(qproc, qproc->proxy_pds,
1227                                  qproc->proxy_pd_count);
1228                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1229                                  qproc->proxy_clk_count);
1230                 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1231                                        qproc->fallback_proxy_reg_count);
1232                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1233                                        qproc->proxy_reg_count);
1234         }
1235 }
1236
1237 static int q6v5_reload_mba(struct rproc *rproc)
1238 {
1239         struct q6v5 *qproc = rproc->priv;
1240         const struct firmware *fw;
1241         int ret;
1242
1243         ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1244         if (ret < 0)
1245                 return ret;
1246
1247         q6v5_load(rproc, fw);
1248         ret = q6v5_mba_load(qproc);
1249         release_firmware(fw);
1250
1251         return ret;
1252 }
1253
1254 static int q6v5_mpss_load(struct q6v5 *qproc)
1255 {
1256         const struct elf32_phdr *phdrs;
1257         const struct elf32_phdr *phdr;
1258         const struct firmware *seg_fw;
1259         const struct firmware *fw;
1260         struct elf32_hdr *ehdr;
1261         phys_addr_t mpss_reloc;
1262         phys_addr_t boot_addr;
1263         phys_addr_t min_addr = PHYS_ADDR_MAX;
1264         phys_addr_t max_addr = 0;
1265         u32 code_length;
1266         bool relocate = false;
1267         char *fw_name;
1268         size_t fw_name_len;
1269         ssize_t offset;
1270         size_t size = 0;
1271         void *ptr;
1272         int ret;
1273         int i;
1274
1275         fw_name_len = strlen(qproc->hexagon_mdt_image);
1276         if (fw_name_len <= 4)
1277                 return -EINVAL;
1278
1279         fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1280         if (!fw_name)
1281                 return -ENOMEM;
1282
1283         ret = request_firmware(&fw, fw_name, qproc->dev);
1284         if (ret < 0) {
1285                 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1286                 goto out;
1287         }
1288
1289         /* Initialize the RMB validator */
1290         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1291
1292         ret = q6v5_mpss_init_image(qproc, fw);
1293         if (ret)
1294                 goto release_firmware;
1295
1296         ehdr = (struct elf32_hdr *)fw->data;
1297         phdrs = (struct elf32_phdr *)(ehdr + 1);
1298
1299         for (i = 0; i < ehdr->e_phnum; i++) {
1300                 phdr = &phdrs[i];
1301
1302                 if (!q6v5_phdr_valid(phdr))
1303                         continue;
1304
1305                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1306                         relocate = true;
1307
1308                 if (phdr->p_paddr < min_addr)
1309                         min_addr = phdr->p_paddr;
1310
1311                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1312                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1313         }
1314
1315         /*
1316          * In case of a modem subsystem restart on secure devices, the modem
1317          * memory can be reclaimed only after MBA is loaded.
1318          */
1319         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1320                                 qproc->mpss_phys, qproc->mpss_size);
1321
1322         /* Share ownership between Linux and MSS, during segment loading */
1323         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1324                                       qproc->mpss_phys, qproc->mpss_size);
1325         if (ret) {
1326                 dev_err(qproc->dev,
1327                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1328                 ret = -EAGAIN;
1329                 goto release_firmware;
1330         }
1331
1332         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1333         qproc->mpss_reloc = mpss_reloc;
1334         /* Load firmware segments */
1335         for (i = 0; i < ehdr->e_phnum; i++) {
1336                 phdr = &phdrs[i];
1337
1338                 if (!q6v5_phdr_valid(phdr))
1339                         continue;
1340
1341                 offset = phdr->p_paddr - mpss_reloc;
1342                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1343                         dev_err(qproc->dev, "segment outside memory range\n");
1344                         ret = -EINVAL;
1345                         goto release_firmware;
1346                 }
1347
1348                 if (phdr->p_filesz > phdr->p_memsz) {
1349                         dev_err(qproc->dev,
1350                                 "refusing to load segment %d with p_filesz > p_memsz\n",
1351                                 i);
1352                         ret = -EINVAL;
1353                         goto release_firmware;
1354                 }
1355
1356                 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1357                 if (!ptr) {
1358                         dev_err(qproc->dev,
1359                                 "unable to map memory region: %pa+%zx-%x\n",
1360                                 &qproc->mpss_phys, offset, phdr->p_memsz);
1361                         goto release_firmware;
1362                 }
1363
1364                 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1365                         /* Firmware is large enough to be non-split */
1366                         if (phdr->p_offset + phdr->p_filesz > fw->size) {
1367                                 dev_err(qproc->dev,
1368                                         "failed to load segment %d from truncated file %s\n",
1369                                         i, fw_name);
1370                                 ret = -EINVAL;
1371                                 memunmap(ptr);
1372                                 goto release_firmware;
1373                         }
1374
1375                         memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1376                 } else if (phdr->p_filesz) {
1377                         /* Replace "xxx.xxx" with "xxx.bxx" */
1378                         sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1379                         ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1380                                                         ptr, phdr->p_filesz);
1381                         if (ret) {
1382                                 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1383                                 memunmap(ptr);
1384                                 goto release_firmware;
1385                         }
1386
1387                         if (seg_fw->size != phdr->p_filesz) {
1388                                 dev_err(qproc->dev,
1389                                         "failed to load segment %d from truncated file %s\n",
1390                                         i, fw_name);
1391                                 ret = -EINVAL;
1392                                 release_firmware(seg_fw);
1393                                 memunmap(ptr);
1394                                 goto release_firmware;
1395                         }
1396
1397                         release_firmware(seg_fw);
1398                 }
1399
1400                 if (phdr->p_memsz > phdr->p_filesz) {
1401                         memset(ptr + phdr->p_filesz, 0,
1402                                phdr->p_memsz - phdr->p_filesz);
1403                 }
1404                 memunmap(ptr);
1405                 size += phdr->p_memsz;
1406
1407                 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1408                 if (!code_length) {
1409                         boot_addr = relocate ? qproc->mpss_phys : min_addr;
1410                         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1411                         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1412                 }
1413                 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1414
1415                 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1416                 if (ret < 0) {
1417                         dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1418                                 ret);
1419                         goto release_firmware;
1420                 }
1421         }
1422
1423         /* Transfer ownership of modem ddr region to q6 */
1424         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1425                                       qproc->mpss_phys, qproc->mpss_size);
1426         if (ret) {
1427                 dev_err(qproc->dev,
1428                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1429                 ret = -EAGAIN;
1430                 goto release_firmware;
1431         }
1432
1433         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1434         if (ret == -ETIMEDOUT)
1435                 dev_err(qproc->dev, "MPSS authentication timed out\n");
1436         else if (ret < 0)
1437                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1438
1439         qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1440
1441 release_firmware:
1442         release_firmware(fw);
1443 out:
1444         kfree(fw_name);
1445
1446         return ret < 0 ? ret : 0;
1447 }
1448
1449 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1450                                    struct rproc_dump_segment *segment,
1451                                    void *dest, size_t cp_offset, size_t size)
1452 {
1453         int ret = 0;
1454         struct q6v5 *qproc = rproc->priv;
1455         int offset = segment->da - qproc->mpss_reloc;
1456         void *ptr = NULL;
1457
1458         /* Unlock mba before copying segments */
1459         if (!qproc->dump_mba_loaded) {
1460                 ret = q6v5_reload_mba(rproc);
1461                 if (!ret) {
1462                         /* Reset ownership back to Linux to copy segments */
1463                         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1464                                                       true, false,
1465                                                       qproc->mpss_phys,
1466                                                       qproc->mpss_size);
1467                 }
1468         }
1469
1470         if (!ret)
1471                 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1472
1473         if (ptr) {
1474                 memcpy(dest, ptr, size);
1475                 memunmap(ptr);
1476         } else {
1477                 memset(dest, 0xff, size);
1478         }
1479
1480         qproc->current_dump_size += size;
1481
1482         /* Reclaim mba after copying segments */
1483         if (qproc->current_dump_size == qproc->total_dump_size) {
1484                 if (qproc->dump_mba_loaded) {
1485                         /* Try to reset ownership back to Q6 */
1486                         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1487                                                 false, true,
1488                                                 qproc->mpss_phys,
1489                                                 qproc->mpss_size);
1490                         q6v5_mba_reclaim(qproc);
1491                 }
1492         }
1493 }
1494
1495 static int q6v5_start(struct rproc *rproc)
1496 {
1497         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1498         int xfermemop_ret;
1499         int ret;
1500
1501         ret = q6v5_mba_load(qproc);
1502         if (ret)
1503                 return ret;
1504
1505         dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1506                  qproc->dp_size ? "" : "out");
1507
1508         ret = q6v5_mpss_load(qproc);
1509         if (ret)
1510                 goto reclaim_mpss;
1511
1512         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1513         if (ret == -ETIMEDOUT) {
1514                 dev_err(qproc->dev, "start timed out\n");
1515                 goto reclaim_mpss;
1516         }
1517
1518         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1519                                                 false, qproc->mba_phys,
1520                                                 qproc->mba_size);
1521         if (xfermemop_ret)
1522                 dev_err(qproc->dev,
1523                         "Failed to reclaim mba buffer system may become unstable\n");
1524
1525         /* Reset Dump Segment Mask */
1526         qproc->current_dump_size = 0;
1527
1528         return 0;
1529
1530 reclaim_mpss:
1531         q6v5_mba_reclaim(qproc);
1532         q6v5_dump_mba_logs(qproc);
1533
1534         return ret;
1535 }
1536
1537 static int q6v5_stop(struct rproc *rproc)
1538 {
1539         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1540         int ret;
1541
1542         ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1543         if (ret == -ETIMEDOUT)
1544                 dev_err(qproc->dev, "timed out on wait\n");
1545
1546         q6v5_mba_reclaim(qproc);
1547
1548         return 0;
1549 }
1550
1551 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1552                                             const struct firmware *mba_fw)
1553 {
1554         const struct firmware *fw;
1555         const struct elf32_phdr *phdrs;
1556         const struct elf32_phdr *phdr;
1557         const struct elf32_hdr *ehdr;
1558         struct q6v5 *qproc = rproc->priv;
1559         unsigned long i;
1560         int ret;
1561
1562         ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1563         if (ret < 0) {
1564                 dev_err(qproc->dev, "unable to load %s\n",
1565                         qproc->hexagon_mdt_image);
1566                 return ret;
1567         }
1568
1569         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1570
1571         ehdr = (struct elf32_hdr *)fw->data;
1572         phdrs = (struct elf32_phdr *)(ehdr + 1);
1573         qproc->total_dump_size = 0;
1574
1575         for (i = 0; i < ehdr->e_phnum; i++) {
1576                 phdr = &phdrs[i];
1577
1578                 if (!q6v5_phdr_valid(phdr))
1579                         continue;
1580
1581                 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1582                                                         phdr->p_memsz,
1583                                                         qcom_q6v5_dump_segment,
1584                                                         NULL);
1585                 if (ret)
1586                         break;
1587
1588                 qproc->total_dump_size += phdr->p_memsz;
1589         }
1590
1591         release_firmware(fw);
1592         return ret;
1593 }
1594
1595 static const struct rproc_ops q6v5_ops = {
1596         .start = q6v5_start,
1597         .stop = q6v5_stop,
1598         .parse_fw = qcom_q6v5_register_dump_segments,
1599         .load = q6v5_load,
1600 };
1601
1602 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1603 {
1604         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1605
1606         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1607                          qproc->proxy_clk_count);
1608         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1609                                qproc->proxy_reg_count);
1610         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1611                                qproc->fallback_proxy_reg_count);
1612         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1613 }
1614
1615 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1616 {
1617         struct of_phandle_args args;
1618         int halt_cell_cnt = 3;
1619         int ret;
1620
1621         qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1622         if (IS_ERR(qproc->reg_base))
1623                 return PTR_ERR(qproc->reg_base);
1624
1625         qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
1626         if (IS_ERR(qproc->rmb_base))
1627                 return PTR_ERR(qproc->rmb_base);
1628
1629         if (qproc->has_vq6)
1630                 halt_cell_cnt++;
1631
1632         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1633                                                "qcom,halt-regs", halt_cell_cnt, 0, &args);
1634         if (ret < 0) {
1635                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1636                 return -EINVAL;
1637         }
1638
1639         qproc->halt_map = syscon_node_to_regmap(args.np);
1640         of_node_put(args.np);
1641         if (IS_ERR(qproc->halt_map))
1642                 return PTR_ERR(qproc->halt_map);
1643
1644         qproc->halt_q6 = args.args[0];
1645         qproc->halt_modem = args.args[1];
1646         qproc->halt_nc = args.args[2];
1647
1648         if (qproc->has_vq6)
1649                 qproc->halt_vq6 = args.args[3];
1650
1651         if (qproc->has_qaccept_regs) {
1652                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1653                                                        "qcom,qaccept-regs",
1654                                                        3, 0, &args);
1655                 if (ret < 0) {
1656                         dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
1657                         return -EINVAL;
1658                 }
1659
1660                 qproc->qaccept_mdm = args.args[0];
1661                 qproc->qaccept_cx = args.args[1];
1662                 qproc->qaccept_axi = args.args[2];
1663         }
1664
1665         if (qproc->has_ext_cntl_regs) {
1666                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1667                                                        "qcom,ext-regs",
1668                                                        2, 0, &args);
1669                 if (ret < 0) {
1670                         dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
1671                         return -EINVAL;
1672                 }
1673
1674                 qproc->conn_map = syscon_node_to_regmap(args.np);
1675                 of_node_put(args.np);
1676                 if (IS_ERR(qproc->conn_map))
1677                         return PTR_ERR(qproc->conn_map);
1678
1679                 qproc->force_clk_on = args.args[0];
1680                 qproc->rscc_disable = args.args[1];
1681
1682                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1683                                                        "qcom,ext-regs",
1684                                                        2, 1, &args);
1685                 if (ret < 0) {
1686                         dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
1687                         return -EINVAL;
1688                 }
1689
1690                 qproc->axim1_clk_off = args.args[0];
1691                 qproc->crypto_clk_off = args.args[1];
1692         }
1693
1694         if (qproc->has_spare_reg) {
1695                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1696                                                        "qcom,spare-regs",
1697                                                        1, 0, &args);
1698                 if (ret < 0) {
1699                         dev_err(&pdev->dev, "failed to parse spare-regs\n");
1700                         return -EINVAL;
1701                 }
1702
1703                 qproc->conn_map = syscon_node_to_regmap(args.np);
1704                 of_node_put(args.np);
1705                 if (IS_ERR(qproc->conn_map))
1706                         return PTR_ERR(qproc->conn_map);
1707
1708                 qproc->conn_box = args.args[0];
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1715                 char **clk_names)
1716 {
1717         int i;
1718
1719         if (!clk_names)
1720                 return 0;
1721
1722         for (i = 0; clk_names[i]; i++) {
1723                 clks[i] = devm_clk_get(dev, clk_names[i]);
1724                 if (IS_ERR(clks[i])) {
1725                         int rc = PTR_ERR(clks[i]);
1726
1727                         if (rc != -EPROBE_DEFER)
1728                                 dev_err(dev, "Failed to get %s clock\n",
1729                                         clk_names[i]);
1730                         return rc;
1731                 }
1732         }
1733
1734         return i;
1735 }
1736
1737 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1738                            char **pd_names)
1739 {
1740         size_t num_pds = 0;
1741         int ret;
1742         int i;
1743
1744         if (!pd_names)
1745                 return 0;
1746
1747         while (pd_names[num_pds])
1748                 num_pds++;
1749
1750         for (i = 0; i < num_pds; i++) {
1751                 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1752                 if (IS_ERR_OR_NULL(devs[i])) {
1753                         ret = PTR_ERR(devs[i]) ? : -ENODATA;
1754                         goto unroll_attach;
1755                 }
1756         }
1757
1758         return num_pds;
1759
1760 unroll_attach:
1761         for (i--; i >= 0; i--)
1762                 dev_pm_domain_detach(devs[i], false);
1763
1764         return ret;
1765 }
1766
1767 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1768                             size_t pd_count)
1769 {
1770         int i;
1771
1772         for (i = 0; i < pd_count; i++)
1773                 dev_pm_domain_detach(pds[i], false);
1774 }
1775
1776 static int q6v5_init_reset(struct q6v5 *qproc)
1777 {
1778         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1779                                                               "mss_restart");
1780         if (IS_ERR(qproc->mss_restart)) {
1781                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1782                 return PTR_ERR(qproc->mss_restart);
1783         }
1784
1785         if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
1786                 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1787                                                                     "pdc_reset");
1788                 if (IS_ERR(qproc->pdc_reset)) {
1789                         dev_err(qproc->dev, "failed to acquire pdc reset\n");
1790                         return PTR_ERR(qproc->pdc_reset);
1791                 }
1792         }
1793
1794         return 0;
1795 }
1796
1797 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1798 {
1799         struct device_node *child;
1800         struct device_node *node;
1801         struct resource r;
1802         int ret;
1803
1804         /*
1805          * In the absence of mba/mpss sub-child, extract the mba and mpss
1806          * reserved memory regions from device's memory-region property.
1807          */
1808         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1809         if (!child)
1810                 node = of_parse_phandle(qproc->dev->of_node,
1811                                         "memory-region", 0);
1812         else
1813                 node = of_parse_phandle(child, "memory-region", 0);
1814
1815         ret = of_address_to_resource(node, 0, &r);
1816         if (ret) {
1817                 dev_err(qproc->dev, "unable to resolve mba region\n");
1818                 return ret;
1819         }
1820         of_node_put(node);
1821
1822         qproc->mba_phys = r.start;
1823         qproc->mba_size = resource_size(&r);
1824
1825         if (!child) {
1826                 node = of_parse_phandle(qproc->dev->of_node,
1827                                         "memory-region", 1);
1828         } else {
1829                 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1830                 node = of_parse_phandle(child, "memory-region", 0);
1831         }
1832
1833         ret = of_address_to_resource(node, 0, &r);
1834         if (ret) {
1835                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1836                 return ret;
1837         }
1838         of_node_put(node);
1839
1840         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1841         qproc->mpss_size = resource_size(&r);
1842
1843         return 0;
1844 }
1845
1846 static int q6v5_probe(struct platform_device *pdev)
1847 {
1848         const struct rproc_hexagon_res *desc;
1849         struct q6v5 *qproc;
1850         struct rproc *rproc;
1851         const char *mba_image;
1852         int ret;
1853
1854         desc = of_device_get_match_data(&pdev->dev);
1855         if (!desc)
1856                 return -EINVAL;
1857
1858         if (desc->need_mem_protection && !qcom_scm_is_available())
1859                 return -EPROBE_DEFER;
1860
1861         mba_image = desc->hexagon_mba_image;
1862         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1863                                             0, &mba_image);
1864         if (ret < 0 && ret != -EINVAL) {
1865                 dev_err(&pdev->dev, "unable to read mba firmware-name\n");
1866                 return ret;
1867         }
1868
1869         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1870                             mba_image, sizeof(*qproc));
1871         if (!rproc) {
1872                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1873                 return -ENOMEM;
1874         }
1875
1876         rproc->auto_boot = false;
1877         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1878
1879         qproc = (struct q6v5 *)rproc->priv;
1880         qproc->dev = &pdev->dev;
1881         qproc->rproc = rproc;
1882         qproc->hexagon_mdt_image = "modem.mdt";
1883         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1884                                             1, &qproc->hexagon_mdt_image);
1885         if (ret < 0 && ret != -EINVAL) {
1886                 dev_err(&pdev->dev, "unable to read mpss firmware-name\n");
1887                 goto free_rproc;
1888         }
1889
1890         platform_set_drvdata(pdev, qproc);
1891
1892         qproc->has_qaccept_regs = desc->has_qaccept_regs;
1893         qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
1894         qproc->has_vq6 = desc->has_vq6;
1895         qproc->has_spare_reg = desc->has_spare_reg;
1896         ret = q6v5_init_mem(qproc, pdev);
1897         if (ret)
1898                 goto free_rproc;
1899
1900         ret = q6v5_alloc_memory_region(qproc);
1901         if (ret)
1902                 goto free_rproc;
1903
1904         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1905                                desc->proxy_clk_names);
1906         if (ret < 0) {
1907                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1908                 goto free_rproc;
1909         }
1910         qproc->proxy_clk_count = ret;
1911
1912         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1913                                desc->reset_clk_names);
1914         if (ret < 0) {
1915                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1916                 goto free_rproc;
1917         }
1918         qproc->reset_clk_count = ret;
1919
1920         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1921                                desc->active_clk_names);
1922         if (ret < 0) {
1923                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1924                 goto free_rproc;
1925         }
1926         qproc->active_clk_count = ret;
1927
1928         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1929                                   desc->proxy_supply);
1930         if (ret < 0) {
1931                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1932                 goto free_rproc;
1933         }
1934         qproc->proxy_reg_count = ret;
1935
1936         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
1937                                   desc->active_supply);
1938         if (ret < 0) {
1939                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1940                 goto free_rproc;
1941         }
1942         qproc->active_reg_count = ret;
1943
1944         ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1945                               desc->proxy_pd_names);
1946         /* Fallback to regulators for old device trees */
1947         if (ret == -ENODATA && desc->fallback_proxy_supply) {
1948                 ret = q6v5_regulator_init(&pdev->dev,
1949                                           qproc->fallback_proxy_regs,
1950                                           desc->fallback_proxy_supply);
1951                 if (ret < 0) {
1952                         dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
1953                         goto free_rproc;
1954                 }
1955                 qproc->fallback_proxy_reg_count = ret;
1956         } else if (ret < 0) {
1957                 dev_err(&pdev->dev, "Failed to init power domains\n");
1958                 goto free_rproc;
1959         } else {
1960                 qproc->proxy_pd_count = ret;
1961         }
1962
1963         qproc->has_alt_reset = desc->has_alt_reset;
1964         ret = q6v5_init_reset(qproc);
1965         if (ret)
1966                 goto detach_proxy_pds;
1967
1968         qproc->version = desc->version;
1969         qproc->need_mem_protection = desc->need_mem_protection;
1970         qproc->has_mba_logs = desc->has_mba_logs;
1971
1972         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
1973                              qcom_msa_handover);
1974         if (ret)
1975                 goto detach_proxy_pds;
1976
1977         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1978         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1979         qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1980         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1981         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1982         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1983         if (IS_ERR(qproc->sysmon)) {
1984                 ret = PTR_ERR(qproc->sysmon);
1985                 goto remove_subdevs;
1986         }
1987
1988         ret = rproc_add(rproc);
1989         if (ret)
1990                 goto remove_sysmon_subdev;
1991
1992         return 0;
1993
1994 remove_sysmon_subdev:
1995         qcom_remove_sysmon_subdev(qproc->sysmon);
1996 remove_subdevs:
1997         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1998         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1999         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2000 detach_proxy_pds:
2001         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2002 free_rproc:
2003         rproc_free(rproc);
2004
2005         return ret;
2006 }
2007
2008 static int q6v5_remove(struct platform_device *pdev)
2009 {
2010         struct q6v5 *qproc = platform_get_drvdata(pdev);
2011         struct rproc *rproc = qproc->rproc;
2012
2013         rproc_del(rproc);
2014
2015         qcom_q6v5_deinit(&qproc->q6v5);
2016         qcom_remove_sysmon_subdev(qproc->sysmon);
2017         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2018         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2019         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2020
2021         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2022
2023         rproc_free(rproc);
2024
2025         return 0;
2026 }
2027
2028 static const struct rproc_hexagon_res sc7180_mss = {
2029         .hexagon_mba_image = "mba.mbn",
2030         .proxy_clk_names = (char*[]){
2031                 "xo",
2032                 NULL
2033         },
2034         .reset_clk_names = (char*[]){
2035                 "iface",
2036                 "bus",
2037                 "snoc_axi",
2038                 NULL
2039         },
2040         .active_clk_names = (char*[]){
2041                 "mnoc_axi",
2042                 "nav",
2043                 NULL
2044         },
2045         .proxy_pd_names = (char*[]){
2046                 "cx",
2047                 "mx",
2048                 "mss",
2049                 NULL
2050         },
2051         .need_mem_protection = true,
2052         .has_alt_reset = false,
2053         .has_mba_logs = true,
2054         .has_spare_reg = true,
2055         .has_qaccept_regs = false,
2056         .has_ext_cntl_regs = false,
2057         .has_vq6 = false,
2058         .version = MSS_SC7180,
2059 };
2060
2061 static const struct rproc_hexagon_res sc7280_mss = {
2062         .hexagon_mba_image = "mba.mbn",
2063         .proxy_clk_names = (char*[]){
2064                 "xo",
2065                 "pka",
2066                 NULL
2067         },
2068         .active_clk_names = (char*[]){
2069                 "iface",
2070                 "offline",
2071                 "snoc_axi",
2072                 NULL
2073         },
2074         .proxy_pd_names = (char*[]){
2075                 "cx",
2076                 "mss",
2077                 NULL
2078         },
2079         .need_mem_protection = true,
2080         .has_alt_reset = false,
2081         .has_mba_logs = true,
2082         .has_spare_reg = false,
2083         .has_qaccept_regs = true,
2084         .has_ext_cntl_regs = true,
2085         .has_vq6 = true,
2086         .version = MSS_SC7280,
2087 };
2088
2089 static const struct rproc_hexagon_res sdm845_mss = {
2090         .hexagon_mba_image = "mba.mbn",
2091         .proxy_clk_names = (char*[]){
2092                         "xo",
2093                         "prng",
2094                         NULL
2095         },
2096         .reset_clk_names = (char*[]){
2097                         "iface",
2098                         "snoc_axi",
2099                         NULL
2100         },
2101         .active_clk_names = (char*[]){
2102                         "bus",
2103                         "mem",
2104                         "gpll0_mss",
2105                         "mnoc_axi",
2106                         NULL
2107         },
2108         .proxy_pd_names = (char*[]){
2109                         "cx",
2110                         "mx",
2111                         "mss",
2112                         NULL
2113         },
2114         .need_mem_protection = true,
2115         .has_alt_reset = true,
2116         .has_mba_logs = false,
2117         .has_spare_reg = false,
2118         .has_qaccept_regs = false,
2119         .has_ext_cntl_regs = false,
2120         .has_vq6 = false,
2121         .version = MSS_SDM845,
2122 };
2123
2124 static const struct rproc_hexagon_res msm8998_mss = {
2125         .hexagon_mba_image = "mba.mbn",
2126         .proxy_clk_names = (char*[]){
2127                         "xo",
2128                         "qdss",
2129                         "mem",
2130                         NULL
2131         },
2132         .active_clk_names = (char*[]){
2133                         "iface",
2134                         "bus",
2135                         "gpll0_mss",
2136                         "mnoc_axi",
2137                         "snoc_axi",
2138                         NULL
2139         },
2140         .proxy_pd_names = (char*[]){
2141                         "cx",
2142                         "mx",
2143                         NULL
2144         },
2145         .need_mem_protection = true,
2146         .has_alt_reset = false,
2147         .has_mba_logs = false,
2148         .has_spare_reg = false,
2149         .has_qaccept_regs = false,
2150         .has_ext_cntl_regs = false,
2151         .has_vq6 = false,
2152         .version = MSS_MSM8998,
2153 };
2154
2155 static const struct rproc_hexagon_res msm8996_mss = {
2156         .hexagon_mba_image = "mba.mbn",
2157         .proxy_supply = (struct qcom_mss_reg_res[]) {
2158                 {
2159                         .supply = "pll",
2160                         .uA = 100000,
2161                 },
2162                 {}
2163         },
2164         .proxy_clk_names = (char*[]){
2165                         "xo",
2166                         "pnoc",
2167                         "qdss",
2168                         NULL
2169         },
2170         .active_clk_names = (char*[]){
2171                         "iface",
2172                         "bus",
2173                         "mem",
2174                         "gpll0_mss",
2175                         "snoc_axi",
2176                         "mnoc_axi",
2177                         NULL
2178         },
2179         .need_mem_protection = true,
2180         .has_alt_reset = false,
2181         .has_mba_logs = false,
2182         .has_spare_reg = false,
2183         .has_qaccept_regs = false,
2184         .has_ext_cntl_regs = false,
2185         .has_vq6 = false,
2186         .version = MSS_MSM8996,
2187 };
2188
2189 static const struct rproc_hexagon_res msm8916_mss = {
2190         .hexagon_mba_image = "mba.mbn",
2191         .proxy_supply = (struct qcom_mss_reg_res[]) {
2192                 {
2193                         .supply = "pll",
2194                         .uA = 100000,
2195                 },
2196                 {}
2197         },
2198         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2199                 {
2200                         .supply = "mx",
2201                         .uV = 1050000,
2202                 },
2203                 {
2204                         .supply = "cx",
2205                         .uA = 100000,
2206                 },
2207                 {}
2208         },
2209         .proxy_clk_names = (char*[]){
2210                 "xo",
2211                 NULL
2212         },
2213         .active_clk_names = (char*[]){
2214                 "iface",
2215                 "bus",
2216                 "mem",
2217                 NULL
2218         },
2219         .proxy_pd_names = (char*[]){
2220                 "mx",
2221                 "cx",
2222                 NULL
2223         },
2224         .need_mem_protection = false,
2225         .has_alt_reset = false,
2226         .has_mba_logs = false,
2227         .has_spare_reg = false,
2228         .has_qaccept_regs = false,
2229         .has_ext_cntl_regs = false,
2230         .has_vq6 = false,
2231         .version = MSS_MSM8916,
2232 };
2233
2234 static const struct rproc_hexagon_res msm8974_mss = {
2235         .hexagon_mba_image = "mba.b00",
2236         .proxy_supply = (struct qcom_mss_reg_res[]) {
2237                 {
2238                         .supply = "pll",
2239                         .uA = 100000,
2240                 },
2241                 {}
2242         },
2243         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2244                 {
2245                         .supply = "mx",
2246                         .uV = 1050000,
2247                 },
2248                 {
2249                         .supply = "cx",
2250                         .uA = 100000,
2251                 },
2252                 {}
2253         },
2254         .active_supply = (struct qcom_mss_reg_res[]) {
2255                 {
2256                         .supply = "mss",
2257                         .uV = 1050000,
2258                         .uA = 100000,
2259                 },
2260                 {}
2261         },
2262         .proxy_clk_names = (char*[]){
2263                 "xo",
2264                 NULL
2265         },
2266         .active_clk_names = (char*[]){
2267                 "iface",
2268                 "bus",
2269                 "mem",
2270                 NULL
2271         },
2272         .proxy_pd_names = (char*[]){
2273                 "mx",
2274                 "cx",
2275                 NULL
2276         },
2277         .need_mem_protection = false,
2278         .has_alt_reset = false,
2279         .has_mba_logs = false,
2280         .has_spare_reg = false,
2281         .has_qaccept_regs = false,
2282         .has_ext_cntl_regs = false,
2283         .has_vq6 = false,
2284         .version = MSS_MSM8974,
2285 };
2286
2287 static const struct of_device_id q6v5_of_match[] = {
2288         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2289         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2290         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2291         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2292         { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2293         { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2294         { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2295         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2296         { },
2297 };
2298 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2299
2300 static struct platform_driver q6v5_driver = {
2301         .probe = q6v5_probe,
2302         .remove = q6v5_remove,
2303         .driver = {
2304                 .name = "qcom-q6v5-mss",
2305                 .of_match_table = q6v5_of_match,
2306         },
2307 };
2308 module_platform_driver(q6v5_driver);
2309
2310 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2311 MODULE_LICENSE("GPL v2");