1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
5 * Copyright (C) 2016 Linaro Ltd.
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/remoteproc.h>
25 #include "linux/remoteproc/qcom_q6v5_ipa_notify.h"
26 #include <linux/reset.h>
27 #include <linux/soc/qcom/mdt_loader.h>
28 #include <linux/iopoll.h>
30 #include "remoteproc_internal.h"
31 #include "qcom_common.h"
32 #include "qcom_q6v5.h"
34 #include <linux/qcom_scm.h>
36 #define MPSS_CRASH_REASON_SMEM 421
38 /* RMB Status Register Values */
39 #define RMB_PBL_SUCCESS 0x1
41 #define RMB_MBA_XPU_UNLOCKED 0x1
42 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
43 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
44 #define RMB_MBA_AUTH_COMPLETE 0x4
46 /* PBL/MBA interface registers */
47 #define RMB_MBA_IMAGE_REG 0x00
48 #define RMB_PBL_STATUS_REG 0x04
49 #define RMB_MBA_COMMAND_REG 0x08
50 #define RMB_MBA_STATUS_REG 0x0C
51 #define RMB_PMI_META_DATA_REG 0x10
52 #define RMB_PMI_CODE_START_REG 0x14
53 #define RMB_PMI_CODE_LENGTH_REG 0x18
54 #define RMB_MBA_MSS_STATUS 0x40
55 #define RMB_MBA_ALT_RESET 0x44
57 #define RMB_CMD_META_DATA_READY 0x1
58 #define RMB_CMD_LOAD_READY 0x2
60 /* QDSP6SS Register Offsets */
61 #define QDSP6SS_RESET_REG 0x014
62 #define QDSP6SS_GFMUX_CTL_REG 0x020
63 #define QDSP6SS_PWR_CTL_REG 0x030
64 #define QDSP6SS_MEM_PWR_CTL 0x0B0
65 #define QDSP6V6SS_MEM_PWR_CTL 0x034
66 #define QDSP6SS_STRAP_ACC 0x110
68 /* AXI Halt Register Offsets */
69 #define AXI_HALTREQ_REG 0x0
70 #define AXI_HALTACK_REG 0x4
71 #define AXI_IDLE_REG 0x8
72 #define AXI_GATING_VALID_OVERRIDE BIT(0)
74 #define HALT_ACK_TIMEOUT_US 100000
77 #define Q6SS_STOP_CORE BIT(0)
78 #define Q6SS_CORE_ARES BIT(1)
79 #define Q6SS_BUS_ARES_ENABLE BIT(2)
82 #define Q6SS_CBCR_CLKEN BIT(0)
83 #define Q6SS_CBCR_CLKOFF BIT(31)
84 #define Q6SS_CBCR_TIMEOUT_US 200
86 /* QDSP6SS_GFMUX_CTL */
87 #define Q6SS_CLK_ENABLE BIT(1)
90 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
91 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
92 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
93 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
94 #define Q6SS_ETB_SLP_NRET_N BIT(17)
95 #define Q6SS_L2DATA_STBY_N BIT(18)
96 #define Q6SS_SLP_RET_N BIT(19)
97 #define Q6SS_CLAMP_IO BIT(20)
98 #define QDSS_BHS_ON BIT(21)
99 #define QDSS_LDO_BYP BIT(22)
101 /* QDSP6v56 parameters */
102 #define QDSP6v56_LDO_BYP BIT(25)
103 #define QDSP6v56_BHS_ON BIT(24)
104 #define QDSP6v56_CLAMP_WL BIT(21)
105 #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
106 #define QDSP6SS_XO_CBCR 0x0038
107 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
109 /* QDSP6v65 parameters */
110 #define QDSP6SS_CORE_CBCR 0x20
111 #define QDSP6SS_SLEEP 0x3C
112 #define QDSP6SS_BOOT_CORE_START 0x400
113 #define QDSP6SS_BOOT_CMD 0x404
114 #define QDSP6SS_BOOT_STATUS 0x408
115 #define BOOT_STATUS_TIMEOUT_US 200
116 #define BOOT_FSM_TIMEOUT 10000
119 struct regulator *reg;
124 struct qcom_mss_reg_res {
130 struct rproc_hexagon_res {
131 const char *hexagon_mba_image;
132 struct qcom_mss_reg_res *proxy_supply;
133 struct qcom_mss_reg_res *active_supply;
134 char **proxy_clk_names;
135 char **reset_clk_names;
136 char **active_clk_names;
137 char **active_pd_names;
138 char **proxy_pd_names;
140 bool need_mem_protection;
149 void __iomem *reg_base;
150 void __iomem *rmb_base;
152 struct regmap *halt_map;
153 struct regmap *conn_map;
160 struct reset_control *mss_restart;
161 struct reset_control *pdc_reset;
163 struct qcom_q6v5 q6v5;
165 struct clk *active_clks[8];
166 struct clk *reset_clks[4];
167 struct clk *proxy_clks[4];
168 struct device *active_pds[1];
169 struct device *proxy_pds[3];
170 int active_clk_count;
176 struct reg_info active_regs[1];
177 struct reg_info proxy_regs[3];
178 int active_reg_count;
183 bool dump_mba_loaded;
184 unsigned long dump_segment_mask;
185 unsigned long dump_complete_mask;
187 phys_addr_t mba_phys;
191 phys_addr_t mpss_phys;
192 phys_addr_t mpss_reloc;
195 struct qcom_rproc_glink glink_subdev;
196 struct qcom_rproc_subdev smd_subdev;
197 struct qcom_rproc_ssr ssr_subdev;
198 struct qcom_rproc_ipa_notify ipa_notify_subdev;
199 struct qcom_sysmon *sysmon;
200 bool need_mem_protection;
205 const char *hexagon_mdt_image;
218 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
219 const struct qcom_mss_reg_res *reg_res)
227 for (i = 0; reg_res[i].supply; i++) {
228 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
229 if (IS_ERR(regs[i].reg)) {
230 rc = PTR_ERR(regs[i].reg);
231 if (rc != -EPROBE_DEFER)
232 dev_err(dev, "Failed to get %s\n regulator",
237 regs[i].uV = reg_res[i].uV;
238 regs[i].uA = reg_res[i].uA;
244 static int q6v5_regulator_enable(struct q6v5 *qproc,
245 struct reg_info *regs, int count)
250 for (i = 0; i < count; i++) {
251 if (regs[i].uV > 0) {
252 ret = regulator_set_voltage(regs[i].reg,
253 regs[i].uV, INT_MAX);
256 "Failed to request voltage for %d.\n",
262 if (regs[i].uA > 0) {
263 ret = regulator_set_load(regs[i].reg,
267 "Failed to set regulator mode\n");
272 ret = regulator_enable(regs[i].reg);
274 dev_err(qproc->dev, "Regulator enable failed\n");
281 for (; i >= 0; i--) {
283 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
286 regulator_set_load(regs[i].reg, 0);
288 regulator_disable(regs[i].reg);
294 static void q6v5_regulator_disable(struct q6v5 *qproc,
295 struct reg_info *regs, int count)
299 for (i = 0; i < count; i++) {
301 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
304 regulator_set_load(regs[i].reg, 0);
306 regulator_disable(regs[i].reg);
310 static int q6v5_clk_enable(struct device *dev,
311 struct clk **clks, int count)
316 for (i = 0; i < count; i++) {
317 rc = clk_prepare_enable(clks[i]);
319 dev_err(dev, "Clock enable failed\n");
326 for (i--; i >= 0; i--)
327 clk_disable_unprepare(clks[i]);
332 static void q6v5_clk_disable(struct device *dev,
333 struct clk **clks, int count)
337 for (i = 0; i < count; i++)
338 clk_disable_unprepare(clks[i]);
341 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
347 for (i = 0; i < pd_count; i++) {
348 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
349 ret = pm_runtime_get_sync(pds[i]);
351 goto unroll_pd_votes;
357 for (i--; i >= 0; i--) {
358 dev_pm_genpd_set_performance_state(pds[i], 0);
359 pm_runtime_put(pds[i]);
365 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
370 for (i = 0; i < pd_count; i++) {
371 dev_pm_genpd_set_performance_state(pds[i], 0);
372 pm_runtime_put(pds[i]);
376 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
377 bool local, bool remote, phys_addr_t addr,
380 struct qcom_scm_vmperm next[2];
383 if (!qproc->need_mem_protection)
386 if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
387 remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
391 next[perms].vmid = QCOM_SCM_VMID_HLOS;
392 next[perms].perm = QCOM_SCM_PERM_RWX;
397 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
398 next[perms].perm = QCOM_SCM_PERM_RW;
402 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
403 current_perm, next, perms);
406 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
408 struct q6v5 *qproc = rproc->priv;
410 memcpy(qproc->mba_region, fw->data, fw->size);
415 static int q6v5_reset_assert(struct q6v5 *qproc)
419 if (qproc->has_alt_reset) {
420 reset_control_assert(qproc->pdc_reset);
421 ret = reset_control_reset(qproc->mss_restart);
422 reset_control_deassert(qproc->pdc_reset);
423 } else if (qproc->has_spare_reg) {
425 * When the AXI pipeline is being reset with the Q6 modem partly
426 * operational there is possibility of AXI valid signal to
427 * glitch, leading to spurious transactions and Q6 hangs. A work
428 * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
429 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
430 * is withdrawn post MSS assert followed by a MSS deassert,
431 * while holding the PDC reset.
433 reset_control_assert(qproc->pdc_reset);
434 regmap_update_bits(qproc->conn_map, qproc->conn_box,
435 AXI_GATING_VALID_OVERRIDE, 1);
436 reset_control_assert(qproc->mss_restart);
437 reset_control_deassert(qproc->pdc_reset);
438 regmap_update_bits(qproc->conn_map, qproc->conn_box,
439 AXI_GATING_VALID_OVERRIDE, 0);
440 ret = reset_control_deassert(qproc->mss_restart);
442 ret = reset_control_assert(qproc->mss_restart);
448 static int q6v5_reset_deassert(struct q6v5 *qproc)
452 if (qproc->has_alt_reset) {
453 reset_control_assert(qproc->pdc_reset);
454 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
455 ret = reset_control_reset(qproc->mss_restart);
456 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
457 reset_control_deassert(qproc->pdc_reset);
458 } else if (qproc->has_spare_reg) {
459 ret = reset_control_reset(qproc->mss_restart);
461 ret = reset_control_deassert(qproc->mss_restart);
467 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
469 unsigned long timeout;
472 timeout = jiffies + msecs_to_jiffies(ms);
474 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
478 if (time_after(jiffies, timeout))
487 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
490 unsigned long timeout;
493 timeout = jiffies + msecs_to_jiffies(ms);
495 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
501 else if (status && val == status)
504 if (time_after(jiffies, timeout))
513 static int q6v5proc_reset(struct q6v5 *qproc)
519 if (qproc->version == MSS_SDM845) {
520 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
521 val |= Q6SS_CBCR_CLKEN;
522 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
524 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
525 val, !(val & Q6SS_CBCR_CLKOFF), 1,
526 Q6SS_CBCR_TIMEOUT_US);
528 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
532 /* De-assert QDSP6 stop core */
533 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
534 /* Trigger boot FSM */
535 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
537 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
538 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
540 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
541 /* Reset the modem so that boot FSM is in reset state */
542 q6v5_reset_deassert(qproc);
547 } else if (qproc->version == MSS_SC7180) {
548 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
549 val |= Q6SS_CBCR_CLKEN;
550 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
552 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
553 val, !(val & Q6SS_CBCR_CLKOFF), 1,
554 Q6SS_CBCR_TIMEOUT_US);
556 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
560 /* Turn on the XO clock needed for PLL setup */
561 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
562 val |= Q6SS_CBCR_CLKEN;
563 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
565 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
566 val, !(val & Q6SS_CBCR_CLKOFF), 1,
567 Q6SS_CBCR_TIMEOUT_US);
569 dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
573 /* Configure Q6 core CBCR to auto-enable after reset sequence */
574 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
575 val |= Q6SS_CBCR_CLKEN;
576 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
578 /* De-assert the Q6 stop core signal */
579 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
581 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
582 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
584 /* Poll the QDSP6SS_BOOT_STATUS for FSM completion */
585 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BOOT_STATUS,
586 val, (val & BIT(0)) != 0, 1,
587 BOOT_STATUS_TIMEOUT_US);
589 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
590 /* Reset the modem so that boot FSM is in reset state */
591 q6v5_reset_deassert(qproc);
595 } else if (qproc->version == MSS_MSM8996 ||
596 qproc->version == MSS_MSM8998) {
599 /* Override the ACC value if required */
600 writel(QDSP6SS_ACC_OVERRIDE_VAL,
601 qproc->reg_base + QDSP6SS_STRAP_ACC);
603 /* Assert resets, stop core */
604 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
605 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
606 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
608 /* BHS require xo cbcr to be enabled */
609 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
610 val |= Q6SS_CBCR_CLKEN;
611 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
613 /* Read CLKOFF bit to go low indicating CLK is enabled */
614 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
615 val, !(val & Q6SS_CBCR_CLKOFF), 1,
616 Q6SS_CBCR_TIMEOUT_US);
619 "xo cbcr enabling timed out (rc:%d)\n", ret);
622 /* Enable power block headswitch and wait for it to stabilize */
623 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
624 val |= QDSP6v56_BHS_ON;
625 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
626 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
629 /* Put LDO in bypass mode */
630 val |= QDSP6v56_LDO_BYP;
631 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
633 /* Deassert QDSP6 compiler memory clamp */
634 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
635 val &= ~QDSP6v56_CLAMP_QMC_MEM;
636 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
638 /* Deassert memory peripheral sleep and L2 memory standby */
639 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
640 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
642 /* Turn on L1, L2, ETB and JU memories 1 at a time */
643 if (qproc->version == MSS_MSM8996) {
644 mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
648 mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
651 val = readl(qproc->reg_base + mem_pwr_ctl);
652 for (; i >= 0; i--) {
654 writel(val, qproc->reg_base + mem_pwr_ctl);
656 * Read back value to ensure the write is done then
657 * wait for 1us for both memory peripheral and data
660 val |= readl(qproc->reg_base + mem_pwr_ctl);
663 /* Remove word line clamp */
664 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
665 val &= ~QDSP6v56_CLAMP_WL;
666 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
668 /* Assert resets, stop core */
669 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
670 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
671 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
673 /* Enable power block headswitch and wait for it to stabilize */
674 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
675 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
676 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
677 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
680 * Turn on memories. L2 banks should be done individually
681 * to minimize inrush current.
683 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
684 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
685 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
686 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
687 val |= Q6SS_L2DATA_SLP_NRET_N_2;
688 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
689 val |= Q6SS_L2DATA_SLP_NRET_N_1;
690 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
691 val |= Q6SS_L2DATA_SLP_NRET_N_0;
692 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
694 /* Remove IO clamp */
695 val &= ~Q6SS_CLAMP_IO;
696 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
698 /* Bring core out of reset */
699 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
700 val &= ~Q6SS_CORE_ARES;
701 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
703 /* Turn on core clock */
704 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
705 val |= Q6SS_CLK_ENABLE;
706 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
708 /* Start core execution */
709 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
710 val &= ~Q6SS_STOP_CORE;
711 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
714 /* Wait for PBL status */
715 ret = q6v5_rmb_pbl_wait(qproc, 1000);
716 if (ret == -ETIMEDOUT) {
717 dev_err(qproc->dev, "PBL boot timed out\n");
718 } else if (ret != RMB_PBL_SUCCESS) {
719 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
728 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
729 struct regmap *halt_map,
735 /* Check if we're already idle */
736 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
740 /* Assert halt request */
741 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
744 regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
745 val, 1000, HALT_ACK_TIMEOUT_US);
747 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
749 dev_err(qproc->dev, "port failed halt\n");
751 /* Clear halt request (port will remain halted until reset) */
752 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
755 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
757 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
766 metadata = qcom_mdt_read_metadata(fw, &size);
767 if (IS_ERR(metadata))
768 return PTR_ERR(metadata);
770 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
773 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
777 memcpy(ptr, metadata, size);
779 /* Hypervisor mapping to access metadata by modem */
780 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
781 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
785 "assigning Q6 access to metadata failed: %d\n", ret);
790 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
791 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
793 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
794 if (ret == -ETIMEDOUT)
795 dev_err(qproc->dev, "MPSS header authentication timed out\n");
797 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
799 /* Metadata authentication done, remove modem access */
800 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
804 "mdt buffer not reclaimed system may become unstable\n");
807 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
810 return ret < 0 ? ret : 0;
813 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
815 if (phdr->p_type != PT_LOAD)
818 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
827 static int q6v5_mba_load(struct q6v5 *qproc)
832 qcom_q6v5_prepare(&qproc->q6v5);
834 ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
836 dev_err(qproc->dev, "failed to enable active power domains\n");
840 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
842 dev_err(qproc->dev, "failed to enable proxy power domains\n");
843 goto disable_active_pds;
846 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
847 qproc->proxy_reg_count);
849 dev_err(qproc->dev, "failed to enable proxy supplies\n");
850 goto disable_proxy_pds;
853 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
854 qproc->proxy_clk_count);
856 dev_err(qproc->dev, "failed to enable proxy clocks\n");
857 goto disable_proxy_reg;
860 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
861 qproc->active_reg_count);
863 dev_err(qproc->dev, "failed to enable supplies\n");
864 goto disable_proxy_clk;
867 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
868 qproc->reset_clk_count);
870 dev_err(qproc->dev, "failed to enable reset clocks\n");
874 ret = q6v5_reset_deassert(qproc);
876 dev_err(qproc->dev, "failed to deassert mss restart\n");
877 goto disable_reset_clks;
880 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
881 qproc->active_clk_count);
883 dev_err(qproc->dev, "failed to enable clocks\n");
887 /* Assign MBA image access in DDR to q6 */
888 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
889 qproc->mba_phys, qproc->mba_size);
892 "assigning Q6 access to mba memory failed: %d\n", ret);
893 goto disable_active_clks;
896 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
898 ret = q6v5proc_reset(qproc);
902 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
903 if (ret == -ETIMEDOUT) {
904 dev_err(qproc->dev, "MBA boot timed out\n");
906 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
907 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
908 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
913 qproc->dump_mba_loaded = true;
917 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
918 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
919 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
922 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
923 false, qproc->mba_phys,
927 "Failed to reclaim mba buffer, system may become unstable\n");
931 q6v5_clk_disable(qproc->dev, qproc->active_clks,
932 qproc->active_clk_count);
934 q6v5_reset_assert(qproc);
936 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
937 qproc->reset_clk_count);
939 q6v5_regulator_disable(qproc, qproc->active_regs,
940 qproc->active_reg_count);
942 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
943 qproc->proxy_clk_count);
945 q6v5_regulator_disable(qproc, qproc->proxy_regs,
946 qproc->proxy_reg_count);
948 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
950 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
952 qcom_q6v5_unprepare(&qproc->q6v5);
957 static void q6v5_mba_reclaim(struct q6v5 *qproc)
962 qproc->dump_mba_loaded = false;
964 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
965 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
966 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
967 if (qproc->version == MSS_MSM8996) {
969 * To avoid high MX current during LPASS/MSS restart.
971 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
972 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
973 QDSP6v56_CLAMP_QMC_MEM;
974 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
977 q6v5_reset_assert(qproc);
979 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
980 qproc->reset_clk_count);
981 q6v5_clk_disable(qproc->dev, qproc->active_clks,
982 qproc->active_clk_count);
983 q6v5_regulator_disable(qproc, qproc->active_regs,
984 qproc->active_reg_count);
985 q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
987 /* In case of failure or coredump scenario where reclaiming MBA memory
988 * could not happen reclaim it here.
990 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
995 ret = qcom_q6v5_unprepare(&qproc->q6v5);
997 q6v5_pds_disable(qproc, qproc->proxy_pds,
998 qproc->proxy_pd_count);
999 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1000 qproc->proxy_clk_count);
1001 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1002 qproc->proxy_reg_count);
1006 static int q6v5_reload_mba(struct rproc *rproc)
1008 struct q6v5 *qproc = rproc->priv;
1009 const struct firmware *fw;
1012 ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1016 q6v5_load(rproc, fw);
1017 ret = q6v5_mba_load(qproc);
1018 release_firmware(fw);
1023 static int q6v5_mpss_load(struct q6v5 *qproc)
1025 const struct elf32_phdr *phdrs;
1026 const struct elf32_phdr *phdr;
1027 const struct firmware *seg_fw;
1028 const struct firmware *fw;
1029 struct elf32_hdr *ehdr;
1030 phys_addr_t mpss_reloc;
1031 phys_addr_t boot_addr;
1032 phys_addr_t min_addr = PHYS_ADDR_MAX;
1033 phys_addr_t max_addr = 0;
1035 bool relocate = false;
1044 fw_name_len = strlen(qproc->hexagon_mdt_image);
1045 if (fw_name_len <= 4)
1048 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1052 ret = request_firmware(&fw, fw_name, qproc->dev);
1054 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1058 /* Initialize the RMB validator */
1059 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1061 ret = q6v5_mpss_init_image(qproc, fw);
1063 goto release_firmware;
1065 ehdr = (struct elf32_hdr *)fw->data;
1066 phdrs = (struct elf32_phdr *)(ehdr + 1);
1068 for (i = 0; i < ehdr->e_phnum; i++) {
1071 if (!q6v5_phdr_valid(phdr))
1074 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1077 if (phdr->p_paddr < min_addr)
1078 min_addr = phdr->p_paddr;
1080 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1081 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1085 * In case of a modem subsystem restart on secure devices, the modem
1086 * memory can be reclaimed only after MBA is loaded. For modem cold
1087 * boot this will be a nop
1089 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1090 qproc->mpss_phys, qproc->mpss_size);
1092 /* Share ownership between Linux and MSS, during segment loading */
1093 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1094 qproc->mpss_phys, qproc->mpss_size);
1097 "assigning Q6 access to mpss memory failed: %d\n", ret);
1099 goto release_firmware;
1102 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1103 qproc->mpss_reloc = mpss_reloc;
1104 /* Load firmware segments */
1105 for (i = 0; i < ehdr->e_phnum; i++) {
1108 if (!q6v5_phdr_valid(phdr))
1111 offset = phdr->p_paddr - mpss_reloc;
1112 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1113 dev_err(qproc->dev, "segment outside memory range\n");
1115 goto release_firmware;
1118 ptr = ioremap_wc(qproc->mpss_phys + offset, phdr->p_memsz);
1121 "unable to map memory region: %pa+%zx-%x\n",
1122 &qproc->mpss_phys, offset, phdr->p_memsz);
1123 goto release_firmware;
1126 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1127 /* Firmware is large enough to be non-split */
1128 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1130 "failed to load segment %d from truncated file %s\n",
1134 goto release_firmware;
1137 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1138 } else if (phdr->p_filesz) {
1139 /* Replace "xxx.xxx" with "xxx.bxx" */
1140 sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1141 ret = request_firmware(&seg_fw, fw_name, qproc->dev);
1143 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1145 goto release_firmware;
1148 memcpy(ptr, seg_fw->data, seg_fw->size);
1150 release_firmware(seg_fw);
1153 if (phdr->p_memsz > phdr->p_filesz) {
1154 memset(ptr + phdr->p_filesz, 0,
1155 phdr->p_memsz - phdr->p_filesz);
1158 size += phdr->p_memsz;
1160 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1162 boot_addr = relocate ? qproc->mpss_phys : min_addr;
1163 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1164 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1166 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1168 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1170 dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1172 goto release_firmware;
1176 /* Transfer ownership of modem ddr region to q6 */
1177 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1178 qproc->mpss_phys, qproc->mpss_size);
1181 "assigning Q6 access to mpss memory failed: %d\n", ret);
1183 goto release_firmware;
1186 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1187 if (ret == -ETIMEDOUT)
1188 dev_err(qproc->dev, "MPSS authentication timed out\n");
1190 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1193 release_firmware(fw);
1197 return ret < 0 ? ret : 0;
1200 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1201 struct rproc_dump_segment *segment,
1205 struct q6v5 *qproc = rproc->priv;
1206 unsigned long mask = BIT((unsigned long)segment->priv);
1207 int offset = segment->da - qproc->mpss_reloc;
1210 /* Unlock mba before copying segments */
1211 if (!qproc->dump_mba_loaded) {
1212 ret = q6v5_reload_mba(rproc);
1214 /* Reset ownership back to Linux to copy segments */
1215 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1223 ptr = ioremap_wc(qproc->mpss_phys + offset, segment->size);
1226 memcpy(dest, ptr, segment->size);
1229 memset(dest, 0xff, segment->size);
1232 qproc->dump_segment_mask |= mask;
1234 /* Reclaim mba after copying segments */
1235 if (qproc->dump_segment_mask == qproc->dump_complete_mask) {
1236 if (qproc->dump_mba_loaded) {
1237 /* Try to reset ownership back to Q6 */
1238 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1242 q6v5_mba_reclaim(qproc);
1247 static int q6v5_start(struct rproc *rproc)
1249 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1253 ret = q6v5_mba_load(qproc);
1257 dev_info(qproc->dev, "MBA booted, loading mpss\n");
1259 ret = q6v5_mpss_load(qproc);
1263 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1264 if (ret == -ETIMEDOUT) {
1265 dev_err(qproc->dev, "start timed out\n");
1269 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1270 false, qproc->mba_phys,
1274 "Failed to reclaim mba buffer system may become unstable\n");
1276 /* Reset Dump Segment Mask */
1277 qproc->dump_segment_mask = 0;
1278 qproc->running = true;
1283 q6v5_mba_reclaim(qproc);
1288 static int q6v5_stop(struct rproc *rproc)
1290 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1293 qproc->running = false;
1295 ret = qcom_q6v5_request_stop(&qproc->q6v5);
1296 if (ret == -ETIMEDOUT)
1297 dev_err(qproc->dev, "timed out on wait\n");
1299 q6v5_mba_reclaim(qproc);
1304 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1305 const struct firmware *mba_fw)
1307 const struct firmware *fw;
1308 const struct elf32_phdr *phdrs;
1309 const struct elf32_phdr *phdr;
1310 const struct elf32_hdr *ehdr;
1311 struct q6v5 *qproc = rproc->priv;
1315 ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1317 dev_err(qproc->dev, "unable to load %s\n",
1318 qproc->hexagon_mdt_image);
1322 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1324 ehdr = (struct elf32_hdr *)fw->data;
1325 phdrs = (struct elf32_phdr *)(ehdr + 1);
1326 qproc->dump_complete_mask = 0;
1328 for (i = 0; i < ehdr->e_phnum; i++) {
1331 if (!q6v5_phdr_valid(phdr))
1334 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1336 qcom_q6v5_dump_segment,
1341 qproc->dump_complete_mask |= BIT(i);
1344 release_firmware(fw);
1348 static const struct rproc_ops q6v5_ops = {
1349 .start = q6v5_start,
1351 .parse_fw = qcom_q6v5_register_dump_segments,
1355 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1357 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1359 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1360 qproc->proxy_clk_count);
1361 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1362 qproc->proxy_reg_count);
1363 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1366 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1368 struct of_phandle_args args;
1369 struct resource *res;
1372 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1373 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1374 if (IS_ERR(qproc->reg_base))
1375 return PTR_ERR(qproc->reg_base);
1377 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1378 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1379 if (IS_ERR(qproc->rmb_base))
1380 return PTR_ERR(qproc->rmb_base);
1382 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1383 "qcom,halt-regs", 3, 0, &args);
1385 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1389 qproc->halt_map = syscon_node_to_regmap(args.np);
1390 of_node_put(args.np);
1391 if (IS_ERR(qproc->halt_map))
1392 return PTR_ERR(qproc->halt_map);
1394 qproc->halt_q6 = args.args[0];
1395 qproc->halt_modem = args.args[1];
1396 qproc->halt_nc = args.args[2];
1398 if (qproc->has_spare_reg) {
1399 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1403 dev_err(&pdev->dev, "failed to parse spare-regs\n");
1407 qproc->conn_map = syscon_node_to_regmap(args.np);
1408 of_node_put(args.np);
1409 if (IS_ERR(qproc->conn_map))
1410 return PTR_ERR(qproc->conn_map);
1412 qproc->conn_box = args.args[0];
1418 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1426 for (i = 0; clk_names[i]; i++) {
1427 clks[i] = devm_clk_get(dev, clk_names[i]);
1428 if (IS_ERR(clks[i])) {
1429 int rc = PTR_ERR(clks[i]);
1431 if (rc != -EPROBE_DEFER)
1432 dev_err(dev, "Failed to get %s clock\n",
1441 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1451 while (pd_names[num_pds])
1454 for (i = 0; i < num_pds; i++) {
1455 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1456 if (IS_ERR_OR_NULL(devs[i])) {
1457 ret = PTR_ERR(devs[i]) ? : -ENODATA;
1465 for (i--; i >= 0; i--)
1466 dev_pm_domain_detach(devs[i], false);
1471 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1476 for (i = 0; i < pd_count; i++)
1477 dev_pm_domain_detach(pds[i], false);
1480 static int q6v5_init_reset(struct q6v5 *qproc)
1482 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1484 if (IS_ERR(qproc->mss_restart)) {
1485 dev_err(qproc->dev, "failed to acquire mss restart\n");
1486 return PTR_ERR(qproc->mss_restart);
1489 if (qproc->has_alt_reset || qproc->has_spare_reg) {
1490 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1492 if (IS_ERR(qproc->pdc_reset)) {
1493 dev_err(qproc->dev, "failed to acquire pdc reset\n");
1494 return PTR_ERR(qproc->pdc_reset);
1501 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1503 struct device_node *child;
1504 struct device_node *node;
1509 * In the absence of mba/mpss sub-child, extract the mba and mpss
1510 * reserved memory regions from device's memory-region property.
1512 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1514 node = of_parse_phandle(qproc->dev->of_node,
1515 "memory-region", 0);
1517 node = of_parse_phandle(child, "memory-region", 0);
1519 ret = of_address_to_resource(node, 0, &r);
1521 dev_err(qproc->dev, "unable to resolve mba region\n");
1526 qproc->mba_phys = r.start;
1527 qproc->mba_size = resource_size(&r);
1528 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1529 if (!qproc->mba_region) {
1530 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1531 &r.start, qproc->mba_size);
1536 node = of_parse_phandle(qproc->dev->of_node,
1537 "memory-region", 1);
1539 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1540 node = of_parse_phandle(child, "memory-region", 0);
1543 ret = of_address_to_resource(node, 0, &r);
1545 dev_err(qproc->dev, "unable to resolve mpss region\n");
1550 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1551 qproc->mpss_size = resource_size(&r);
1556 #if IS_ENABLED(CONFIG_QCOM_Q6V5_IPA_NOTIFY)
1558 /* Register IPA notification function */
1559 int qcom_register_ipa_notify(struct rproc *rproc, qcom_ipa_notify_t notify,
1562 struct qcom_rproc_ipa_notify *ipa_notify;
1563 struct q6v5 *qproc = rproc->priv;
1568 ipa_notify = &qproc->ipa_notify_subdev;
1569 if (ipa_notify->notify)
1572 ipa_notify->notify = notify;
1573 ipa_notify->data = data;
1577 EXPORT_SYMBOL_GPL(qcom_register_ipa_notify);
1579 /* Deregister IPA notification function */
1580 void qcom_deregister_ipa_notify(struct rproc *rproc)
1582 struct q6v5 *qproc = rproc->priv;
1584 qproc->ipa_notify_subdev.notify = NULL;
1586 EXPORT_SYMBOL_GPL(qcom_deregister_ipa_notify);
1587 #endif /* !IS_ENABLED(CONFIG_QCOM_Q6V5_IPA_NOTIFY) */
1589 static int q6v5_probe(struct platform_device *pdev)
1591 const struct rproc_hexagon_res *desc;
1593 struct rproc *rproc;
1594 const char *mba_image;
1597 desc = of_device_get_match_data(&pdev->dev);
1601 if (desc->need_mem_protection && !qcom_scm_is_available())
1602 return -EPROBE_DEFER;
1604 mba_image = desc->hexagon_mba_image;
1605 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1607 if (ret < 0 && ret != -EINVAL)
1610 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1611 mba_image, sizeof(*qproc));
1613 dev_err(&pdev->dev, "failed to allocate rproc\n");
1617 rproc->auto_boot = false;
1618 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1620 qproc = (struct q6v5 *)rproc->priv;
1621 qproc->dev = &pdev->dev;
1622 qproc->rproc = rproc;
1623 qproc->hexagon_mdt_image = "modem.mdt";
1624 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1625 1, &qproc->hexagon_mdt_image);
1626 if (ret < 0 && ret != -EINVAL)
1629 platform_set_drvdata(pdev, qproc);
1631 qproc->has_spare_reg = desc->has_spare_reg;
1632 ret = q6v5_init_mem(qproc, pdev);
1636 ret = q6v5_alloc_memory_region(qproc);
1640 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1641 desc->proxy_clk_names);
1643 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1646 qproc->proxy_clk_count = ret;
1648 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1649 desc->reset_clk_names);
1651 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1654 qproc->reset_clk_count = ret;
1656 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1657 desc->active_clk_names);
1659 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1662 qproc->active_clk_count = ret;
1664 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1665 desc->proxy_supply);
1667 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1670 qproc->proxy_reg_count = ret;
1672 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1673 desc->active_supply);
1675 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1678 qproc->active_reg_count = ret;
1680 ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1681 desc->active_pd_names);
1683 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1686 qproc->active_pd_count = ret;
1688 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1689 desc->proxy_pd_names);
1691 dev_err(&pdev->dev, "Failed to init power domains\n");
1692 goto detach_active_pds;
1694 qproc->proxy_pd_count = ret;
1696 qproc->has_alt_reset = desc->has_alt_reset;
1697 ret = q6v5_init_reset(qproc);
1699 goto detach_proxy_pds;
1701 qproc->version = desc->version;
1702 qproc->need_mem_protection = desc->need_mem_protection;
1704 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1707 goto detach_proxy_pds;
1709 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1710 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1711 qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1712 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1713 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1714 qcom_add_ipa_notify_subdev(rproc, &qproc->ipa_notify_subdev);
1715 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1716 if (IS_ERR(qproc->sysmon)) {
1717 ret = PTR_ERR(qproc->sysmon);
1718 goto remove_subdevs;
1721 ret = rproc_add(rproc);
1723 goto remove_sysmon_subdev;
1727 remove_sysmon_subdev:
1728 qcom_remove_sysmon_subdev(qproc->sysmon);
1730 qcom_remove_ipa_notify_subdev(qproc->rproc, &qproc->ipa_notify_subdev);
1731 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1732 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1733 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1735 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1737 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1744 static int q6v5_remove(struct platform_device *pdev)
1746 struct q6v5 *qproc = platform_get_drvdata(pdev);
1747 struct rproc *rproc = qproc->rproc;
1751 qcom_remove_sysmon_subdev(qproc->sysmon);
1752 qcom_remove_ipa_notify_subdev(rproc, &qproc->ipa_notify_subdev);
1753 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1754 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1755 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1757 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1758 q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1765 static const struct rproc_hexagon_res sc7180_mss = {
1766 .hexagon_mba_image = "mba.mbn",
1767 .proxy_clk_names = (char*[]){
1771 .reset_clk_names = (char*[]){
1777 .active_clk_names = (char*[]){
1782 .active_pd_names = (char*[]){
1786 .proxy_pd_names = (char*[]){
1792 .need_mem_protection = true,
1793 .has_alt_reset = false,
1794 .has_spare_reg = true,
1795 .version = MSS_SC7180,
1798 static const struct rproc_hexagon_res sdm845_mss = {
1799 .hexagon_mba_image = "mba.mbn",
1800 .proxy_clk_names = (char*[]){
1805 .reset_clk_names = (char*[]){
1810 .active_clk_names = (char*[]){
1817 .active_pd_names = (char*[]){
1821 .proxy_pd_names = (char*[]){
1827 .need_mem_protection = true,
1828 .has_alt_reset = true,
1829 .has_spare_reg = false,
1830 .version = MSS_SDM845,
1833 static const struct rproc_hexagon_res msm8998_mss = {
1834 .hexagon_mba_image = "mba.mbn",
1835 .proxy_clk_names = (char*[]){
1841 .active_clk_names = (char*[]){
1849 .proxy_pd_names = (char*[]){
1854 .need_mem_protection = true,
1855 .has_alt_reset = false,
1856 .has_spare_reg = false,
1857 .version = MSS_MSM8998,
1860 static const struct rproc_hexagon_res msm8996_mss = {
1861 .hexagon_mba_image = "mba.mbn",
1862 .proxy_supply = (struct qcom_mss_reg_res[]) {
1869 .proxy_clk_names = (char*[]){
1875 .active_clk_names = (char*[]){
1884 .need_mem_protection = true,
1885 .has_alt_reset = false,
1886 .has_spare_reg = false,
1887 .version = MSS_MSM8996,
1890 static const struct rproc_hexagon_res msm8916_mss = {
1891 .hexagon_mba_image = "mba.mbn",
1892 .proxy_supply = (struct qcom_mss_reg_res[]) {
1907 .proxy_clk_names = (char*[]){
1911 .active_clk_names = (char*[]){
1917 .need_mem_protection = false,
1918 .has_alt_reset = false,
1919 .has_spare_reg = false,
1920 .version = MSS_MSM8916,
1923 static const struct rproc_hexagon_res msm8974_mss = {
1924 .hexagon_mba_image = "mba.b00",
1925 .proxy_supply = (struct qcom_mss_reg_res[]) {
1940 .active_supply = (struct qcom_mss_reg_res[]) {
1948 .proxy_clk_names = (char*[]){
1952 .active_clk_names = (char*[]){
1958 .need_mem_protection = false,
1959 .has_alt_reset = false,
1960 .has_spare_reg = false,
1961 .version = MSS_MSM8974,
1964 static const struct of_device_id q6v5_of_match[] = {
1965 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1966 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1967 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1968 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
1969 { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
1970 { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
1971 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
1974 MODULE_DEVICE_TABLE(of, q6v5_of_match);
1976 static struct platform_driver q6v5_driver = {
1977 .probe = q6v5_probe,
1978 .remove = q6v5_remove,
1980 .name = "qcom-q6v5-mss",
1981 .of_match_table = q6v5_of_match,
1984 module_platform_driver(q6v5_driver);
1986 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
1987 MODULE_LICENSE("GPL v2");