drivers/remoteproc/qcom_q6v5_mss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm self-authenticating modem subsystem remoteproc driver
   4  *
   5  * Copyright (C) 2016 Linaro Ltd.
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/devcoredump.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/remoteproc.h>
  26 #include <linux/reset.h>
  27 #include <linux/soc/qcom/mdt_loader.h>
  28 #include <linux/iopoll.h>
  29 #include <linux/slab.h>
  30
  31 #include "remoteproc_internal.h"
  32 #include "qcom_common.h"
  33 #include "qcom_pil_info.h"
  34 #include "qcom_q6v5.h"
  35
  36 #include <linux/qcom_scm.h>
  37
  38 #define MPSS_CRASH_REASON_SMEM          421
  39
  40 #define MBA_LOG_SIZE                    SZ_4K
  41
  42 /* RMB Status Register Values */
  43 #define RMB_PBL_SUCCESS                 0x1
  44
  45 #define RMB_MBA_XPU_UNLOCKED            0x1
  46 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  47 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  48 #define RMB_MBA_AUTH_COMPLETE           0x4
  49
  50 /* PBL/MBA interface registers */
  51 #define RMB_MBA_IMAGE_REG               0x00
  52 #define RMB_PBL_STATUS_REG              0x04
  53 #define RMB_MBA_COMMAND_REG             0x08
  54 #define RMB_MBA_STATUS_REG              0x0C
  55 #define RMB_PMI_META_DATA_REG           0x10
  56 #define RMB_PMI_CODE_START_REG          0x14
  57 #define RMB_PMI_CODE_LENGTH_REG         0x18
  58 #define RMB_MBA_MSS_STATUS              0x40
  59 #define RMB_MBA_ALT_RESET               0x44
  60
  61 #define RMB_CMD_META_DATA_READY         0x1
  62 #define RMB_CMD_LOAD_READY              0x2
  63
  64 /* QDSP6SS Register Offsets */
  65 #define QDSP6SS_RESET_REG               0x014
  66 #define QDSP6SS_GFMUX_CTL_REG           0x020
  67 #define QDSP6SS_PWR_CTL_REG             0x030
  68 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  69 #define QDSP6V6SS_MEM_PWR_CTL           0x034
  70 #define QDSP6SS_STRAP_ACC               0x110
  71
  72 /* AXI Halt Register Offsets */
  73 #define AXI_HALTREQ_REG                 0x0
  74 #define AXI_HALTACK_REG                 0x4
  75 #define AXI_IDLE_REG                    0x8
  76 #define AXI_GATING_VALID_OVERRIDE       BIT(0)
  77
  78 #define HALT_ACK_TIMEOUT_US             100000
  79
  80 /* QDSP6SS_RESET */
  81 #define Q6SS_STOP_CORE                  BIT(0)
  82 #define Q6SS_CORE_ARES                  BIT(1)
  83 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  84
  85 /* QDSP6SS CBCR */
  86 #define Q6SS_CBCR_CLKEN                 BIT(0)
  87 #define Q6SS_CBCR_CLKOFF                BIT(31)
  88 #define Q6SS_CBCR_TIMEOUT_US            200
  89
  90 /* QDSP6SS_GFMUX_CTL */
  91 #define Q6SS_CLK_ENABLE                 BIT(1)
  92
  93 /* QDSP6SS_PWR_CTL */
  94 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
  95 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
  96 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
  97 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
  98 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
  99 #define Q6SS_L2DATA_STBY_N              BIT(18)
 100 #define Q6SS_SLP_RET_N                  BIT(19)
 101 #define Q6SS_CLAMP_IO                   BIT(20)
 102 #define QDSS_BHS_ON                     BIT(21)
 103 #define QDSS_LDO_BYP                    BIT(22)
 104
 105 /* QDSP6v56 parameters */
 106 #define QDSP6v56_LDO_BYP                BIT(25)
 107 #define QDSP6v56_BHS_ON         BIT(24)
 108 #define QDSP6v56_CLAMP_WL               BIT(21)
 109 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
 110 #define QDSP6SS_XO_CBCR         0x0038
 111 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 112
 113 /* QDSP6v65 parameters */
 114 #define QDSP6SS_CORE_CBCR               0x20
 115 #define QDSP6SS_SLEEP                   0x3C
 116 #define QDSP6SS_BOOT_CORE_START         0x400
 117 #define QDSP6SS_BOOT_CMD                0x404
 118 #define BOOT_FSM_TIMEOUT                10000
 119
 120 struct reg_info {
 121         struct regulator *reg;
 122         int uV;
 123         int uA;
 124 };
 125
 126 struct qcom_mss_reg_res {
 127         const char *supply;
 128         int uV;
 129         int uA;
 130 };
 131
 132 struct rproc_hexagon_res {
 133         const char *hexagon_mba_image;
 134         struct qcom_mss_reg_res *proxy_supply;
 135         struct qcom_mss_reg_res *fallback_proxy_supply;
 136         struct qcom_mss_reg_res *active_supply;
 137         char **proxy_clk_names;
 138         char **reset_clk_names;
 139         char **active_clk_names;
 140         char **active_pd_names;
 141         char **proxy_pd_names;
 142         int version;
 143         bool need_mem_protection;
 144         bool has_alt_reset;
 145         bool has_mba_logs;
 146         bool has_spare_reg;
 147 };
 148
 149 struct q6v5 {
 150         struct device *dev;
 151         struct rproc *rproc;
 152
 153         void __iomem *reg_base;
 154         void __iomem *rmb_base;
 155
 156         struct regmap *halt_map;
 157         struct regmap *conn_map;
 158
 159         u32 halt_q6;
 160         u32 halt_modem;
 161         u32 halt_nc;
 162         u32 conn_box;
 163
 164         struct reset_control *mss_restart;
 165         struct reset_control *pdc_reset;
 166
 167         struct qcom_q6v5 q6v5;
 168
 169         struct clk *active_clks[8];
 170         struct clk *reset_clks[4];
 171         struct clk *proxy_clks[4];
 172         struct device *active_pds[1];
 173         struct device *proxy_pds[3];
 174         int active_clk_count;
 175         int reset_clk_count;
 176         int proxy_clk_count;
 177         int active_pd_count;
 178         int proxy_pd_count;
 179
 180         struct reg_info active_regs[1];
 181         struct reg_info proxy_regs[1];
 182         struct reg_info fallback_proxy_regs[2];
 183         int active_reg_count;
 184         int proxy_reg_count;
 185         int fallback_proxy_reg_count;
 186
 187         bool dump_mba_loaded;
 188         size_t current_dump_size;
 189         size_t total_dump_size;
 190
 191         phys_addr_t mba_phys;
 192         size_t mba_size;
 193         size_t dp_size;
 194
 195         phys_addr_t mpss_phys;
 196         phys_addr_t mpss_reloc;
 197         size_t mpss_size;
 198
 199         struct qcom_rproc_glink glink_subdev;
 200         struct qcom_rproc_subdev smd_subdev;
 201         struct qcom_rproc_ssr ssr_subdev;
 202         struct qcom_sysmon *sysmon;
 203         bool need_mem_protection;
 204         bool has_alt_reset;
 205         bool has_mba_logs;
 206         bool has_spare_reg;
 207         int mpss_perm;
 208         int mba_perm;
 209         const char *hexagon_mdt_image;
 210         int version;
 211 };
 212
 213 enum {
 214         MSS_MSM8916,
 215         MSS_MSM8974,
 216         MSS_MSM8996,
 217         MSS_MSM8998,
 218         MSS_SC7180,
 219         MSS_SDM845,
 220 };
 221
 222 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 223                                const struct qcom_mss_reg_res *reg_res)
 224 {
 225         int rc;
 226         int i;
 227
 228         if (!reg_res)
 229                 return 0;
 230
 231         for (i = 0; reg_res[i].supply; i++) {
 232                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 233                 if (IS_ERR(regs[i].reg)) {
 234                         rc = PTR_ERR(regs[i].reg);
 235                         if (rc != -EPROBE_DEFER)
 236                                 dev_err(dev, "Failed to get %s\n regulator",
 237                                         reg_res[i].supply);
 238                         return rc;
 239                 }
 240
 241                 regs[i].uV = reg_res[i].uV;
 242                 regs[i].uA = reg_res[i].uA;
 243         }
 244
 245         return i;
 246 }
 247
 248 static int q6v5_regulator_enable(struct q6v5 *qproc,
 249                                  struct reg_info *regs, int count)
 250 {
 251         int ret;
 252         int i;
 253
 254         for (i = 0; i < count; i++) {
 255                 if (regs[i].uV > 0) {
 256                         ret = regulator_set_voltage(regs[i].reg,
 257                                         regs[i].uV, INT_MAX);
 258                         if (ret) {
 259                                 dev_err(qproc->dev,
 260                                         "Failed to request voltage for %d.\n",
 261                                                 i);
 262                                 goto err;
 263                         }
 264                 }
 265
 266                 if (regs[i].uA > 0) {
 267                         ret = regulator_set_load(regs[i].reg,
 268                                                  regs[i].uA);
 269                         if (ret < 0) {
 270                                 dev_err(qproc->dev,
 271                                         "Failed to set regulator mode\n");
 272                                 goto err;
 273                         }
 274                 }
 275
 276                 ret = regulator_enable(regs[i].reg);
 277                 if (ret) {
 278                         dev_err(qproc->dev, "Regulator enable failed\n");
 279                         goto err;
 280                 }
 281         }
 282
 283         return 0;
 284 err:
 285         for (; i >= 0; i--) {
 286                 if (regs[i].uV > 0)
 287                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 288
 289                 if (regs[i].uA > 0)
 290                         regulator_set_load(regs[i].reg, 0);
 291
 292                 regulator_disable(regs[i].reg);
 293         }
 294
 295         return ret;
 296 }
 297
 298 static void q6v5_regulator_disable(struct q6v5 *qproc,
 299                                    struct reg_info *regs, int count)
 300 {
 301         int i;
 302
 303         for (i = 0; i < count; i++) {
 304                 if (regs[i].uV > 0)
 305                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 306
 307                 if (regs[i].uA > 0)
 308                         regulator_set_load(regs[i].reg, 0);
 309
 310                 regulator_disable(regs[i].reg);
 311         }
 312 }
 313
 314 static int q6v5_clk_enable(struct device *dev,
 315                            struct clk **clks, int count)
 316 {
 317         int rc;
 318         int i;
 319
 320         for (i = 0; i < count; i++) {
 321                 rc = clk_prepare_enable(clks[i]);
 322                 if (rc) {
 323                         dev_err(dev, "Clock enable failed\n");
 324                         goto err;
 325                 }
 326         }
 327
 328         return 0;
 329 err:
 330         for (i--; i >= 0; i--)
 331                 clk_disable_unprepare(clks[i]);
 332
 333         return rc;
 334 }
 335
 336 static void q6v5_clk_disable(struct device *dev,
 337                              struct clk **clks, int count)
 338 {
 339         int i;
 340
 341         for (i = 0; i < count; i++)
 342                 clk_disable_unprepare(clks[i]);
 343 }
 344
 345 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 346                            size_t pd_count)
 347 {
 348         int ret;
 349         int i;
 350
 351         for (i = 0; i < pd_count; i++) {
 352                 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 353                 ret = pm_runtime_get_sync(pds[i]);
 354                 if (ret < 0)
 355                         goto unroll_pd_votes;
 356         }
 357
 358         return 0;
 359
 360 unroll_pd_votes:
 361         for (i--; i >= 0; i--) {
 362                 dev_pm_genpd_set_performance_state(pds[i], 0);
 363                 pm_runtime_put(pds[i]);
 364         }
 365
 366         return ret;
 367 }
 368
 369 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 370                              size_t pd_count)
 371 {
 372         int i;
 373
 374         for (i = 0; i < pd_count; i++) {
 375                 dev_pm_genpd_set_performance_state(pds[i], 0);
 376                 pm_runtime_put(pds[i]);
 377         }
 378 }
 379
 380 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 381                                    bool local, bool remote, phys_addr_t addr,
 382                                    size_t size)
 383 {
 384         struct qcom_scm_vmperm next[2];
 385         int perms = 0;
 386
 387         if (!qproc->need_mem_protection)
 388                 return 0;
 389
 390         if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
 391             remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
 392                 return 0;
 393
 394         if (local) {
 395                 next[perms].vmid = QCOM_SCM_VMID_HLOS;
 396                 next[perms].perm = QCOM_SCM_PERM_RWX;
 397                 perms++;
 398         }
 399
 400         if (remote) {
 401                 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
 402                 next[perms].perm = QCOM_SCM_PERM_RW;
 403                 perms++;
 404         }
 405
 406         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 407                                    current_perm, next, perms);
 408 }
 409
 410 static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region)
 411 {
 412         const struct firmware *dp_fw;
 413
 414         if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
 415                 return;
 416
 417         if (SZ_1M + dp_fw->size <= qproc->mba_size) {
 418                 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
 419                 qproc->dp_size = dp_fw->size;
 420         }
 421
 422         release_firmware(dp_fw);
 423 }
 424
 425 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 426 {
 427         struct q6v5 *qproc = rproc->priv;
 428         void *mba_region;
 429
 430         /* MBA is restricted to a maximum size of 1M */
 431         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 432                 dev_err(qproc->dev, "MBA firmware load failed\n");
 433                 return -EINVAL;
 434         }
 435
 436         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 437         if (!mba_region) {
 438                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 439                         &qproc->mba_phys, qproc->mba_size);
 440                 return -EBUSY;
 441         }
 442
 443         memcpy(mba_region, fw->data, fw->size);
 444         q6v5_debug_policy_load(qproc, mba_region);
 445         memunmap(mba_region);
 446
 447         return 0;
 448 }
 449
 450 static int q6v5_reset_assert(struct q6v5 *qproc)
 451 {
 452         int ret;
 453
 454         if (qproc->has_alt_reset) {
 455                 reset_control_assert(qproc->pdc_reset);
 456                 ret = reset_control_reset(qproc->mss_restart);
 457                 reset_control_deassert(qproc->pdc_reset);
 458         } else if (qproc->has_spare_reg) {
 459                 /*
 460                  * When the AXI pipeline is being reset with the Q6 modem partly
 461                  * operational there is possibility of AXI valid signal to
 462                  * glitch, leading to spurious transactions and Q6 hangs. A work
 463                  * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
 464                  * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
 465                  * is withdrawn post MSS assert followed by a MSS deassert,
 466                  * while holding the PDC reset.
 467                  */
 468                 reset_control_assert(qproc->pdc_reset);
 469                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 470                                    AXI_GATING_VALID_OVERRIDE, 1);
 471                 reset_control_assert(qproc->mss_restart);
 472                 reset_control_deassert(qproc->pdc_reset);
 473                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 474                                    AXI_GATING_VALID_OVERRIDE, 0);
 475                 ret = reset_control_deassert(qproc->mss_restart);
 476         } else {
 477                 ret = reset_control_assert(qproc->mss_restart);
 478         }
 479
 480         return ret;
 481 }
 482
 483 static int q6v5_reset_deassert(struct q6v5 *qproc)
 484 {
 485         int ret;
 486
 487         if (qproc->has_alt_reset) {
 488                 reset_control_assert(qproc->pdc_reset);
 489                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 490                 ret = reset_control_reset(qproc->mss_restart);
 491                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 492                 reset_control_deassert(qproc->pdc_reset);
 493         } else if (qproc->has_spare_reg) {
 494                 ret = reset_control_reset(qproc->mss_restart);
 495         } else {
 496                 ret = reset_control_deassert(qproc->mss_restart);
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 503 {
 504         unsigned long timeout;
 505         s32 val;
 506
 507         timeout = jiffies + msecs_to_jiffies(ms);
 508         for (;;) {
 509                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 510                 if (val)
 511                         break;
 512
 513                 if (time_after(jiffies, timeout))
 514                         return -ETIMEDOUT;
 515
 516                 msleep(1);
 517         }
 518
 519         return val;
 520 }
 521
 522 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 523 {
 524
 525         unsigned long timeout;
 526         s32 val;
 527
 528         timeout = jiffies + msecs_to_jiffies(ms);
 529         for (;;) {
 530                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 531                 if (val < 0)
 532                         break;
 533
 534                 if (!status && val)
 535                         break;
 536                 else if (status && val == status)
 537                         break;
 538
 539                 if (time_after(jiffies, timeout))
 540                         return -ETIMEDOUT;
 541
 542                 msleep(1);
 543         }
 544
 545         return val;
 546 }
 547
 548 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
 549 {
 550         struct rproc *rproc = qproc->rproc;
 551         void *data;
 552         void *mba_region;
 553
 554         if (!qproc->has_mba_logs)
 555                 return;
 556
 557         if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
 558                                     qproc->mba_size))
 559                 return;
 560
 561         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 562         if (!mba_region)
 563                 return;
 564
 565         data = vmalloc(MBA_LOG_SIZE);
 566         if (data) {
 567                 memcpy(data, mba_region, MBA_LOG_SIZE);
 568                 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
 569         }
 570         memunmap(mba_region);
 571 }
 572
 573 static int q6v5proc_reset(struct q6v5 *qproc)
 574 {
 575         u32 val;
 576         int ret;
 577         int i;
 578
 579         if (qproc->version == MSS_SDM845) {
 580                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 581                 val |= Q6SS_CBCR_CLKEN;
 582                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 583
 584                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 585                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 586                                          Q6SS_CBCR_TIMEOUT_US);
 587                 if (ret) {
 588                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 589                         return -ETIMEDOUT;
 590                 }
 591
 592                 /* De-assert QDSP6 stop core */
 593                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 594                 /* Trigger boot FSM */
 595                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 596
 597                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 598                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 599                 if (ret) {
 600                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 601                         /* Reset the modem so that boot FSM is in reset state */
 602                         q6v5_reset_deassert(qproc);
 603                         return ret;
 604                 }
 605
 606                 goto pbl_wait;
 607         } else if (qproc->version == MSS_SC7180) {
 608                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 609                 val |= Q6SS_CBCR_CLKEN;
 610                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 611
 612                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 613                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 614                                          Q6SS_CBCR_TIMEOUT_US);
 615                 if (ret) {
 616                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 617                         return -ETIMEDOUT;
 618                 }
 619
 620                 /* Turn on the XO clock needed for PLL setup */
 621                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 622                 val |= Q6SS_CBCR_CLKEN;
 623                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 624
 625                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 626                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 627                                          Q6SS_CBCR_TIMEOUT_US);
 628                 if (ret) {
 629                         dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
 630                         return -ETIMEDOUT;
 631                 }
 632
 633                 /* Configure Q6 core CBCR to auto-enable after reset sequence */
 634                 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
 635                 val |= Q6SS_CBCR_CLKEN;
 636                 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
 637
 638                 /* De-assert the Q6 stop core signal */
 639                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 640
 641                 /* Wait for 10 us for any staggering logic to settle */
 642                 usleep_range(10, 20);
 643
 644                 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
 645                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 646
 647                 /* Poll the MSS_STATUS for FSM completion */
 648                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 649                                          val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 650                 if (ret) {
 651                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 652                         /* Reset the modem so that boot FSM is in reset state */
 653                         q6v5_reset_deassert(qproc);
 654                         return ret;
 655                 }
 656                 goto pbl_wait;
 657         } else if (qproc->version == MSS_MSM8996 ||
 658                    qproc->version == MSS_MSM8998) {
 659                 int mem_pwr_ctl;
 660
 661                 /* Override the ACC value if required */
 662                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 663                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 664
 665                 /* Assert resets, stop core */
 666                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 667                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 668                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 669
 670                 /* BHS require xo cbcr to be enabled */
 671                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 672                 val |= Q6SS_CBCR_CLKEN;
 673                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 674
 675                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 676                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 677                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 678                                          Q6SS_CBCR_TIMEOUT_US);
 679                 if (ret) {
 680                         dev_err(qproc->dev,
 681                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 682                         return ret;
 683                 }
 684                 /* Enable power block headswitch and wait for it to stabilize */
 685                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 686                 val |= QDSP6v56_BHS_ON;
 687                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 688                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 689                 udelay(1);
 690
 691                 /* Put LDO in bypass mode */
 692                 val |= QDSP6v56_LDO_BYP;
 693                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 694
 695                 /* Deassert QDSP6 compiler memory clamp */
 696                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 697                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 698                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 699
 700                 /* Deassert memory peripheral sleep and L2 memory standby */
 701                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 702                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 703
 704                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 705                 if (qproc->version == MSS_MSM8996) {
 706                         mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
 707                         i = 19;
 708                 } else {
 709                         /* MSS_MSM8998 */
 710                         mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
 711                         i = 28;
 712                 }
 713                 val = readl(qproc->reg_base + mem_pwr_ctl);
 714                 for (; i >= 0; i--) {
 715                         val |= BIT(i);
 716                         writel(val, qproc->reg_base + mem_pwr_ctl);
 717                         /*
 718                          * Read back value to ensure the write is done then
 719                          * wait for 1us for both memory peripheral and data
 720                          * array to turn on.
 721                          */
 722                         val |= readl(qproc->reg_base + mem_pwr_ctl);
 723                         udelay(1);
 724                 }
 725                 /* Remove word line clamp */
 726                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 727                 val &= ~QDSP6v56_CLAMP_WL;
 728                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 729         } else {
 730                 /* Assert resets, stop core */
 731                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 732                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 733                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 734
 735                 /* Enable power block headswitch and wait for it to stabilize */
 736                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 737                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 738                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 739                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 740                 udelay(1);
 741                 /*
 742                  * Turn on memories. L2 banks should be done individually
 743                  * to minimize inrush current.
 744                  */
 745                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 746                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 747                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 748                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 749                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 750                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 751                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 752                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 753                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 754                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 755         }
 756         /* Remove IO clamp */
 757         val &= ~Q6SS_CLAMP_IO;
 758         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 759
 760         /* Bring core out of reset */
 761         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 762         val &= ~Q6SS_CORE_ARES;
 763         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 764
 765         /* Turn on core clock */
 766         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 767         val |= Q6SS_CLK_ENABLE;
 768         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 769
 770         /* Start core execution */
 771         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 772         val &= ~Q6SS_STOP_CORE;
 773         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 774
 775 pbl_wait:
 776         /* Wait for PBL status */
 777         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 778         if (ret == -ETIMEDOUT) {
 779                 dev_err(qproc->dev, "PBL boot timed out\n");
 780         } else if (ret != RMB_PBL_SUCCESS) {
 781                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 782                 ret = -EINVAL;
 783         } else {
 784                 ret = 0;
 785         }
 786
 787         return ret;
 788 }
 789
 790 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 791                                    struct regmap *halt_map,
 792                                    u32 offset)
 793 {
 794         unsigned int val;
 795         int ret;
 796
 797         /* Check if we're already idle */
 798         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 799         if (!ret && val)
 800                 return;
 801
 802         /* Assert halt request */
 803         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 804
 805         /* Wait for halt */
 806         regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
 807                                  val, 1000, HALT_ACK_TIMEOUT_US);
 808
 809         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 810         if (ret || !val)
 811                 dev_err(qproc->dev, "port failed halt\n");
 812
 813         /* Clear halt request (port will remain halted until reset) */
 814         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 815 }
 816
 817 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 818 {
 819         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 820         dma_addr_t phys;
 821         void *metadata;
 822         int mdata_perm;
 823         int xferop_ret;
 824         size_t size;
 825         void *ptr;
 826         int ret;
 827
 828         metadata = qcom_mdt_read_metadata(fw, &size);
 829         if (IS_ERR(metadata))
 830                 return PTR_ERR(metadata);
 831
 832         ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
 833         if (!ptr) {
 834                 kfree(metadata);
 835                 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 836                 return -ENOMEM;
 837         }
 838
 839         memcpy(ptr, metadata, size);
 840
 841         /* Hypervisor mapping to access metadata by modem */
 842         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 843         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
 844                                       phys, size);
 845         if (ret) {
 846                 dev_err(qproc->dev,
 847                         "assigning Q6 access to metadata failed: %d\n", ret);
 848                 ret = -EAGAIN;
 849                 goto free_dma_attrs;
 850         }
 851
 852         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 853         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 854
 855         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 856         if (ret == -ETIMEDOUT)
 857                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 858         else if (ret < 0)
 859                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
 860
 861         /* Metadata authentication done, remove modem access */
 862         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
 863                                              phys, size);
 864         if (xferop_ret)
 865                 dev_warn(qproc->dev,
 866                          "mdt buffer not reclaimed system may become unstable\n");
 867
 868 free_dma_attrs:
 869         dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
 870         kfree(metadata);
 871
 872         return ret < 0 ? ret : 0;
 873 }
 874
 875 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
 876 {
 877         if (phdr->p_type != PT_LOAD)
 878                 return false;
 879
 880         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 881                 return false;
 882
 883         if (!phdr->p_memsz)
 884                 return false;
 885
 886         return true;
 887 }
 888
 889 static int q6v5_mba_load(struct q6v5 *qproc)
 890 {
 891         int ret;
 892         int xfermemop_ret;
 893         bool mba_load_err = false;
 894
 895         qcom_q6v5_prepare(&qproc->q6v5);
 896
 897         ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
 898         if (ret < 0) {
 899                 dev_err(qproc->dev, "failed to enable active power domains\n");
 900                 goto disable_irqs;
 901         }
 902
 903         ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
 904         if (ret < 0) {
 905                 dev_err(qproc->dev, "failed to enable proxy power domains\n");
 906                 goto disable_active_pds;
 907         }
 908
 909         ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
 910                                     qproc->fallback_proxy_reg_count);
 911         if (ret) {
 912                 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
 913                 goto disable_proxy_pds;
 914         }
 915
 916         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
 917                                     qproc->proxy_reg_count);
 918         if (ret) {
 919                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
 920                 goto disable_fallback_proxy_reg;
 921         }
 922
 923         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
 924                               qproc->proxy_clk_count);
 925         if (ret) {
 926                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
 927                 goto disable_proxy_reg;
 928         }
 929
 930         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
 931                                     qproc->active_reg_count);
 932         if (ret) {
 933                 dev_err(qproc->dev, "failed to enable supplies\n");
 934                 goto disable_proxy_clk;
 935         }
 936
 937         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
 938                               qproc->reset_clk_count);
 939         if (ret) {
 940                 dev_err(qproc->dev, "failed to enable reset clocks\n");
 941                 goto disable_vdd;
 942         }
 943
 944         ret = q6v5_reset_deassert(qproc);
 945         if (ret) {
 946                 dev_err(qproc->dev, "failed to deassert mss restart\n");
 947                 goto disable_reset_clks;
 948         }
 949
 950         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
 951                               qproc->active_clk_count);
 952         if (ret) {
 953                 dev_err(qproc->dev, "failed to enable clocks\n");
 954                 goto assert_reset;
 955         }
 956
 957         /*
 958          * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
 959          * the Q6 access to this region.
 960          */
 961         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
 962                                       qproc->mpss_phys, qproc->mpss_size);
 963         if (ret) {
 964                 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
 965                 goto disable_active_clks;
 966         }
 967
 968         /* Assign MBA image access in DDR to q6 */
 969         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
 970                                       qproc->mba_phys, qproc->mba_size);
 971         if (ret) {
 972                 dev_err(qproc->dev,
 973                         "assigning Q6 access to mba memory failed: %d\n", ret);
 974                 goto disable_active_clks;
 975         }
 976
 977         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
 978         if (qproc->dp_size) {
 979                 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
 980                 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 981         }
 982
 983         ret = q6v5proc_reset(qproc);
 984         if (ret)
 985                 goto reclaim_mba;
 986
 987         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
 988         if (ret == -ETIMEDOUT) {
 989                 dev_err(qproc->dev, "MBA boot timed out\n");
 990                 goto halt_axi_ports;
 991         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
 992                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
 993                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
 994                 ret = -EINVAL;
 995                 goto halt_axi_ports;
 996         }
 997
 998         qproc->dump_mba_loaded = true;
 999         return 0;
1000
1001 halt_axi_ports:
1002         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1003         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1004         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1005         mba_load_err = true;
1006 reclaim_mba:
1007         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1008                                                 false, qproc->mba_phys,
1009                                                 qproc->mba_size);
1010         if (xfermemop_ret) {
1011                 dev_err(qproc->dev,
1012                         "Failed to reclaim mba buffer, system may become unstable\n");
1013         } else if (mba_load_err) {
1014                 q6v5_dump_mba_logs(qproc);
1015         }
1016
1017 disable_active_clks:
1018         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1019                          qproc->active_clk_count);
1020 assert_reset:
1021         q6v5_reset_assert(qproc);
1022 disable_reset_clks:
1023         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1024                          qproc->reset_clk_count);
1025 disable_vdd:
1026         q6v5_regulator_disable(qproc, qproc->active_regs,
1027                                qproc->active_reg_count);
1028 disable_proxy_clk:
1029         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1030                          qproc->proxy_clk_count);
1031 disable_proxy_reg:
1032         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1033                                qproc->proxy_reg_count);
1034 disable_fallback_proxy_reg:
1035         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1036                                qproc->fallback_proxy_reg_count);
1037 disable_proxy_pds:
1038         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1039 disable_active_pds:
1040         q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1041 disable_irqs:
1042         qcom_q6v5_unprepare(&qproc->q6v5);
1043
1044         return ret;
1045 }
1046
1047 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1048 {
1049         int ret;
1050         u32 val;
1051
1052         qproc->dump_mba_loaded = false;
1053         qproc->dp_size = 0;
1054
1055         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1056         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1057         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1058         if (qproc->version == MSS_MSM8996) {
1059                 /*
1060                  * To avoid high MX current during LPASS/MSS restart.
1061                  */
1062                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1063                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1064                         QDSP6v56_CLAMP_QMC_MEM;
1065                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1066         }
1067
1068         q6v5_reset_assert(qproc);
1069
1070         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1071                          qproc->reset_clk_count);
1072         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1073                          qproc->active_clk_count);
1074         q6v5_regulator_disable(qproc, qproc->active_regs,
1075                                qproc->active_reg_count);
1076         q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1077
1078         /* In case of failure or coredump scenario where reclaiming MBA memory
1079          * could not happen reclaim it here.
1080          */
1081         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1082                                       qproc->mba_phys,
1083                                       qproc->mba_size);
1084         WARN_ON(ret);
1085
1086         ret = qcom_q6v5_unprepare(&qproc->q6v5);
1087         if (ret) {
1088                 q6v5_pds_disable(qproc, qproc->proxy_pds,
1089                                  qproc->proxy_pd_count);
1090                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1091                                  qproc->proxy_clk_count);
1092                 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1093                                        qproc->fallback_proxy_reg_count);
1094                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1095                                        qproc->proxy_reg_count);
1096         }
1097 }
1098
1099 static int q6v5_reload_mba(struct rproc *rproc)
1100 {
1101         struct q6v5 *qproc = rproc->priv;
1102         const struct firmware *fw;
1103         int ret;
1104
1105         ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1106         if (ret < 0)
1107                 return ret;
1108
1109         q6v5_load(rproc, fw);
1110         ret = q6v5_mba_load(qproc);
1111         release_firmware(fw);
1112
1113         return ret;
1114 }
1115
1116 static int q6v5_mpss_load(struct q6v5 *qproc)
1117 {
1118         const struct elf32_phdr *phdrs;
1119         const struct elf32_phdr *phdr;
1120         const struct firmware *seg_fw;
1121         const struct firmware *fw;
1122         struct elf32_hdr *ehdr;
1123         phys_addr_t mpss_reloc;
1124         phys_addr_t boot_addr;
1125         phys_addr_t min_addr = PHYS_ADDR_MAX;
1126         phys_addr_t max_addr = 0;
1127         u32 code_length;
1128         bool relocate = false;
1129         char *fw_name;
1130         size_t fw_name_len;
1131         ssize_t offset;
1132         size_t size = 0;
1133         void *ptr;
1134         int ret;
1135         int i;
1136
1137         fw_name_len = strlen(qproc->hexagon_mdt_image);
1138         if (fw_name_len <= 4)
1139                 return -EINVAL;
1140
1141         fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1142         if (!fw_name)
1143                 return -ENOMEM;
1144
1145         ret = request_firmware(&fw, fw_name, qproc->dev);
1146         if (ret < 0) {
1147                 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1148                 goto out;
1149         }
1150
1151         /* Initialize the RMB validator */
1152         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1153
1154         ret = q6v5_mpss_init_image(qproc, fw);
1155         if (ret)
1156                 goto release_firmware;
1157
1158         ehdr = (struct elf32_hdr *)fw->data;
1159         phdrs = (struct elf32_phdr *)(ehdr + 1);
1160
1161         for (i = 0; i < ehdr->e_phnum; i++) {
1162                 phdr = &phdrs[i];
1163
1164                 if (!q6v5_phdr_valid(phdr))
1165                         continue;
1166
1167                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1168                         relocate = true;
1169
1170                 if (phdr->p_paddr < min_addr)
1171                         min_addr = phdr->p_paddr;
1172
1173                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1174                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1175         }
1176
1177         /*
1178          * In case of a modem subsystem restart on secure devices, the modem
1179          * memory can be reclaimed only after MBA is loaded.
1180          */
1181         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1182                                 qproc->mpss_phys, qproc->mpss_size);
1183
1184         /* Share ownership between Linux and MSS, during segment loading */
1185         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1186                                       qproc->mpss_phys, qproc->mpss_size);
1187         if (ret) {
1188                 dev_err(qproc->dev,
1189                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1190                 ret = -EAGAIN;
1191                 goto release_firmware;
1192         }
1193
1194         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1195         qproc->mpss_reloc = mpss_reloc;
1196         /* Load firmware segments */
1197         for (i = 0; i < ehdr->e_phnum; i++) {
1198                 phdr = &phdrs[i];
1199
1200                 if (!q6v5_phdr_valid(phdr))
1201                         continue;
1202
1203                 offset = phdr->p_paddr - mpss_reloc;
1204                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1205                         dev_err(qproc->dev, "segment outside memory range\n");
1206                         ret = -EINVAL;
1207                         goto release_firmware;
1208                 }
1209
1210                 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1211                 if (!ptr) {
1212                         dev_err(qproc->dev,
1213                                 "unable to map memory region: %pa+%zx-%x\n",
1214                                 &qproc->mpss_phys, offset, phdr->p_memsz);
1215                         goto release_firmware;
1216                 }
1217
1218                 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1219                         /* Firmware is large enough to be non-split */
1220                         if (phdr->p_offset + phdr->p_filesz > fw->size) {
1221                                 dev_err(qproc->dev,
1222                                         "failed to load segment %d from truncated file %s\n",
1223                                         i, fw_name);
1224                                 ret = -EINVAL;
1225                                 memunmap(ptr);
1226                                 goto release_firmware;
1227                         }
1228
1229                         memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1230                 } else if (phdr->p_filesz) {
1231                         /* Replace "xxx.xxx" with "xxx.bxx" */
1232                         sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1233                         ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1234                                                         ptr, phdr->p_filesz);
1235                         if (ret) {
1236                                 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1237                                 memunmap(ptr);
1238                                 goto release_firmware;
1239                         }
1240
1241                         release_firmware(seg_fw);
1242                 }
1243
1244                 if (phdr->p_memsz > phdr->p_filesz) {
1245                         memset(ptr + phdr->p_filesz, 0,
1246                                phdr->p_memsz - phdr->p_filesz);
1247                 }
1248                 memunmap(ptr);
1249                 size += phdr->p_memsz;
1250
1251                 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1252                 if (!code_length) {
1253                         boot_addr = relocate ? qproc->mpss_phys : min_addr;
1254                         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1255                         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1256                 }
1257                 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1258
1259                 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1260                 if (ret < 0) {
1261                         dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1262                                 ret);
1263                         goto release_firmware;
1264                 }
1265         }
1266
1267         /* Transfer ownership of modem ddr region to q6 */
1268         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1269                                       qproc->mpss_phys, qproc->mpss_size);
1270         if (ret) {
1271                 dev_err(qproc->dev,
1272                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1273                 ret = -EAGAIN;
1274                 goto release_firmware;
1275         }
1276
1277         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1278         if (ret == -ETIMEDOUT)
1279                 dev_err(qproc->dev, "MPSS authentication timed out\n");
1280         else if (ret < 0)
1281                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1282
1283         qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1284
1285 release_firmware:
1286         release_firmware(fw);
1287 out:
1288         kfree(fw_name);
1289
1290         return ret < 0 ? ret : 0;
1291 }
1292
1293 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1294                                    struct rproc_dump_segment *segment,
1295                                    void *dest, size_t cp_offset, size_t size)
1296 {
1297         int ret = 0;
1298         struct q6v5 *qproc = rproc->priv;
1299         int offset = segment->da - qproc->mpss_reloc;
1300         void *ptr = NULL;
1301
1302         /* Unlock mba before copying segments */
1303         if (!qproc->dump_mba_loaded) {
1304                 ret = q6v5_reload_mba(rproc);
1305                 if (!ret) {
1306                         /* Reset ownership back to Linux to copy segments */
1307                         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1308                                                       true, false,
1309                                                       qproc->mpss_phys,
1310                                                       qproc->mpss_size);
1311                 }
1312         }
1313
1314         if (!ret)
1315                 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1316
1317         if (ptr) {
1318                 memcpy(dest, ptr, size);
1319                 memunmap(ptr);
1320         } else {
1321                 memset(dest, 0xff, size);
1322         }
1323
1324         qproc->current_dump_size += size;
1325
1326         /* Reclaim mba after copying segments */
1327         if (qproc->current_dump_size == qproc->total_dump_size) {
1328                 if (qproc->dump_mba_loaded) {
1329                         /* Try to reset ownership back to Q6 */
1330                         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1331                                                 false, true,
1332                                                 qproc->mpss_phys,
1333                                                 qproc->mpss_size);
1334                         q6v5_mba_reclaim(qproc);
1335                 }
1336         }
1337 }
1338
1339 static int q6v5_start(struct rproc *rproc)
1340 {
1341         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1342         int xfermemop_ret;
1343         int ret;
1344
1345         ret = q6v5_mba_load(qproc);
1346         if (ret)
1347                 return ret;
1348
1349         dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1350                  qproc->dp_size ? "" : "out");
1351
1352         ret = q6v5_mpss_load(qproc);
1353         if (ret)
1354                 goto reclaim_mpss;
1355
1356         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1357         if (ret == -ETIMEDOUT) {
1358                 dev_err(qproc->dev, "start timed out\n");
1359                 goto reclaim_mpss;
1360         }
1361
1362         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1363                                                 false, qproc->mba_phys,
1364                                                 qproc->mba_size);
1365         if (xfermemop_ret)
1366                 dev_err(qproc->dev,
1367                         "Failed to reclaim mba buffer system may become unstable\n");
1368
1369         /* Reset Dump Segment Mask */
1370         qproc->current_dump_size = 0;
1371
1372         return 0;
1373
1374 reclaim_mpss:
1375         q6v5_mba_reclaim(qproc);
1376         q6v5_dump_mba_logs(qproc);
1377
1378         return ret;
1379 }
1380
1381 static int q6v5_stop(struct rproc *rproc)
1382 {
1383         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1384         int ret;
1385
1386         ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1387         if (ret == -ETIMEDOUT)
1388                 dev_err(qproc->dev, "timed out on wait\n");
1389
1390         q6v5_mba_reclaim(qproc);
1391
1392         return 0;
1393 }
1394
1395 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1396                                             const struct firmware *mba_fw)
1397 {
1398         const struct firmware *fw;
1399         const struct elf32_phdr *phdrs;
1400         const struct elf32_phdr *phdr;
1401         const struct elf32_hdr *ehdr;
1402         struct q6v5 *qproc = rproc->priv;
1403         unsigned long i;
1404         int ret;
1405
1406         ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1407         if (ret < 0) {
1408                 dev_err(qproc->dev, "unable to load %s\n",
1409                         qproc->hexagon_mdt_image);
1410                 return ret;
1411         }
1412
1413         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1414
1415         ehdr = (struct elf32_hdr *)fw->data;
1416         phdrs = (struct elf32_phdr *)(ehdr + 1);
1417         qproc->total_dump_size = 0;
1418
1419         for (i = 0; i < ehdr->e_phnum; i++) {
1420                 phdr = &phdrs[i];
1421
1422                 if (!q6v5_phdr_valid(phdr))
1423                         continue;
1424
1425                 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1426                                                         phdr->p_memsz,
1427                                                         qcom_q6v5_dump_segment,
1428                                                         NULL);
1429                 if (ret)
1430                         break;
1431
1432                 qproc->total_dump_size += phdr->p_memsz;
1433         }
1434
1435         release_firmware(fw);
1436         return ret;
1437 }
1438
1439 static const struct rproc_ops q6v5_ops = {
1440         .start = q6v5_start,
1441         .stop = q6v5_stop,
1442         .parse_fw = qcom_q6v5_register_dump_segments,
1443         .load = q6v5_load,
1444 };
1445
1446 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1447 {
1448         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1449
1450         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1451                          qproc->proxy_clk_count);
1452         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1453                                qproc->proxy_reg_count);
1454         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1455                                qproc->fallback_proxy_reg_count);
1456         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1457 }
1458
1459 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1460 {
1461         struct of_phandle_args args;
1462         struct resource *res;
1463         int ret;
1464
1465         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1466         qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1467         if (IS_ERR(qproc->reg_base))
1468                 return PTR_ERR(qproc->reg_base);
1469
1470         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1471         qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1472         if (IS_ERR(qproc->rmb_base))
1473                 return PTR_ERR(qproc->rmb_base);
1474
1475         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1476                                                "qcom,halt-regs", 3, 0, &args);
1477         if (ret < 0) {
1478                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1479                 return -EINVAL;
1480         }
1481
1482         qproc->halt_map = syscon_node_to_regmap(args.np);
1483         of_node_put(args.np);
1484         if (IS_ERR(qproc->halt_map))
1485                 return PTR_ERR(qproc->halt_map);
1486
1487         qproc->halt_q6 = args.args[0];
1488         qproc->halt_modem = args.args[1];
1489         qproc->halt_nc = args.args[2];
1490
1491         if (qproc->has_spare_reg) {
1492                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1493                                                        "qcom,spare-regs",
1494                                                        1, 0, &args);
1495                 if (ret < 0) {
1496                         dev_err(&pdev->dev, "failed to parse spare-regs\n");
1497                         return -EINVAL;
1498                 }
1499
1500                 qproc->conn_map = syscon_node_to_regmap(args.np);
1501                 of_node_put(args.np);
1502                 if (IS_ERR(qproc->conn_map))
1503                         return PTR_ERR(qproc->conn_map);
1504
1505                 qproc->conn_box = args.args[0];
1506         }
1507
1508         return 0;
1509 }
1510
1511 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1512                 char **clk_names)
1513 {
1514         int i;
1515
1516         if (!clk_names)
1517                 return 0;
1518
1519         for (i = 0; clk_names[i]; i++) {
1520                 clks[i] = devm_clk_get(dev, clk_names[i]);
1521                 if (IS_ERR(clks[i])) {
1522                         int rc = PTR_ERR(clks[i]);
1523
1524                         if (rc != -EPROBE_DEFER)
1525                                 dev_err(dev, "Failed to get %s clock\n",
1526                                         clk_names[i]);
1527                         return rc;
1528                 }
1529         }
1530
1531         return i;
1532 }
1533
1534 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1535                            char **pd_names)
1536 {
1537         size_t num_pds = 0;
1538         int ret;
1539         int i;
1540
1541         if (!pd_names)
1542                 return 0;
1543
1544         while (pd_names[num_pds])
1545                 num_pds++;
1546
1547         for (i = 0; i < num_pds; i++) {
1548                 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1549                 if (IS_ERR_OR_NULL(devs[i])) {
1550                         ret = PTR_ERR(devs[i]) ? : -ENODATA;
1551                         goto unroll_attach;
1552                 }
1553         }
1554
1555         return num_pds;
1556
1557 unroll_attach:
1558         for (i--; i >= 0; i--)
1559                 dev_pm_domain_detach(devs[i], false);
1560
1561         return ret;
1562 }
1563
1564 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1565                             size_t pd_count)
1566 {
1567         int i;
1568
1569         for (i = 0; i < pd_count; i++)
1570                 dev_pm_domain_detach(pds[i], false);
1571 }
1572
1573 static int q6v5_init_reset(struct q6v5 *qproc)
1574 {
1575         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1576                                                               "mss_restart");
1577         if (IS_ERR(qproc->mss_restart)) {
1578                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1579                 return PTR_ERR(qproc->mss_restart);
1580         }
1581
1582         if (qproc->has_alt_reset || qproc->has_spare_reg) {
1583                 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1584                                                                     "pdc_reset");
1585                 if (IS_ERR(qproc->pdc_reset)) {
1586                         dev_err(qproc->dev, "failed to acquire pdc reset\n");
1587                         return PTR_ERR(qproc->pdc_reset);
1588                 }
1589         }
1590
1591         return 0;
1592 }
1593
1594 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1595 {
1596         struct device_node *child;
1597         struct device_node *node;
1598         struct resource r;
1599         int ret;
1600
1601         /*
1602          * In the absence of mba/mpss sub-child, extract the mba and mpss
1603          * reserved memory regions from device's memory-region property.
1604          */
1605         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1606         if (!child)
1607                 node = of_parse_phandle(qproc->dev->of_node,
1608                                         "memory-region", 0);
1609         else
1610                 node = of_parse_phandle(child, "memory-region", 0);
1611
1612         ret = of_address_to_resource(node, 0, &r);
1613         if (ret) {
1614                 dev_err(qproc->dev, "unable to resolve mba region\n");
1615                 return ret;
1616         }
1617         of_node_put(node);
1618
1619         qproc->mba_phys = r.start;
1620         qproc->mba_size = resource_size(&r);
1621
1622         if (!child) {
1623                 node = of_parse_phandle(qproc->dev->of_node,
1624                                         "memory-region", 1);
1625         } else {
1626                 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1627                 node = of_parse_phandle(child, "memory-region", 0);
1628         }
1629
1630         ret = of_address_to_resource(node, 0, &r);
1631         if (ret) {
1632                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1633                 return ret;
1634         }
1635         of_node_put(node);
1636
1637         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1638         qproc->mpss_size = resource_size(&r);
1639
1640         return 0;
1641 }
1642
1643 static int q6v5_probe(struct platform_device *pdev)
1644 {
1645         const struct rproc_hexagon_res *desc;
1646         struct q6v5 *qproc;
1647         struct rproc *rproc;
1648         const char *mba_image;
1649         int ret;
1650
1651         desc = of_device_get_match_data(&pdev->dev);
1652         if (!desc)
1653                 return -EINVAL;
1654
1655         if (desc->need_mem_protection && !qcom_scm_is_available())
1656                 return -EPROBE_DEFER;
1657
1658         mba_image = desc->hexagon_mba_image;
1659         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1660                                             0, &mba_image);
1661         if (ret < 0 && ret != -EINVAL)
1662                 return ret;
1663
1664         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1665                             mba_image, sizeof(*qproc));
1666         if (!rproc) {
1667                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1668                 return -ENOMEM;
1669         }
1670
1671         rproc->auto_boot = false;
1672         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1673
1674         qproc = (struct q6v5 *)rproc->priv;
1675         qproc->dev = &pdev->dev;
1676         qproc->rproc = rproc;
1677         qproc->hexagon_mdt_image = "modem.mdt";
1678         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1679                                             1, &qproc->hexagon_mdt_image);
1680         if (ret < 0 && ret != -EINVAL)
1681                 goto free_rproc;
1682
1683         platform_set_drvdata(pdev, qproc);
1684
1685         qproc->has_spare_reg = desc->has_spare_reg;
1686         ret = q6v5_init_mem(qproc, pdev);
1687         if (ret)
1688                 goto free_rproc;
1689
1690         ret = q6v5_alloc_memory_region(qproc);
1691         if (ret)
1692                 goto free_rproc;
1693
1694         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1695                                desc->proxy_clk_names);
1696         if (ret < 0) {
1697                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1698                 goto free_rproc;
1699         }
1700         qproc->proxy_clk_count = ret;
1701
1702         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1703                                desc->reset_clk_names);
1704         if (ret < 0) {
1705                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1706                 goto free_rproc;
1707         }
1708         qproc->reset_clk_count = ret;
1709
1710         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1711                                desc->active_clk_names);
1712         if (ret < 0) {
1713                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1714                 goto free_rproc;
1715         }
1716         qproc->active_clk_count = ret;
1717
1718         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1719                                   desc->proxy_supply);
1720         if (ret < 0) {
1721                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1722                 goto free_rproc;
1723         }
1724         qproc->proxy_reg_count = ret;
1725
1726         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
1727                                   desc->active_supply);
1728         if (ret < 0) {
1729                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1730                 goto free_rproc;
1731         }
1732         qproc->active_reg_count = ret;
1733
1734         ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1735                               desc->active_pd_names);
1736         if (ret < 0) {
1737                 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1738                 goto free_rproc;
1739         }
1740         qproc->active_pd_count = ret;
1741
1742         ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1743                               desc->proxy_pd_names);
1744         /* Fallback to regulators for old device trees */
1745         if (ret == -ENODATA && desc->fallback_proxy_supply) {
1746                 ret = q6v5_regulator_init(&pdev->dev,
1747                                           qproc->fallback_proxy_regs,
1748                                           desc->fallback_proxy_supply);
1749                 if (ret < 0) {
1750                         dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
1751                         goto detach_active_pds;
1752                 }
1753                 qproc->fallback_proxy_reg_count = ret;
1754         } else if (ret < 0) {
1755                 dev_err(&pdev->dev, "Failed to init power domains\n");
1756                 goto detach_active_pds;
1757         } else {
1758                 qproc->proxy_pd_count = ret;
1759         }
1760
1761         qproc->has_alt_reset = desc->has_alt_reset;
1762         ret = q6v5_init_reset(qproc);
1763         if (ret)
1764                 goto detach_proxy_pds;
1765
1766         qproc->version = desc->version;
1767         qproc->need_mem_protection = desc->need_mem_protection;
1768         qproc->has_mba_logs = desc->has_mba_logs;
1769
1770         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1771                              qcom_msa_handover);
1772         if (ret)
1773                 goto detach_proxy_pds;
1774
1775         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1776         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1777         qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1778         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1779         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1780         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1781         if (IS_ERR(qproc->sysmon)) {
1782                 ret = PTR_ERR(qproc->sysmon);
1783                 goto remove_subdevs;
1784         }
1785
1786         ret = rproc_add(rproc);
1787         if (ret)
1788                 goto remove_sysmon_subdev;
1789
1790         return 0;
1791
1792 remove_sysmon_subdev:
1793         qcom_remove_sysmon_subdev(qproc->sysmon);
1794 remove_subdevs:
1795         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1796         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1797         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1798 detach_proxy_pds:
1799         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1800 detach_active_pds:
1801         q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1802 free_rproc:
1803         rproc_free(rproc);
1804
1805         return ret;
1806 }
1807
1808 static int q6v5_remove(struct platform_device *pdev)
1809 {
1810         struct q6v5 *qproc = platform_get_drvdata(pdev);
1811         struct rproc *rproc = qproc->rproc;
1812
1813         rproc_del(rproc);
1814
1815         qcom_remove_sysmon_subdev(qproc->sysmon);
1816         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1817         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1818         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1819
1820         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1821         q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1822
1823         rproc_free(rproc);
1824
1825         return 0;
1826 }
1827
1828 static const struct rproc_hexagon_res sc7180_mss = {
1829         .hexagon_mba_image = "mba.mbn",
1830         .proxy_clk_names = (char*[]){
1831                 "xo",
1832                 NULL
1833         },
1834         .reset_clk_names = (char*[]){
1835                 "iface",
1836                 "bus",
1837                 "snoc_axi",
1838                 NULL
1839         },
1840         .active_clk_names = (char*[]){
1841                 "mnoc_axi",
1842                 "nav",
1843                 NULL
1844         },
1845         .active_pd_names = (char*[]){
1846                 "load_state",
1847                 NULL
1848         },
1849         .proxy_pd_names = (char*[]){
1850                 "cx",
1851                 "mx",
1852                 "mss",
1853                 NULL
1854         },
1855         .need_mem_protection = true,
1856         .has_alt_reset = false,
1857         .has_mba_logs = true,
1858         .has_spare_reg = true,
1859         .version = MSS_SC7180,
1860 };
1861
1862 static const struct rproc_hexagon_res sdm845_mss = {
1863         .hexagon_mba_image = "mba.mbn",
1864         .proxy_clk_names = (char*[]){
1865                         "xo",
1866                         "prng",
1867                         NULL
1868         },
1869         .reset_clk_names = (char*[]){
1870                         "iface",
1871                         "snoc_axi",
1872                         NULL
1873         },
1874         .active_clk_names = (char*[]){
1875                         "bus",
1876                         "mem",
1877                         "gpll0_mss",
1878                         "mnoc_axi",
1879                         NULL
1880         },
1881         .active_pd_names = (char*[]){
1882                         "load_state",
1883                         NULL
1884         },
1885         .proxy_pd_names = (char*[]){
1886                         "cx",
1887                         "mx",
1888                         "mss",
1889                         NULL
1890         },
1891         .need_mem_protection = true,
1892         .has_alt_reset = true,
1893         .has_mba_logs = false,
1894         .has_spare_reg = false,
1895         .version = MSS_SDM845,
1896 };
1897
1898 static const struct rproc_hexagon_res msm8998_mss = {
1899         .hexagon_mba_image = "mba.mbn",
1900         .proxy_clk_names = (char*[]){
1901                         "xo",
1902                         "qdss",
1903                         "mem",
1904                         NULL
1905         },
1906         .active_clk_names = (char*[]){
1907                         "iface",
1908                         "bus",
1909                         "gpll0_mss",
1910                         "mnoc_axi",
1911                         "snoc_axi",
1912                         NULL
1913         },
1914         .proxy_pd_names = (char*[]){
1915                         "cx",
1916                         "mx",
1917                         NULL
1918         },
1919         .need_mem_protection = true,
1920         .has_alt_reset = false,
1921         .has_mba_logs = false,
1922         .has_spare_reg = false,
1923         .version = MSS_MSM8998,
1924 };
1925
1926 static const struct rproc_hexagon_res msm8996_mss = {
1927         .hexagon_mba_image = "mba.mbn",
1928         .proxy_supply = (struct qcom_mss_reg_res[]) {
1929                 {
1930                         .supply = "pll",
1931                         .uA = 100000,
1932                 },
1933                 {}
1934         },
1935         .proxy_clk_names = (char*[]){
1936                         "xo",
1937                         "pnoc",
1938                         "qdss",
1939                         NULL
1940         },
1941         .active_clk_names = (char*[]){
1942                         "iface",
1943                         "bus",
1944                         "mem",
1945                         "gpll0_mss",
1946                         "snoc_axi",
1947                         "mnoc_axi",
1948                         NULL
1949         },
1950         .need_mem_protection = true,
1951         .has_alt_reset = false,
1952         .has_mba_logs = false,
1953         .has_spare_reg = false,
1954         .version = MSS_MSM8996,
1955 };
1956
1957 static const struct rproc_hexagon_res msm8916_mss = {
1958         .hexagon_mba_image = "mba.mbn",
1959         .proxy_supply = (struct qcom_mss_reg_res[]) {
1960                 {
1961                         .supply = "pll",
1962                         .uA = 100000,
1963                 },
1964                 {}
1965         },
1966         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
1967                 {
1968                         .supply = "mx",
1969                         .uV = 1050000,
1970                 },
1971                 {
1972                         .supply = "cx",
1973                         .uA = 100000,
1974                 },
1975                 {}
1976         },
1977         .proxy_clk_names = (char*[]){
1978                 "xo",
1979                 NULL
1980         },
1981         .active_clk_names = (char*[]){
1982                 "iface",
1983                 "bus",
1984                 "mem",
1985                 NULL
1986         },
1987         .proxy_pd_names = (char*[]){
1988                 "mx",
1989                 "cx",
1990                 NULL
1991         },
1992         .need_mem_protection = false,
1993         .has_alt_reset = false,
1994         .has_mba_logs = false,
1995         .has_spare_reg = false,
1996         .version = MSS_MSM8916,
1997 };
1998
1999 static const struct rproc_hexagon_res msm8974_mss = {
2000         .hexagon_mba_image = "mba.b00",
2001         .proxy_supply = (struct qcom_mss_reg_res[]) {
2002                 {
2003                         .supply = "pll",
2004                         .uA = 100000,
2005                 },
2006                 {}
2007         },
2008         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2009                 {
2010                         .supply = "mx",
2011                         .uV = 1050000,
2012                 },
2013                 {
2014                         .supply = "cx",
2015                         .uA = 100000,
2016                 },
2017                 {}
2018         },
2019         .active_supply = (struct qcom_mss_reg_res[]) {
2020                 {
2021                         .supply = "mss",
2022                         .uV = 1050000,
2023                         .uA = 100000,
2024                 },
2025                 {}
2026         },
2027         .proxy_clk_names = (char*[]){
2028                 "xo",
2029                 NULL
2030         },
2031         .active_clk_names = (char*[]){
2032                 "iface",
2033                 "bus",
2034                 "mem",
2035                 NULL
2036         },
2037         .proxy_pd_names = (char*[]){
2038                 "mx",
2039                 "cx",
2040                 NULL
2041         },
2042         .need_mem_protection = false,
2043         .has_alt_reset = false,
2044         .has_mba_logs = false,
2045         .has_spare_reg = false,
2046         .version = MSS_MSM8974,
2047 };
2048
2049 static const struct of_device_id q6v5_of_match[] = {
2050         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2051         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2052         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2053         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2054         { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2055         { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2056         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2057         { },
2058 };
2059 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2060
2061 static struct platform_driver q6v5_driver = {
2062         .probe = q6v5_probe,
2063         .remove = q6v5_remove,
2064         .driver = {
2065                 .name = "qcom-q6v5-mss",
2066                 .of_match_table = q6v5_of_match,
2067         },
2068 };
2069 module_platform_driver(q6v5_driver);
2070
2071 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2072 MODULE_LICENSE("GPL v2");