drivers/regulator/axp20x-regulator.c

   1 /*
   2  * AXP20x regulators driver.
   3  *
   4  * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General
   7  * Public License. See the file "COPYING" in the main directory of this
   8  * archive for more details.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/mfd/axp20x.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/regulator/driver.h>
  27 #include <linux/regulator/machine.h>
  28 #include <linux/regulator/of_regulator.h>
  29
  30 #define AXP20X_GPIO0_FUNC_MASK          GENMASK(3, 0)
  31 #define AXP20X_GPIO1_FUNC_MASK          GENMASK(3, 0)
  32
  33 #define AXP20X_IO_ENABLED               0x03
  34 #define AXP20X_IO_DISABLED              0x07
  35
  36 #define AXP20X_WORKMODE_DCDC2_MASK      BIT_MASK(2)
  37 #define AXP20X_WORKMODE_DCDC3_MASK      BIT_MASK(1)
  38
  39 #define AXP20X_FREQ_DCDC_MASK           GENMASK(3, 0)
  40
  41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK    BIT_MASK(2)
  42
  43 #define AXP20X_DCDC2_V_OUT_MASK         GENMASK(5, 0)
  44 #define AXP20X_DCDC3_V_OUT_MASK         GENMASK(7, 0)
  45 #define AXP20X_LDO24_V_OUT_MASK         GENMASK(7, 4)
  46 #define AXP20X_LDO3_V_OUT_MASK          GENMASK(6, 0)
  47 #define AXP20X_LDO5_V_OUT_MASK          GENMASK(7, 4)
  48
  49 #define AXP20X_PWR_OUT_EXTEN_MASK       BIT_MASK(0)
  50 #define AXP20X_PWR_OUT_DCDC3_MASK       BIT_MASK(1)
  51 #define AXP20X_PWR_OUT_LDO2_MASK        BIT_MASK(2)
  52 #define AXP20X_PWR_OUT_LDO4_MASK        BIT_MASK(3)
  53 #define AXP20X_PWR_OUT_DCDC2_MASK       BIT_MASK(4)
  54 #define AXP20X_PWR_OUT_LDO3_MASK        BIT_MASK(6)
  55
  56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK        BIT_MASK(0)
  57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
  58         ((x) << 0)
  59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK         BIT_MASK(1)
  60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
  61         ((x) << 1)
  62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK          BIT_MASK(2)
  63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN               BIT(2)
  64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK           BIT_MASK(3)
  65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN                BIT(3)
  66
  67 #define AXP20X_LDO4_V_OUT_1250mV_START  0x0
  68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS  0
  69 #define AXP20X_LDO4_V_OUT_1250mV_END    \
  70         (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
  71 #define AXP20X_LDO4_V_OUT_1300mV_START  0x1
  72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS  7
  73 #define AXP20X_LDO4_V_OUT_1300mV_END    \
  74         (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
  75 #define AXP20X_LDO4_V_OUT_2500mV_START  0x9
  76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS  0
  77 #define AXP20X_LDO4_V_OUT_2500mV_END    \
  78         (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
  79 #define AXP20X_LDO4_V_OUT_2700mV_START  0xa
  80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS  1
  81 #define AXP20X_LDO4_V_OUT_2700mV_END    \
  82         (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
  83 #define AXP20X_LDO4_V_OUT_3000mV_START  0xc
  84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS  3
  85 #define AXP20X_LDO4_V_OUT_3000mV_END    \
  86         (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
  87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES  16
  88
  89 #define AXP22X_IO_ENABLED               0x03
  90 #define AXP22X_IO_DISABLED              0x04
  91
  92 #define AXP22X_WORKMODE_DCDCX_MASK(x)   BIT_MASK(x)
  93
  94 #define AXP22X_MISC_N_VBUSEN_FUNC       BIT(4)
  95
  96 #define AXP22X_DCDC1_V_OUT_MASK         GENMASK(4, 0)
  97 #define AXP22X_DCDC2_V_OUT_MASK         GENMASK(5, 0)
  98 #define AXP22X_DCDC3_V_OUT_MASK         GENMASK(5, 0)
  99 #define AXP22X_DCDC4_V_OUT_MASK         GENMASK(5, 0)
 100 #define AXP22X_DCDC5_V_OUT_MASK         GENMASK(4, 0)
 101 #define AXP22X_DC5LDO_V_OUT_MASK        GENMASK(2, 0)
 102 #define AXP22X_ALDO1_V_OUT_MASK         GENMASK(4, 0)
 103 #define AXP22X_ALDO2_V_OUT_MASK         GENMASK(4, 0)
 104 #define AXP22X_ALDO3_V_OUT_MASK         GENMASK(4, 0)
 105 #define AXP22X_DLDO1_V_OUT_MASK         GENMASK(4, 0)
 106 #define AXP22X_DLDO2_V_OUT_MASK         GENMASK(4, 0)
 107 #define AXP22X_DLDO3_V_OUT_MASK         GENMASK(4, 0)
 108 #define AXP22X_DLDO4_V_OUT_MASK         GENMASK(4, 0)
 109 #define AXP22X_ELDO1_V_OUT_MASK         GENMASK(4, 0)
 110 #define AXP22X_ELDO2_V_OUT_MASK         GENMASK(4, 0)
 111 #define AXP22X_ELDO3_V_OUT_MASK         GENMASK(4, 0)
 112 #define AXP22X_LDO_IO0_V_OUT_MASK       GENMASK(4, 0)
 113 #define AXP22X_LDO_IO1_V_OUT_MASK       GENMASK(4, 0)
 114
 115 #define AXP22X_PWR_OUT_DC5LDO_MASK      BIT_MASK(0)
 116 #define AXP22X_PWR_OUT_DCDC1_MASK       BIT_MASK(1)
 117 #define AXP22X_PWR_OUT_DCDC2_MASK       BIT_MASK(2)
 118 #define AXP22X_PWR_OUT_DCDC3_MASK       BIT_MASK(3)
 119 #define AXP22X_PWR_OUT_DCDC4_MASK       BIT_MASK(4)
 120 #define AXP22X_PWR_OUT_DCDC5_MASK       BIT_MASK(5)
 121 #define AXP22X_PWR_OUT_ALDO1_MASK       BIT_MASK(6)
 122 #define AXP22X_PWR_OUT_ALDO2_MASK       BIT_MASK(7)
 123
 124 #define AXP22X_PWR_OUT_SW_MASK          BIT_MASK(6)
 125 #define AXP22X_PWR_OUT_DC1SW_MASK       BIT_MASK(7)
 126
 127 #define AXP22X_PWR_OUT_ELDO1_MASK       BIT_MASK(0)
 128 #define AXP22X_PWR_OUT_ELDO2_MASK       BIT_MASK(1)
 129 #define AXP22X_PWR_OUT_ELDO3_MASK       BIT_MASK(2)
 130 #define AXP22X_PWR_OUT_DLDO1_MASK       BIT_MASK(3)
 131 #define AXP22X_PWR_OUT_DLDO2_MASK       BIT_MASK(4)
 132 #define AXP22X_PWR_OUT_DLDO3_MASK       BIT_MASK(5)
 133 #define AXP22X_PWR_OUT_DLDO4_MASK       BIT_MASK(6)
 134 #define AXP22X_PWR_OUT_ALDO3_MASK       BIT_MASK(7)
 135
 136 #define AXP803_PWR_OUT_DCDC1_MASK       BIT_MASK(0)
 137 #define AXP803_PWR_OUT_DCDC2_MASK       BIT_MASK(1)
 138 #define AXP803_PWR_OUT_DCDC3_MASK       BIT_MASK(2)
 139 #define AXP803_PWR_OUT_DCDC4_MASK       BIT_MASK(3)
 140 #define AXP803_PWR_OUT_DCDC5_MASK       BIT_MASK(4)
 141 #define AXP803_PWR_OUT_DCDC6_MASK       BIT_MASK(5)
 142
 143 #define AXP803_PWR_OUT_FLDO1_MASK       BIT_MASK(2)
 144 #define AXP803_PWR_OUT_FLDO2_MASK       BIT_MASK(3)
 145
 146 #define AXP803_DCDC1_V_OUT_MASK         GENMASK(4, 0)
 147 #define AXP803_DCDC2_V_OUT_MASK         GENMASK(6, 0)
 148 #define AXP803_DCDC3_V_OUT_MASK         GENMASK(6, 0)
 149 #define AXP803_DCDC4_V_OUT_MASK         GENMASK(6, 0)
 150 #define AXP803_DCDC5_V_OUT_MASK         GENMASK(6, 0)
 151 #define AXP803_DCDC6_V_OUT_MASK         GENMASK(6, 0)
 152
 153 #define AXP803_FLDO1_V_OUT_MASK         GENMASK(3, 0)
 154 #define AXP803_FLDO2_V_OUT_MASK         GENMASK(3, 0)
 155
 156 #define AXP803_DCDC23_POLYPHASE_DUAL    BIT(6)
 157 #define AXP803_DCDC56_POLYPHASE_DUAL    BIT(5)
 158
 159 #define AXP803_DCDC234_500mV_START      0x00
 160 #define AXP803_DCDC234_500mV_STEPS      70
 161 #define AXP803_DCDC234_500mV_END        \
 162         (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
 163 #define AXP803_DCDC234_1220mV_START     0x47
 164 #define AXP803_DCDC234_1220mV_STEPS     4
 165 #define AXP803_DCDC234_1220mV_END       \
 166         (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
 167 #define AXP803_DCDC234_NUM_VOLTAGES     76
 168
 169 #define AXP803_DCDC5_800mV_START        0x00
 170 #define AXP803_DCDC5_800mV_STEPS        32
 171 #define AXP803_DCDC5_800mV_END          \
 172         (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
 173 #define AXP803_DCDC5_1140mV_START       0x21
 174 #define AXP803_DCDC5_1140mV_STEPS       35
 175 #define AXP803_DCDC5_1140mV_END         \
 176         (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
 177 #define AXP803_DCDC5_NUM_VOLTAGES       68
 178
 179 #define AXP803_DCDC6_600mV_START        0x00
 180 #define AXP803_DCDC6_600mV_STEPS        50
 181 #define AXP803_DCDC6_600mV_END          \
 182         (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
 183 #define AXP803_DCDC6_1120mV_START       0x33
 184 #define AXP803_DCDC6_1120mV_STEPS       14
 185 #define AXP803_DCDC6_1120mV_END         \
 186         (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
 187 #define AXP803_DCDC6_NUM_VOLTAGES       72
 188
 189 #define AXP803_DLDO2_700mV_START        0x00
 190 #define AXP803_DLDO2_700mV_STEPS        26
 191 #define AXP803_DLDO2_700mV_END          \
 192         (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
 193 #define AXP803_DLDO2_3400mV_START       0x1b
 194 #define AXP803_DLDO2_3400mV_STEPS       4
 195 #define AXP803_DLDO2_3400mV_END         \
 196         (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
 197 #define AXP803_DLDO2_NUM_VOLTAGES       32
 198
 199 #define AXP806_DCDCA_V_CTRL_MASK        GENMASK(6, 0)
 200 #define AXP806_DCDCB_V_CTRL_MASK        GENMASK(4, 0)
 201 #define AXP806_DCDCC_V_CTRL_MASK        GENMASK(6, 0)
 202 #define AXP806_DCDCD_V_CTRL_MASK        GENMASK(5, 0)
 203 #define AXP806_DCDCE_V_CTRL_MASK        GENMASK(4, 0)
 204 #define AXP806_ALDO1_V_CTRL_MASK        GENMASK(4, 0)
 205 #define AXP806_ALDO2_V_CTRL_MASK        GENMASK(4, 0)
 206 #define AXP806_ALDO3_V_CTRL_MASK        GENMASK(4, 0)
 207 #define AXP806_BLDO1_V_CTRL_MASK        GENMASK(3, 0)
 208 #define AXP806_BLDO2_V_CTRL_MASK        GENMASK(3, 0)
 209 #define AXP806_BLDO3_V_CTRL_MASK        GENMASK(3, 0)
 210 #define AXP806_BLDO4_V_CTRL_MASK        GENMASK(3, 0)
 211 #define AXP806_CLDO1_V_CTRL_MASK        GENMASK(4, 0)
 212 #define AXP806_CLDO2_V_CTRL_MASK        GENMASK(4, 0)
 213 #define AXP806_CLDO3_V_CTRL_MASK        GENMASK(4, 0)
 214
 215 #define AXP806_PWR_OUT_DCDCA_MASK       BIT_MASK(0)
 216 #define AXP806_PWR_OUT_DCDCB_MASK       BIT_MASK(1)
 217 #define AXP806_PWR_OUT_DCDCC_MASK       BIT_MASK(2)
 218 #define AXP806_PWR_OUT_DCDCD_MASK       BIT_MASK(3)
 219 #define AXP806_PWR_OUT_DCDCE_MASK       BIT_MASK(4)
 220 #define AXP806_PWR_OUT_ALDO1_MASK       BIT_MASK(5)
 221 #define AXP806_PWR_OUT_ALDO2_MASK       BIT_MASK(6)
 222 #define AXP806_PWR_OUT_ALDO3_MASK       BIT_MASK(7)
 223 #define AXP806_PWR_OUT_BLDO1_MASK       BIT_MASK(0)
 224 #define AXP806_PWR_OUT_BLDO2_MASK       BIT_MASK(1)
 225 #define AXP806_PWR_OUT_BLDO3_MASK       BIT_MASK(2)
 226 #define AXP806_PWR_OUT_BLDO4_MASK       BIT_MASK(3)
 227 #define AXP806_PWR_OUT_CLDO1_MASK       BIT_MASK(4)
 228 #define AXP806_PWR_OUT_CLDO2_MASK       BIT_MASK(5)
 229 #define AXP806_PWR_OUT_CLDO3_MASK       BIT_MASK(6)
 230 #define AXP806_PWR_OUT_SW_MASK          BIT_MASK(7)
 231
 232 #define AXP806_DCDCAB_POLYPHASE_DUAL    0x40
 233 #define AXP806_DCDCABC_POLYPHASE_TRI    0x80
 234 #define AXP806_DCDCABC_POLYPHASE_MASK   GENMASK(7, 6)
 235
 236 #define AXP806_DCDCDE_POLYPHASE_DUAL    BIT(5)
 237
 238 #define AXP806_DCDCA_600mV_START        0x00
 239 #define AXP806_DCDCA_600mV_STEPS        50
 240 #define AXP806_DCDCA_600mV_END          \
 241         (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
 242 #define AXP806_DCDCA_1120mV_START       0x33
 243 #define AXP806_DCDCA_1120mV_STEPS       14
 244 #define AXP806_DCDCA_1120mV_END         \
 245         (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
 246 #define AXP806_DCDCA_NUM_VOLTAGES       72
 247
 248 #define AXP806_DCDCD_600mV_START        0x00
 249 #define AXP806_DCDCD_600mV_STEPS        45
 250 #define AXP806_DCDCD_600mV_END          \
 251         (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
 252 #define AXP806_DCDCD_1600mV_START       0x2e
 253 #define AXP806_DCDCD_1600mV_STEPS       17
 254 #define AXP806_DCDCD_1600mV_END         \
 255         (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
 256 #define AXP806_DCDCD_NUM_VOLTAGES       64
 257
 258 #define AXP809_DCDC4_600mV_START        0x00
 259 #define AXP809_DCDC4_600mV_STEPS        47
 260 #define AXP809_DCDC4_600mV_END          \
 261         (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
 262 #define AXP809_DCDC4_1800mV_START       0x30
 263 #define AXP809_DCDC4_1800mV_STEPS       8
 264 #define AXP809_DCDC4_1800mV_END         \
 265         (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
 266 #define AXP809_DCDC4_NUM_VOLTAGES       57
 267
 268 #define AXP813_DCDC7_V_OUT_MASK         GENMASK(6, 0)
 269
 270 #define AXP813_PWR_OUT_DCDC7_MASK       BIT_MASK(6)
 271
 272 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,    \
 273                     _vmask, _ereg, _emask, _enable_val, _disable_val)           \
 274         [_family##_##_id] = {                                                   \
 275                 .name           = (_match),                                     \
 276                 .supply_name    = (_supply),                                    \
 277                 .of_match       = of_match_ptr(_match),                         \
 278                 .regulators_node = of_match_ptr("regulators"),                  \
 279                 .type           = REGULATOR_VOLTAGE,                            \
 280                 .id             = _family##_##_id,                              \
 281                 .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
 282                 .owner          = THIS_MODULE,                                  \
 283                 .min_uV         = (_min) * 1000,                                \
 284                 .uV_step        = (_step) * 1000,                               \
 285                 .vsel_reg       = (_vreg),                                      \
 286                 .vsel_mask      = (_vmask),                                     \
 287                 .enable_reg     = (_ereg),                                      \
 288                 .enable_mask    = (_emask),                                     \
 289                 .enable_val     = (_enable_val),                                \
 290                 .disable_val    = (_disable_val),                               \
 291                 .ops            = &axp20x_ops,                                  \
 292         }
 293
 294 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,       \
 295                  _vmask, _ereg, _emask)                                         \
 296         [_family##_##_id] = {                                                   \
 297                 .name           = (_match),                                     \
 298                 .supply_name    = (_supply),                                    \
 299                 .of_match       = of_match_ptr(_match),                         \
 300                 .regulators_node = of_match_ptr("regulators"),                  \
 301                 .type           = REGULATOR_VOLTAGE,                            \
 302                 .id             = _family##_##_id,                              \
 303                 .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
 304                 .owner          = THIS_MODULE,                                  \
 305                 .min_uV         = (_min) * 1000,                                \
 306                 .uV_step        = (_step) * 1000,                               \
 307                 .vsel_reg       = (_vreg),                                      \
 308                 .vsel_mask      = (_vmask),                                     \
 309                 .enable_reg     = (_ereg),                                      \
 310                 .enable_mask    = (_emask),                                     \
 311                 .ops            = &axp20x_ops,                                  \
 312         }
 313
 314 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask)               \
 315         [_family##_##_id] = {                                                   \
 316                 .name           = (_match),                                     \
 317                 .supply_name    = (_supply),                                    \
 318                 .of_match       = of_match_ptr(_match),                         \
 319                 .regulators_node = of_match_ptr("regulators"),                  \
 320                 .type           = REGULATOR_VOLTAGE,                            \
 321                 .id             = _family##_##_id,                              \
 322                 .owner          = THIS_MODULE,                                  \
 323                 .enable_reg     = (_ereg),                                      \
 324                 .enable_mask    = (_emask),                                     \
 325                 .ops            = &axp20x_ops_sw,                               \
 326         }
 327
 328 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)                    \
 329         [_family##_##_id] = {                                                   \
 330                 .name           = (_match),                                     \
 331                 .supply_name    = (_supply),                                    \
 332                 .of_match       = of_match_ptr(_match),                         \
 333                 .regulators_node = of_match_ptr("regulators"),                  \
 334                 .type           = REGULATOR_VOLTAGE,                            \
 335                 .id             = _family##_##_id,                              \
 336                 .n_voltages     = 1,                                            \
 337                 .owner          = THIS_MODULE,                                  \
 338                 .min_uV         = (_volt) * 1000,                               \
 339                 .ops            = &axp20x_ops_fixed                             \
 340         }
 341
 342 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages,    \
 343                         _vreg, _vmask, _ereg, _emask)                           \
 344         [_family##_##_id] = {                                                   \
 345                 .name           = (_match),                                     \
 346                 .supply_name    = (_supply),                                    \
 347                 .of_match       = of_match_ptr(_match),                         \
 348                 .regulators_node = of_match_ptr("regulators"),                  \
 349                 .type           = REGULATOR_VOLTAGE,                            \
 350                 .id             = _family##_##_id,                              \
 351                 .n_voltages     = (_n_voltages),                                \
 352                 .owner          = THIS_MODULE,                                  \
 353                 .vsel_reg       = (_vreg),                                      \
 354                 .vsel_mask      = (_vmask),                                     \
 355                 .enable_reg     = (_ereg),                                      \
 356                 .enable_mask    = (_emask),                                     \
 357                 .linear_ranges  = (_ranges),                                    \
 358                 .n_linear_ranges = ARRAY_SIZE(_ranges),                         \
 359                 .ops            = &axp20x_ops_range,                            \
 360         }
 361
 362 static const int axp209_dcdc2_ldo3_slew_rates[] = {
 363         1600,
 364          800,
 365 };
 366
 367 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
 368 {
 369         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 370         const struct regulator_desc *desc;
 371         u8 reg, mask, enable, cfg = 0xff;
 372         const int *slew_rates;
 373         int rate_count = 0;
 374
 375         if (!rdev)
 376                 return -EINVAL;
 377
 378         desc = rdev->desc;
 379
 380         switch (axp20x->variant) {
 381         case AXP209_ID:
 382                 if (desc->id == AXP20X_DCDC2) {
 383                         slew_rates = axp209_dcdc2_ldo3_slew_rates;
 384                         rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 385                         reg = AXP20X_DCDC2_LDO3_V_RAMP;
 386                         mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
 387                                AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
 388                         enable = (ramp > 0) ?
 389                                  AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN :
 390                                  !AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN;
 391                         break;
 392                 }
 393
 394                 if (desc->id == AXP20X_LDO3) {
 395                         slew_rates = axp209_dcdc2_ldo3_slew_rates;
 396                         rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 397                         reg = AXP20X_DCDC2_LDO3_V_RAMP;
 398                         mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
 399                                AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
 400                         enable = (ramp > 0) ?
 401                                  AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN :
 402                                  !AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN;
 403                         break;
 404                 }
 405
 406                 if (rate_count > 0)
 407                         break;
 408
 409                 /* fall through */
 410         default:
 411                 /* Not supported for this regulator */
 412                 return -ENOTSUPP;
 413         }
 414
 415         if (ramp == 0) {
 416                 cfg = enable;
 417         } else {
 418                 int i;
 419
 420                 for (i = 0; i < rate_count; i++) {
 421                         if (ramp <= slew_rates[i])
 422                                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
 423                         else
 424                                 break;
 425                 }
 426
 427                 if (cfg == 0xff) {
 428                         dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
 429                         return -EINVAL;
 430                 }
 431
 432                 cfg |= enable;
 433         }
 434
 435         return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
 436 }
 437
 438 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
 439 {
 440         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 441         const struct regulator_desc *desc;
 442
 443         if (!rdev)
 444                 return -EINVAL;
 445
 446         desc = rdev->desc;
 447
 448         switch (axp20x->variant) {
 449         case AXP209_ID:
 450                 if ((desc->id == AXP20X_LDO3) &&
 451                     rdev->constraints && rdev->constraints->soft_start) {
 452                         int v_out;
 453                         int ret;
 454
 455                         /*
 456                          * On some boards, the LDO3 can be overloaded when
 457                          * turning on, causing the entire PMIC to shutdown
 458                          * without warning. Turning it on at the minimal voltage
 459                          * and then setting the voltage to the requested value
 460                          * works reliably.
 461                          */
 462                         if (regulator_is_enabled_regmap(rdev))
 463                                 break;
 464
 465                         v_out = regulator_get_voltage_sel_regmap(rdev);
 466                         if (v_out < 0)
 467                                 return v_out;
 468
 469                         if (v_out == 0)
 470                                 break;
 471
 472                         ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
 473                         /*
 474                          * A small pause is needed between
 475                          * setting the voltage and enabling the LDO to give the
 476                          * internal state machine time to process the request.
 477                          */
 478                         usleep_range(1000, 5000);
 479                         ret |= regulator_enable_regmap(rdev);
 480                         ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
 481
 482                         return ret;
 483                 }
 484                 break;
 485         default:
 486                 /* No quirks */
 487                 break;
 488         }
 489
 490         return regulator_enable_regmap(rdev);
 491 };
 492
 493 static const struct regulator_ops axp20x_ops_fixed = {
 494         .list_voltage           = regulator_list_voltage_linear,
 495 };
 496
 497 static const struct regulator_ops axp20x_ops_range = {
 498         .set_voltage_sel        = regulator_set_voltage_sel_regmap,
 499         .get_voltage_sel        = regulator_get_voltage_sel_regmap,
 500         .list_voltage           = regulator_list_voltage_linear_range,
 501         .enable                 = regulator_enable_regmap,
 502         .disable                = regulator_disable_regmap,
 503         .is_enabled             = regulator_is_enabled_regmap,
 504 };
 505
 506 static const struct regulator_ops axp20x_ops = {
 507         .set_voltage_sel        = regulator_set_voltage_sel_regmap,
 508         .get_voltage_sel        = regulator_get_voltage_sel_regmap,
 509         .list_voltage           = regulator_list_voltage_linear,
 510         .enable                 = axp20x_regulator_enable_regmap,
 511         .disable                = regulator_disable_regmap,
 512         .is_enabled             = regulator_is_enabled_regmap,
 513         .set_ramp_delay         = axp20x_set_ramp_delay,
 514 };
 515
 516 static const struct regulator_ops axp20x_ops_sw = {
 517         .enable                 = regulator_enable_regmap,
 518         .disable                = regulator_disable_regmap,
 519         .is_enabled             = regulator_is_enabled_regmap,
 520 };
 521
 522 static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
 523         REGULATOR_LINEAR_RANGE(1250000,
 524                                AXP20X_LDO4_V_OUT_1250mV_START,
 525                                AXP20X_LDO4_V_OUT_1250mV_END,
 526                                0),
 527         REGULATOR_LINEAR_RANGE(1300000,
 528                                AXP20X_LDO4_V_OUT_1300mV_START,
 529                                AXP20X_LDO4_V_OUT_1300mV_END,
 530                                100000),
 531         REGULATOR_LINEAR_RANGE(2500000,
 532                                AXP20X_LDO4_V_OUT_2500mV_START,
 533                                AXP20X_LDO4_V_OUT_2500mV_END,
 534                                0),
 535         REGULATOR_LINEAR_RANGE(2700000,
 536                                AXP20X_LDO4_V_OUT_2700mV_START,
 537                                AXP20X_LDO4_V_OUT_2700mV_END,
 538                                100000),
 539         REGULATOR_LINEAR_RANGE(3000000,
 540                                AXP20X_LDO4_V_OUT_3000mV_START,
 541                                AXP20X_LDO4_V_OUT_3000mV_END,
 542                                100000),
 543 };
 544
 545 static const struct regulator_desc axp20x_regulators[] = {
 546         AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
 547                  AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
 548                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
 549         AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
 550                  AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
 551                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
 552         AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
 553         AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
 554                  AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK,
 555                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
 556         AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
 557                  AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
 558                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
 559         AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
 560                         axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
 561                         AXP20X_LDO24_V_OUT, AXP20X_LDO24_V_OUT_MASK,
 562                         AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
 563         AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
 564                     AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
 565                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 566                     AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
 567 };
 568
 569 static const struct regulator_desc axp22x_regulators[] = {
 570         AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 571                  AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 572                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 573         AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 574                  AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 575                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 576         AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 577                  AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 578                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 579         AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
 580                  AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT,
 581                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 582         AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 583                  AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 584                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 585         /* secondary switchable output of DCDC1 */
 586         AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
 587                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 588         /* LDO regulator internally chained to DCDC5 */
 589         AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 590                  AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 591                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 592         AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 593                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 594                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 595         AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 596                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 597                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 598         AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 599                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 600                  AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
 601         AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 602                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 603                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 604         AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 605                  AXP22X_DLDO2_V_OUT, AXP22X_PWR_OUT_DLDO2_MASK,
 606                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 607         AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 608                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 609                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 610         AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 611                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 612                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 613         AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 614                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 615                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 616         AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 617                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 618                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 619         AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 620                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 621                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 622         /* Note the datasheet only guarantees reliable operation up to
 623          * 3.3V, this needs to be enforced via dts provided constraints */
 624         AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 625                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 626                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 627                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 628         /* Note the datasheet only guarantees reliable operation up to
 629          * 3.3V, this needs to be enforced via dts provided constraints */
 630         AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 631                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 632                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 633                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 634         AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
 635 };
 636
 637 static const struct regulator_desc axp22x_drivevbus_regulator = {
 638         .name           = "drivevbus",
 639         .supply_name    = "drivevbus",
 640         .of_match       = of_match_ptr("drivevbus"),
 641         .regulators_node = of_match_ptr("regulators"),
 642         .type           = REGULATOR_VOLTAGE,
 643         .owner          = THIS_MODULE,
 644         .enable_reg     = AXP20X_VBUS_IPSOUT_MGMT,
 645         .enable_mask    = AXP20X_VBUS_IPSOUT_MGMT_MASK,
 646         .ops            = &axp20x_ops_sw,
 647 };
 648
 649 /* DCDC ranges shared with AXP813 */
 650 static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
 651         REGULATOR_LINEAR_RANGE(500000,
 652                                AXP803_DCDC234_500mV_START,
 653                                AXP803_DCDC234_500mV_END,
 654                                10000),
 655         REGULATOR_LINEAR_RANGE(1220000,
 656                                AXP803_DCDC234_1220mV_START,
 657                                AXP803_DCDC234_1220mV_END,
 658                                20000),
 659 };
 660
 661 static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
 662         REGULATOR_LINEAR_RANGE(800000,
 663                                AXP803_DCDC5_800mV_START,
 664                                AXP803_DCDC5_800mV_END,
 665                                10000),
 666         REGULATOR_LINEAR_RANGE(1140000,
 667                                AXP803_DCDC5_1140mV_START,
 668                                AXP803_DCDC5_1140mV_END,
 669                                20000),
 670 };
 671
 672 static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
 673         REGULATOR_LINEAR_RANGE(600000,
 674                                AXP803_DCDC6_600mV_START,
 675                                AXP803_DCDC6_600mV_END,
 676                                10000),
 677         REGULATOR_LINEAR_RANGE(1120000,
 678                                AXP803_DCDC6_1120mV_START,
 679                                AXP803_DCDC6_1120mV_END,
 680                                20000),
 681 };
 682
 683 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
 684 static const struct regulator_linear_range axp803_dldo2_ranges[] = {
 685         REGULATOR_LINEAR_RANGE(700000,
 686                                AXP803_DLDO2_700mV_START,
 687                                AXP803_DLDO2_700mV_END,
 688                                100000),
 689         REGULATOR_LINEAR_RANGE(3400000,
 690                                AXP803_DLDO2_3400mV_START,
 691                                AXP803_DLDO2_3400mV_END,
 692                                200000),
 693 };
 694
 695 static const struct regulator_desc axp803_regulators[] = {
 696         AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 697                  AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 698                  AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 699         AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
 700                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 701                         AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 702                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 703         AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
 704                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 705                         AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 706                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 707         AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
 708                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 709                         AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 710                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 711         AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
 712                         axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 713                         AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 714                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 715         AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
 716                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 717                         AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 718                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 719         /* secondary switchable output of DCDC1 */
 720         AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
 721                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 722         AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 723                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 724                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 725         AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 726                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 727                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 728         AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 729                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 730                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 731         AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 732                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 733                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 734         AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
 735                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 736                         AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 737                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 738         AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 739                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 740                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 741         AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 742                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 743                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 744         AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 745                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 746                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 747         AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 748                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 749                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 750         AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 751                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 752                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 753         AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 754                  AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 755                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 756         AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 757                  AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 758                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 759         AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
 760                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 761                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 762                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 763         AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
 764                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 765                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 766                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 767         AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
 768 };
 769
 770 static const struct regulator_linear_range axp806_dcdca_ranges[] = {
 771         REGULATOR_LINEAR_RANGE(600000,
 772                                AXP806_DCDCA_600mV_START,
 773                                AXP806_DCDCA_600mV_END,
 774                                10000),
 775         REGULATOR_LINEAR_RANGE(1120000,
 776                                AXP806_DCDCA_1120mV_START,
 777                                AXP806_DCDCA_1120mV_END,
 778                                20000),
 779 };
 780
 781 static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
 782         REGULATOR_LINEAR_RANGE(600000,
 783                                AXP806_DCDCD_600mV_START,
 784                                AXP806_DCDCD_600mV_END,
 785                                20000),
 786         REGULATOR_LINEAR_RANGE(1600000,
 787                                AXP806_DCDCD_600mV_START,
 788                                AXP806_DCDCD_600mV_END,
 789                                100000),
 790 };
 791
 792 static const struct regulator_desc axp806_regulators[] = {
 793         AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
 794                         axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 795                         AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
 796                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
 797         AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
 798                  AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL,
 799                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
 800         AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
 801                         axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 802                         AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
 803                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
 804         AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
 805                         axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
 806                         AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
 807                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
 808         AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
 809                  AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
 810                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
 811         AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 812                  AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
 813                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
 814         AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
 815                  AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
 816                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
 817         AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 818                  AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
 819                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
 820         AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
 821                  AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
 822                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
 823         AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
 824                  AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL,
 825                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
 826         AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
 827                  AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
 828                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
 829         AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
 830                  AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
 831                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
 832         AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
 833                  AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
 834                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
 835         AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
 836                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 837                         AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
 838                         AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
 839         AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
 840                  AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
 841                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
 842         AXP_DESC_SW(AXP806, SW, "sw", "swin",
 843                     AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
 844 };
 845
 846 static const struct regulator_linear_range axp809_dcdc4_ranges[] = {
 847         REGULATOR_LINEAR_RANGE(600000,
 848                                AXP809_DCDC4_600mV_START,
 849                                AXP809_DCDC4_600mV_END,
 850                                20000),
 851         REGULATOR_LINEAR_RANGE(1800000,
 852                                AXP809_DCDC4_1800mV_START,
 853                                AXP809_DCDC4_1800mV_END,
 854                                100000),
 855 };
 856
 857 static const struct regulator_desc axp809_regulators[] = {
 858         AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 859                  AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 860                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 861         AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 862                  AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 863                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 864         AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 865                  AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 866                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 867         AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
 868                         axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
 869                         AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
 870                         AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 871         AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 872                  AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 873                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 874         /* secondary switchable output of DCDC1 */
 875         AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
 876                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 877         /* LDO regulator internally chained to DCDC5 */
 878         AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 879                  AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 880                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 881         AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 882                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 883                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 884         AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 885                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 886                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 887         AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 888                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 889                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
 890         AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
 891                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 892                         AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 893                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 894         AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 895                  AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 896                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 897         AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 898                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 899                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 900         AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 901                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 902                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 903         AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 904                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 905                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 906         /*
 907          * Note the datasheet only guarantees reliable operation up to
 908          * 3.3V, this needs to be enforced via dts provided constraints
 909          */
 910         AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 911                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 912                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 913                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 914         /*
 915          * Note the datasheet only guarantees reliable operation up to
 916          * 3.3V, this needs to be enforced via dts provided constraints
 917          */
 918         AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 919                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 920                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 921                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 922         AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
 923         AXP_DESC_SW(AXP809, SW, "sw", "swin",
 924                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
 925 };
 926
 927 static const struct regulator_desc axp813_regulators[] = {
 928         AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 929                  AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 930                  AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 931         AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
 932                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 933                         AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 934                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 935         AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
 936                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 937                         AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 938                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 939         AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
 940                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 941                         AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 942                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 943         AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
 944                         axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 945                         AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 946                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 947         AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
 948                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 949                         AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 950                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 951         AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
 952                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 953                         AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
 954                         AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
 955         AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 956                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 957                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 958         AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 959                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT,
 960                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 961         AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 962                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 963                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 964         AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 965                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 966                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 967         AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
 968                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 969                         AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT,
 970                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 971         AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 972                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 973                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 974         AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 975                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 976                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 977         AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 978                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 979                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 980         AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 981                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 982                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 983         AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 984                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT,
 985                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 986         /* to do / check ... */
 987         AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 988                  AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 989                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 990         AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 991                  AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 992                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 993         /*
 994          * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
 995          *
 996          * This means FLDO3 effectively switches supplies at runtime,
 997          * something the regulator subsystem does not support.
 998          */
 999         AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
1000         AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
1001                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
1002                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
1003                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1004         AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
1005                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1006                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1007                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1008         AXP_DESC_SW(AXP813, SW, "sw", "swin",
1009                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1010 };
1011
1012 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1013 {
1014         struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1015         unsigned int reg = AXP20X_DCDC_FREQ;
1016         u32 min, max, def, step;
1017
1018         switch (axp20x->variant) {
1019         case AXP202_ID:
1020         case AXP209_ID:
1021                 min = 750;
1022                 max = 1875;
1023                 def = 1500;
1024                 step = 75;
1025                 break;
1026         case AXP803_ID:
1027         case AXP813_ID:
1028                 /*
1029                  * AXP803/AXP813 DCDC work frequency setting has the same
1030                  * range and step as AXP22X, but at a different register.
1031                  * (See include/linux/mfd/axp20x.h)
1032                  */
1033                 reg = AXP803_DCDC_FREQ_CTRL;
1034                 /* Fall through to the check below.*/
1035         case AXP806_ID:
1036                 /*
1037                  * AXP806 also have DCDC work frequency setting register at a
1038                  * different position.
1039                  */
1040                 if (axp20x->variant == AXP806_ID)
1041                         reg = AXP806_DCDC_FREQ_CTRL;
1042                 /* Fall through */
1043         case AXP221_ID:
1044         case AXP223_ID:
1045         case AXP809_ID:
1046                 min = 1800;
1047                 max = 4050;
1048                 def = 3000;
1049                 step = 150;
1050                 break;
1051         default:
1052                 dev_err(&pdev->dev,
1053                         "Setting DCDC frequency for unsupported AXP variant\n");
1054                 return -EINVAL;
1055         }
1056
1057         if (dcdcfreq == 0)
1058                 dcdcfreq = def;
1059
1060         if (dcdcfreq < min) {
1061                 dcdcfreq = min;
1062                 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1063                          min);
1064         }
1065
1066         if (dcdcfreq > max) {
1067                 dcdcfreq = max;
1068                 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1069                          max);
1070         }
1071
1072         dcdcfreq = (dcdcfreq - min) / step;
1073
1074         return regmap_update_bits(axp20x->regmap, reg,
1075                                   AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1076 }
1077
1078 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1079 {
1080         struct device_node *np, *regulators;
1081         int ret;
1082         u32 dcdcfreq = 0;
1083
1084         np = of_node_get(pdev->dev.parent->of_node);
1085         if (!np)
1086                 return 0;
1087
1088         regulators = of_get_child_by_name(np, "regulators");
1089         if (!regulators) {
1090                 dev_warn(&pdev->dev, "regulators node not found\n");
1091         } else {
1092                 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1093                 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1094                 if (ret < 0) {
1095                         dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1096                         return ret;
1097                 }
1098
1099                 of_node_put(regulators);
1100         }
1101
1102         return 0;
1103 }
1104
1105 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1106 {
1107         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1108         unsigned int reg = AXP20X_DCDC_MODE;
1109         unsigned int mask;
1110
1111         switch (axp20x->variant) {
1112         case AXP202_ID:
1113         case AXP209_ID:
1114                 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1115                         return -EINVAL;
1116
1117                 mask = AXP20X_WORKMODE_DCDC2_MASK;
1118                 if (id == AXP20X_DCDC3)
1119                         mask = AXP20X_WORKMODE_DCDC3_MASK;
1120
1121                 workmode <<= ffs(mask) - 1;
1122                 break;
1123
1124         case AXP806_ID:
1125                 reg = AXP806_DCDC_MODE_CTRL2;
1126                 /*
1127                  * AXP806 DCDC regulator IDs have the same range as AXP22X.
1128                  * Fall through to the check below.
1129                  * (See include/linux/mfd/axp20x.h)
1130                  */
1131         case AXP221_ID:
1132         case AXP223_ID:
1133         case AXP809_ID:
1134                 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1135                         return -EINVAL;
1136
1137                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1138                 workmode <<= id - AXP22X_DCDC1;
1139                 break;
1140
1141         case AXP803_ID:
1142                 if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1143                         return -EINVAL;
1144
1145                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1146                 workmode <<= id - AXP803_DCDC1;
1147                 break;
1148
1149         case AXP813_ID:
1150                 if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1151                         return -EINVAL;
1152
1153                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1154                 workmode <<= id - AXP813_DCDC1;
1155                 break;
1156
1157         default:
1158                 /* should not happen */
1159                 WARN_ON(1);
1160                 return -EINVAL;
1161         }
1162
1163         return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1164 }
1165
1166 /*
1167  * This function checks whether a regulator is part of a poly-phase
1168  * output setup based on the registers settings. Returns true if it is.
1169  */
1170 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1171 {
1172         u32 reg = 0;
1173
1174         /*
1175          * Currently in our supported AXP variants, only AXP803, AXP806,
1176          * and AXP813 have polyphase regulators.
1177          */
1178         switch (axp20x->variant) {
1179         case AXP803_ID:
1180         case AXP813_ID:
1181                 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
1182
1183                 switch (id) {
1184                 case AXP803_DCDC3:
1185                         return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1186                 case AXP803_DCDC6:
1187                         return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1188                 }
1189                 break;
1190
1191         case AXP806_ID:
1192                 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
1193
1194                 switch (id) {
1195                 case AXP806_DCDCB:
1196                         return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1197                                 AXP806_DCDCAB_POLYPHASE_DUAL) ||
1198                                 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1199                                 AXP806_DCDCABC_POLYPHASE_TRI));
1200                 case AXP806_DCDCC:
1201                         return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1202                                 AXP806_DCDCABC_POLYPHASE_TRI);
1203                 case AXP806_DCDCE:
1204                         return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1205                 }
1206                 break;
1207
1208         default:
1209                 return false;
1210         }
1211
1212         return false;
1213 }
1214
1215 static int axp20x_regulator_probe(struct platform_device *pdev)
1216 {
1217         struct regulator_dev *rdev;
1218         struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1219         const struct regulator_desc *regulators;
1220         struct regulator_config config = {
1221                 .dev = pdev->dev.parent,
1222                 .regmap = axp20x->regmap,
1223                 .driver_data = axp20x,
1224         };
1225         int ret, i, nregulators;
1226         u32 workmode;
1227         const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1228         const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1229         bool drivevbus = false;
1230
1231         switch (axp20x->variant) {
1232         case AXP202_ID:
1233         case AXP209_ID:
1234                 regulators = axp20x_regulators;
1235                 nregulators = AXP20X_REG_ID_MAX;
1236                 break;
1237         case AXP221_ID:
1238         case AXP223_ID:
1239                 regulators = axp22x_regulators;
1240                 nregulators = AXP22X_REG_ID_MAX;
1241                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1242                                                   "x-powers,drive-vbus-en");
1243                 break;
1244         case AXP803_ID:
1245                 regulators = axp803_regulators;
1246                 nregulators = AXP803_REG_ID_MAX;
1247                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1248                                                   "x-powers,drive-vbus-en");
1249                 break;
1250         case AXP806_ID:
1251                 regulators = axp806_regulators;
1252                 nregulators = AXP806_REG_ID_MAX;
1253                 break;
1254         case AXP809_ID:
1255                 regulators = axp809_regulators;
1256                 nregulators = AXP809_REG_ID_MAX;
1257                 break;
1258         case AXP813_ID:
1259                 regulators = axp813_regulators;
1260                 nregulators = AXP813_REG_ID_MAX;
1261                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1262                                                   "x-powers,drive-vbus-en");
1263                 break;
1264         default:
1265                 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1266                         axp20x->variant);
1267                 return -EINVAL;
1268         }
1269
1270         /* This only sets the dcdc freq. Ignore any errors */
1271         axp20x_regulator_parse_dt(pdev);
1272
1273         for (i = 0; i < nregulators; i++) {
1274                 const struct regulator_desc *desc = &regulators[i];
1275                 struct regulator_desc *new_desc;
1276
1277                 /*
1278                  * If this regulator is a slave in a poly-phase setup,
1279                  * skip it, as its controls are bound to the master
1280                  * regulator and won't work.
1281                  */
1282                 if (axp20x_is_polyphase_slave(axp20x, i))
1283                         continue;
1284
1285                 /* Support for AXP813's FLDO3 is not implemented */
1286                 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1287                         continue;
1288
1289                 /*
1290                  * Regulators DC1SW and DC5LDO are connected internally,
1291                  * so we have to handle their supply names separately.
1292                  *
1293                  * We always register the regulators in proper sequence,
1294                  * so the supply names are correctly read. See the last
1295                  * part of this loop to see where we save the DT defined
1296                  * name.
1297                  */
1298                 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1299                     (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1300                     (regulators == axp809_regulators && i == AXP809_DC1SW)) {
1301                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1302                                                 GFP_KERNEL);
1303                         if (!new_desc)
1304                                 return -ENOMEM;
1305
1306                         *new_desc = regulators[i];
1307                         new_desc->supply_name = dcdc1_name;
1308                         desc = new_desc;
1309                 }
1310
1311                 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1312                     (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
1313                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1314                                                 GFP_KERNEL);
1315                         if (!new_desc)
1316                                 return -ENOMEM;
1317
1318                         *new_desc = regulators[i];
1319                         new_desc->supply_name = dcdc5_name;
1320                         desc = new_desc;
1321                 }
1322
1323                 rdev = devm_regulator_register(&pdev->dev, desc, &config);
1324                 if (IS_ERR(rdev)) {
1325                         dev_err(&pdev->dev, "Failed to register %s\n",
1326                                 regulators[i].name);
1327
1328                         return PTR_ERR(rdev);
1329                 }
1330
1331                 ret = of_property_read_u32(rdev->dev.of_node,
1332                                            "x-powers,dcdc-workmode",
1333                                            &workmode);
1334                 if (!ret) {
1335                         if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1336                                 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1337                                         rdev->desc->name);
1338                 }
1339
1340                 /*
1341                  * Save AXP22X DCDC1 / DCDC5 regulator names for later.
1342                  */
1343                 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1344                     (regulators == axp809_regulators && i == AXP809_DCDC1))
1345                         of_property_read_string(rdev->dev.of_node,
1346                                                 "regulator-name",
1347                                                 &dcdc1_name);
1348
1349                 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1350                     (regulators == axp809_regulators && i == AXP809_DCDC5))
1351                         of_property_read_string(rdev->dev.of_node,
1352                                                 "regulator-name",
1353                                                 &dcdc5_name);
1354         }
1355
1356         if (drivevbus) {
1357                 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1358                 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1359                                    AXP22X_MISC_N_VBUSEN_FUNC, 0);
1360                 rdev = devm_regulator_register(&pdev->dev,
1361                                                &axp22x_drivevbus_regulator,
1362                                                &config);
1363                 if (IS_ERR(rdev)) {
1364                         dev_err(&pdev->dev, "Failed to register drivevbus\n");
1365                         return PTR_ERR(rdev);
1366                 }
1367         }
1368
1369         return 0;
1370 }
1371
1372 static struct platform_driver axp20x_regulator_driver = {
1373         .probe  = axp20x_regulator_probe,
1374         .driver = {
1375                 .name           = "axp20x-regulator",
1376         },
1377 };
1378
1379 module_platform_driver(axp20x_regulator_driver);
1380
1381 MODULE_LICENSE("GPL v2");
1382 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1383 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1384 MODULE_ALIAS("platform:axp20x-regulator");