drivers/pwm/pwm-sun4i.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Allwinner sun4i Pulse Width Modulation Controller
   4  *
   5  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
   6  *
   7  * Limitations:
   8  * - When outputing the source clock directly, the PWM logic will be bypassed
   9  *   and the currently running period is not guaranteed to be completed
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pwm.h>
  23 #include <linux/reset.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/time.h>
  27
  28 #define PWM_CTRL_REG            0x0
  29
  30 #define PWM_CH_PRD_BASE         0x4
  31 #define PWM_CH_PRD_OFFSET       0x4
  32 #define PWM_CH_PRD(ch)          (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
  33
  34 #define PWMCH_OFFSET            15
  35 #define PWM_PRESCAL_MASK        GENMASK(3, 0)
  36 #define PWM_PRESCAL_OFF         0
  37 #define PWM_EN                  BIT(4)
  38 #define PWM_ACT_STATE           BIT(5)
  39 #define PWM_CLK_GATING          BIT(6)
  40 #define PWM_MODE                BIT(7)
  41 #define PWM_PULSE               BIT(8)
  42 #define PWM_BYPASS              BIT(9)
  43
  44 #define PWM_RDY_BASE            28
  45 #define PWM_RDY_OFFSET          1
  46 #define PWM_RDY(ch)             BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
  47
  48 #define PWM_PRD(prd)            (((prd) - 1) << 16)
  49 #define PWM_PRD_MASK            GENMASK(15, 0)
  50
  51 #define PWM_DTY_MASK            GENMASK(15, 0)
  52
  53 #define PWM_REG_PRD(reg)        ((((reg) >> 16) & PWM_PRD_MASK) + 1)
  54 #define PWM_REG_DTY(reg)        ((reg) & PWM_DTY_MASK)
  55 #define PWM_REG_PRESCAL(reg, chan)      (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
  56
  57 #define BIT_CH(bit, chan)       ((bit) << ((chan) * PWMCH_OFFSET))
  58
  59 static const u32 prescaler_table[] = {
  60         120,
  61         180,
  62         240,
  63         360,
  64         480,
  65         0,
  66         0,
  67         0,
  68         12000,
  69         24000,
  70         36000,
  71         48000,
  72         72000,
  73         0,
  74         0,
  75         0, /* Actually 1 but tested separately */
  76 };
  77
  78 struct sun4i_pwm_data {
  79         bool has_prescaler_bypass;
  80         bool has_direct_mod_clk_output;
  81         unsigned int npwm;
  82 };
  83
  84 struct sun4i_pwm_chip {
  85         struct pwm_chip chip;
  86         struct clk *bus_clk;
  87         struct clk *clk;
  88         struct reset_control *rst;
  89         void __iomem *base;
  90         spinlock_t ctrl_lock;
  91         const struct sun4i_pwm_data *data;
  92         unsigned long next_period[2];
  93         bool needs_delay[2];
  94 };
  95
  96 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
  97 {
  98         return container_of(chip, struct sun4i_pwm_chip, chip);
  99 }
 100
 101 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
 102                                   unsigned long offset)
 103 {
 104         return readl(chip->base + offset);
 105 }
 106
 107 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
 108                                     u32 val, unsigned long offset)
 109 {
 110         writel(val, chip->base + offset);
 111 }
 112
 113 static void sun4i_pwm_get_state(struct pwm_chip *chip,
 114                                 struct pwm_device *pwm,
 115                                 struct pwm_state *state)
 116 {
 117         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 118         u64 clk_rate, tmp;
 119         u32 val;
 120         unsigned int prescaler;
 121
 122         clk_rate = clk_get_rate(sun4i_pwm->clk);
 123
 124         val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 125
 126         /*
 127          * PWM chapter in H6 manual has a diagram which explains that if bypass
 128          * bit is set, no other setting has any meaning. Even more, experiment
 129          * proved that also enable bit is ignored in this case.
 130          */
 131         if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
 132             sun4i_pwm->data->has_direct_mod_clk_output) {
 133                 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
 134                 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
 135                 state->polarity = PWM_POLARITY_NORMAL;
 136                 state->enabled = true;
 137                 return;
 138         }
 139
 140         if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
 141             sun4i_pwm->data->has_prescaler_bypass)
 142                 prescaler = 1;
 143         else
 144                 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
 145
 146         if (prescaler == 0)
 147                 return;
 148
 149         if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
 150                 state->polarity = PWM_POLARITY_NORMAL;
 151         else
 152                 state->polarity = PWM_POLARITY_INVERSED;
 153
 154         if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
 155             BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
 156                 state->enabled = true;
 157         else
 158                 state->enabled = false;
 159
 160         val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
 161
 162         tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
 163         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 164
 165         tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
 166         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 167 }
 168
 169 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
 170                                const struct pwm_state *state,
 171                                u32 *dty, u32 *prd, unsigned int *prsclr,
 172                                bool *bypass)
 173 {
 174         u64 clk_rate, div = 0;
 175         unsigned int pval, prescaler = 0;
 176
 177         clk_rate = clk_get_rate(sun4i_pwm->clk);
 178
 179         *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
 180                   state->enabled &&
 181                   (state->period * clk_rate >= NSEC_PER_SEC) &&
 182                   (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
 183                   (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
 184
 185         /* Skip calculation of other parameters if we bypass them */
 186         if (*bypass)
 187                 return 0;
 188
 189         if (sun4i_pwm->data->has_prescaler_bypass) {
 190                 /* First, test without any prescaler when available */
 191                 prescaler = PWM_PRESCAL_MASK;
 192                 /*
 193                  * When not using any prescaler, the clock period in nanoseconds
 194                  * is not an integer so round it half up instead of
 195                  * truncating to get less surprising values.
 196                  */
 197                 div = clk_rate * state->period + NSEC_PER_SEC / 2;
 198                 do_div(div, NSEC_PER_SEC);
 199                 if (div - 1 > PWM_PRD_MASK)
 200                         prescaler = 0;
 201         }
 202
 203         if (prescaler == 0) {
 204                 /* Go up from the first divider */
 205                 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
 206                         if (!prescaler_table[prescaler])
 207                                 continue;
 208                         pval = prescaler_table[prescaler];
 209                         div = clk_rate;
 210                         do_div(div, pval);
 211                         div = div * state->period;
 212                         do_div(div, NSEC_PER_SEC);
 213                         if (div - 1 <= PWM_PRD_MASK)
 214                                 break;
 215                 }
 216
 217                 if (div - 1 > PWM_PRD_MASK)
 218                         return -EINVAL;
 219         }
 220
 221         *prd = div;
 222         div *= state->duty_cycle;
 223         do_div(div, state->period);
 224         *dty = div;
 225         *prsclr = prescaler;
 226
 227         return 0;
 228 }
 229
 230 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 231                            const struct pwm_state *state)
 232 {
 233         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 234         struct pwm_state cstate;
 235         u32 ctrl, duty, period, val;
 236         int ret;
 237         unsigned int delay_us, prescaler;
 238         unsigned long now;
 239         bool bypass;
 240
 241         pwm_get_state(pwm, &cstate);
 242
 243         if (!cstate.enabled) {
 244                 ret = clk_prepare_enable(sun4i_pwm->clk);
 245                 if (ret) {
 246                         dev_err(chip->dev, "failed to enable PWM clock\n");
 247                         return ret;
 248                 }
 249         }
 250
 251         ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
 252                                   &bypass);
 253         if (ret) {
 254                 dev_err(chip->dev, "period exceeds the maximum value\n");
 255                 if (!cstate.enabled)
 256                         clk_disable_unprepare(sun4i_pwm->clk);
 257                 return ret;
 258         }
 259
 260         spin_lock(&sun4i_pwm->ctrl_lock);
 261         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 262
 263         if (sun4i_pwm->data->has_direct_mod_clk_output) {
 264                 if (bypass) {
 265                         ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
 266                         /* We can skip other parameter */
 267                         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 268                         spin_unlock(&sun4i_pwm->ctrl_lock);
 269                         return 0;
 270                 }
 271
 272                 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
 273         }
 274
 275         if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 276                 /* Prescaler changed, the clock has to be gated */
 277                 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 278                 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 279
 280                 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 281                 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 282         }
 283
 284         val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 285         sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 286         sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 287                 usecs_to_jiffies(cstate.period / 1000 + 1);
 288         sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 289
 290         if (state->polarity != PWM_POLARITY_NORMAL)
 291                 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 292         else
 293                 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 294
 295         ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 296
 297         if (state->enabled) {
 298                 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
 299         } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 300                 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 301                 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 302         }
 303
 304         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 305
 306         spin_unlock(&sun4i_pwm->ctrl_lock);
 307
 308         if (state->enabled)
 309                 return 0;
 310
 311         if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 312                 clk_disable_unprepare(sun4i_pwm->clk);
 313                 return 0;
 314         }
 315
 316         /* We need a full period to elapse before disabling the channel. */
 317         now = jiffies;
 318         if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
 319             time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
 320                 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
 321                                            now);
 322                 if ((delay_us / 500) > MAX_UDELAY_MS)
 323                         msleep(delay_us / 1000 + 1);
 324                 else
 325                         usleep_range(delay_us, delay_us * 2);
 326         }
 327         sun4i_pwm->needs_delay[pwm->hwpwm] = false;
 328
 329         spin_lock(&sun4i_pwm->ctrl_lock);
 330         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 331         ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 332         ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 333         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 334         spin_unlock(&sun4i_pwm->ctrl_lock);
 335
 336         clk_disable_unprepare(sun4i_pwm->clk);
 337
 338         return 0;
 339 }
 340
 341 static const struct pwm_ops sun4i_pwm_ops = {
 342         .apply = sun4i_pwm_apply,
 343         .get_state = sun4i_pwm_get_state,
 344         .owner = THIS_MODULE,
 345 };
 346
 347 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
 348         .has_prescaler_bypass = false,
 349         .npwm = 2,
 350 };
 351
 352 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
 353         .has_prescaler_bypass = true,
 354         .npwm = 2,
 355 };
 356
 357 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
 358         .has_prescaler_bypass = true,
 359         .npwm = 1,
 360 };
 361
 362 static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
 363         .has_prescaler_bypass = true,
 364         .has_direct_mod_clk_output = true,
 365         .npwm = 2,
 366 };
 367
 368 static const struct of_device_id sun4i_pwm_dt_ids[] = {
 369         {
 370                 .compatible = "allwinner,sun4i-a10-pwm",
 371                 .data = &sun4i_pwm_dual_nobypass,
 372         }, {
 373                 .compatible = "allwinner,sun5i-a10s-pwm",
 374                 .data = &sun4i_pwm_dual_bypass,
 375         }, {
 376                 .compatible = "allwinner,sun5i-a13-pwm",
 377                 .data = &sun4i_pwm_single_bypass,
 378         }, {
 379                 .compatible = "allwinner,sun7i-a20-pwm",
 380                 .data = &sun4i_pwm_dual_bypass,
 381         }, {
 382                 .compatible = "allwinner,sun8i-h3-pwm",
 383                 .data = &sun4i_pwm_single_bypass,
 384         }, {
 385                 .compatible = "allwinner,sun50i-h6-pwm",
 386                 .data = &sun50i_h6_pwm_data,
 387         }, {
 388                 /* sentinel */
 389         },
 390 };
 391 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
 392
 393 static int sun4i_pwm_probe(struct platform_device *pdev)
 394 {
 395         struct sun4i_pwm_chip *pwm;
 396         struct resource *res;
 397         int ret;
 398
 399         pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 400         if (!pwm)
 401                 return -ENOMEM;
 402
 403         pwm->data = of_device_get_match_data(&pdev->dev);
 404         if (!pwm->data)
 405                 return -ENODEV;
 406
 407         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 408         pwm->base = devm_ioremap_resource(&pdev->dev, res);
 409         if (IS_ERR(pwm->base))
 410                 return PTR_ERR(pwm->base);
 411
 412         /*
 413          * All hardware variants need a source clock that is divided and
 414          * then feeds the counter that defines the output wave form. In the
 415          * device tree this clock is either unnamed or called "mod".
 416          * Some variants (e.g. H6) need another clock to access the
 417          * hardware registers; this is called "bus".
 418          * So we request "mod" first (and ignore the corner case that a
 419          * parent provides a "mod" clock while the right one would be the
 420          * unnamed one of the PWM device) and if this is not found we fall
 421          * back to the first clock of the PWM.
 422          */
 423         pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
 424         if (IS_ERR(pwm->clk)) {
 425                 if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 426                         dev_err(&pdev->dev, "get mod clock failed %pe\n",
 427                                 pwm->clk);
 428                 return PTR_ERR(pwm->clk);
 429         }
 430
 431         if (!pwm->clk) {
 432                 pwm->clk = devm_clk_get(&pdev->dev, NULL);
 433                 if (IS_ERR(pwm->clk)) {
 434                         if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 435                                 dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
 436                                         pwm->clk);
 437                         return PTR_ERR(pwm->clk);
 438                 }
 439         }
 440
 441         pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
 442         if (IS_ERR(pwm->bus_clk)) {
 443                 if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 444                         dev_err(&pdev->dev, "get bus clock failed %pe\n",
 445                                 pwm->bus_clk);
 446                 return PTR_ERR(pwm->bus_clk);
 447         }
 448
 449         pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 450         if (IS_ERR(pwm->rst)) {
 451                 if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 452                         dev_err(&pdev->dev, "get reset failed %pe\n",
 453                                 pwm->rst);
 454                 return PTR_ERR(pwm->rst);
 455         }
 456
 457         /* Deassert reset */
 458         ret = reset_control_deassert(pwm->rst);
 459         if (ret) {
 460                 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
 461                         ERR_PTR(ret));
 462                 return ret;
 463         }
 464
 465         /*
 466          * We're keeping the bus clock on for the sake of simplicity.
 467          * Actually it only needs to be on for hardware register accesses.
 468          */
 469         ret = clk_prepare_enable(pwm->bus_clk);
 470         if (ret) {
 471                 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
 472                         ERR_PTR(ret));
 473                 goto err_bus;
 474         }
 475
 476         pwm->chip.dev = &pdev->dev;
 477         pwm->chip.ops = &sun4i_pwm_ops;
 478         pwm->chip.base = -1;
 479         pwm->chip.npwm = pwm->data->npwm;
 480         pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 481         pwm->chip.of_pwm_n_cells = 3;
 482
 483         spin_lock_init(&pwm->ctrl_lock);
 484
 485         ret = pwmchip_add(&pwm->chip);
 486         if (ret < 0) {
 487                 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 488                 goto err_pwm_add;
 489         }
 490
 491         platform_set_drvdata(pdev, pwm);
 492
 493         return 0;
 494
 495 err_pwm_add:
 496         clk_disable_unprepare(pwm->bus_clk);
 497 err_bus:
 498         reset_control_assert(pwm->rst);
 499
 500         return ret;
 501 }
 502
 503 static int sun4i_pwm_remove(struct platform_device *pdev)
 504 {
 505         struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
 506         int ret;
 507
 508         ret = pwmchip_remove(&pwm->chip);
 509         if (ret)
 510                 return ret;
 511
 512         clk_disable_unprepare(pwm->bus_clk);
 513         reset_control_assert(pwm->rst);
 514
 515         return 0;
 516 }
 517
 518 static struct platform_driver sun4i_pwm_driver = {
 519         .driver = {
 520                 .name = "sun4i-pwm",
 521                 .of_match_table = sun4i_pwm_dt_ids,
 522         },
 523         .probe = sun4i_pwm_probe,
 524         .remove = sun4i_pwm_remove,
 525 };
 526 module_platform_driver(sun4i_pwm_driver);
 527
 528 MODULE_ALIAS("platform:sun4i-pwm");
 529 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
 530 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
 531 MODULE_LICENSE("GPL v2");