1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Spreadtrum Communications Inc.
9 #include <linux/math64.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pwm.h>
14 #define SPRD_PWM_PRESCALE 0x0
15 #define SPRD_PWM_MOD 0x4
16 #define SPRD_PWM_DUTY 0x8
17 #define SPRD_PWM_ENABLE 0x18
19 #define SPRD_PWM_MOD_MAX GENMASK(7, 0)
20 #define SPRD_PWM_DUTY_MSK GENMASK(15, 0)
21 #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0)
22 #define SPRD_PWM_ENABLE_BIT BIT(0)
24 #define SPRD_PWM_CHN_NUM 4
25 #define SPRD_PWM_REGS_SHIFT 5
26 #define SPRD_PWM_CHN_CLKS_NUM 2
27 #define SPRD_PWM_CHN_OUTPUT_CLK 1
30 struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM];
34 struct sprd_pwm_chip {
39 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
43 * The list of clocks required by PWM channels, and each channel has 2 clocks:
44 * enable clock and pwm clock.
46 static const char * const sprd_pwm_clks[] = {
53 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
55 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
57 return readl_relaxed(spc->base + offset);
60 static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
63 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
65 writel_relaxed(val, spc->base + offset);
68 static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
69 struct pwm_state *state)
71 struct sprd_pwm_chip *spc =
72 container_of(chip, struct sprd_pwm_chip, chip);
73 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
74 u32 val, duty, prescale;
79 * The clocks to PWM channel has to be enabled first before
80 * reading to the registers.
82 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
84 dev_err(spc->dev, "failed to enable pwm%u clocks\n",
89 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
90 if (val & SPRD_PWM_ENABLE_BIT)
91 state->enabled = true;
93 state->enabled = false;
96 * The hardware provides a counter that is feed by the source clock.
97 * The period length is (PRESCALE + 1) * MOD counter steps.
98 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
99 * Thus the period_ns and duty_ns calculation formula should be:
100 * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate
101 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate
103 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
104 prescale = val & SPRD_PWM_PRESCALE_MSK;
105 tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX;
106 state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
108 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
109 duty = val & SPRD_PWM_DUTY_MSK;
110 tmp = (prescale + 1) * NSEC_PER_SEC * duty;
111 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
113 /* Disable PWM clocks if the PWM channel is not in enable state. */
115 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
118 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
119 int duty_ns, int period_ns)
121 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
126 * The hardware provides a counter that is feed by the source clock.
127 * The period length is (PRESCALE + 1) * MOD counter steps.
128 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
130 * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX.
131 * The value for PRESCALE is selected such that the resulting period
132 * gets the maximal length not bigger than the requested one with the
133 * given settings (MOD = SPRD_PWM_MOD_MAX and input clock).
135 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
137 tmp = (u64)chn->clk_rate * period_ns;
138 do_div(tmp, NSEC_PER_SEC);
139 prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;
140 if (prescale > SPRD_PWM_PRESCALE_MSK)
141 prescale = SPRD_PWM_PRESCALE_MSK;
144 * Note: Writing DUTY triggers the hardware to actually apply the
145 * values written to MOD and DUTY to the output, so must keep writing
148 * The hardware can ensures that current running period is completed
149 * before changing a new configuration to avoid mixed settings.
151 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
152 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
153 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
158 static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
159 const struct pwm_state *state)
161 struct sprd_pwm_chip *spc =
162 container_of(chip, struct sprd_pwm_chip, chip);
163 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
164 struct pwm_state *cstate = &pwm->state;
167 if (state->enabled) {
168 if (!cstate->enabled) {
170 * The clocks to PWM channel has to be enabled first
171 * before writing to the registers.
173 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM,
177 "failed to enable pwm%u clocks\n",
183 if (state->period != cstate->period ||
184 state->duty_cycle != cstate->duty_cycle) {
185 ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
191 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
192 } else if (cstate->enabled) {
194 * Note: After setting SPRD_PWM_ENABLE to zero, the controller
195 * will not wait for current period to be completed, instead it
196 * will stop the PWM channel immediately.
198 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
200 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
206 static const struct pwm_ops sprd_pwm_ops = {
207 .apply = sprd_pwm_apply,
208 .get_state = sprd_pwm_get_state,
209 .owner = THIS_MODULE,
212 static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
217 for (i = 0; i < SPRD_PWM_CHN_NUM; i++) {
218 struct sprd_pwm_chn *chn = &spc->chn[i];
221 for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j)
223 sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j];
225 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
231 return dev_err_probe(spc->dev, ret,
232 "failed to get channel clocks\n");
235 clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;
236 chn->clk_rate = clk_get_rate(clk_pwm);
240 dev_err(spc->dev, "no available PWM channels\n");
249 static int sprd_pwm_probe(struct platform_device *pdev)
251 struct sprd_pwm_chip *spc;
254 spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
258 spc->base = devm_platform_ioremap_resource(pdev, 0);
259 if (IS_ERR(spc->base))
260 return PTR_ERR(spc->base);
262 spc->dev = &pdev->dev;
263 platform_set_drvdata(pdev, spc);
265 ret = sprd_pwm_clk_init(spc);
269 spc->chip.dev = &pdev->dev;
270 spc->chip.ops = &sprd_pwm_ops;
272 spc->chip.npwm = spc->num_pwms;
274 ret = pwmchip_add(&spc->chip);
276 dev_err(&pdev->dev, "failed to add PWM chip\n");
281 static int sprd_pwm_remove(struct platform_device *pdev)
283 struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
285 return pwmchip_remove(&spc->chip);
288 static const struct of_device_id sprd_pwm_of_match[] = {
289 { .compatible = "sprd,ums512-pwm", },
292 MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
294 static struct platform_driver sprd_pwm_driver = {
297 .of_match_table = sprd_pwm_of_match,
299 .probe = sprd_pwm_probe,
300 .remove = sprd_pwm_remove,
303 module_platform_driver(sprd_pwm_driver);
305 MODULE_DESCRIPTION("Spreadtrum PWM Driver");
306 MODULE_LICENSE("GPL v2");