1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * Copyright (C) 2014 ROCKCHIP, Inc.
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/property.h>
15 #include <linux/pwm.h>
16 #include <linux/time.h>
18 #define PWM_CTRL_TIMER_EN (1 << 0)
19 #define PWM_CTRL_OUTPUT_EN (1 << 3)
21 #define PWM_ENABLE (1 << 0)
22 #define PWM_CONTINUOUS (1 << 1)
23 #define PWM_DUTY_POSITIVE (1 << 3)
24 #define PWM_DUTY_NEGATIVE (0 << 3)
25 #define PWM_INACTIVE_NEGATIVE (0 << 4)
26 #define PWM_INACTIVE_POSITIVE (1 << 4)
27 #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
28 #define PWM_OUTPUT_LEFT (0 << 5)
29 #define PWM_LOCK_EN (1 << 6)
30 #define PWM_LP_DISABLE (0 << 8)
32 struct rockchip_pwm_chip {
35 const struct rockchip_pwm_data *data;
39 struct rockchip_pwm_regs {
46 struct rockchip_pwm_data {
47 struct rockchip_pwm_regs regs;
48 unsigned int prescaler;
49 bool supports_polarity;
54 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *chip)
56 return pwmchip_get_drvdata(chip);
59 static int rockchip_pwm_get_state(struct pwm_chip *chip,
60 struct pwm_device *pwm,
61 struct pwm_state *state)
63 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
64 u32 enable_conf = pc->data->enable_conf;
65 unsigned long clk_rate;
70 ret = clk_enable(pc->pclk);
74 ret = clk_enable(pc->clk);
78 clk_rate = clk_get_rate(pc->clk);
80 tmp = readl_relaxed(pc->base + pc->data->regs.period);
81 tmp *= pc->data->prescaler * NSEC_PER_SEC;
82 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
84 tmp = readl_relaxed(pc->base + pc->data->regs.duty);
85 tmp *= pc->data->prescaler * NSEC_PER_SEC;
86 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
88 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
89 state->enabled = (val & enable_conf) == enable_conf;
91 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
92 state->polarity = PWM_POLARITY_INVERSED;
94 state->polarity = PWM_POLARITY_NORMAL;
97 clk_disable(pc->pclk);
102 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
103 const struct pwm_state *state)
105 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
106 unsigned long period, duty;
110 clk_rate = clk_get_rate(pc->clk);
113 * Since period and duty cycle registers have a width of 32
114 * bits, every possible input period can be obtained using the
115 * default prescaler value for all practical clock rate values.
117 div = clk_rate * state->period;
118 period = DIV_ROUND_CLOSEST_ULL(div,
119 pc->data->prescaler * NSEC_PER_SEC);
121 div = clk_rate * state->duty_cycle;
122 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
125 * Lock the period and duty of previous configuration, then
126 * change the duty and period, that would not be effective.
128 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
129 if (pc->data->supports_lock) {
131 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
134 writel(period, pc->base + pc->data->regs.period);
135 writel(duty, pc->base + pc->data->regs.duty);
137 if (pc->data->supports_polarity) {
138 ctrl &= ~PWM_POLARITY_MASK;
139 if (state->polarity == PWM_POLARITY_INVERSED)
140 ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
142 ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
146 * Unlock and set polarity at the same time,
147 * the configuration of duty, period and polarity
148 * would be effective together at next period.
150 if (pc->data->supports_lock)
151 ctrl &= ~PWM_LOCK_EN;
153 writel(ctrl, pc->base + pc->data->regs.ctrl);
156 static int rockchip_pwm_enable(struct pwm_chip *chip,
157 struct pwm_device *pwm,
160 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
161 u32 enable_conf = pc->data->enable_conf;
166 ret = clk_enable(pc->clk);
171 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
178 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
181 clk_disable(pc->clk);
186 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
187 const struct pwm_state *state)
189 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
190 struct pwm_state curstate;
194 ret = clk_enable(pc->pclk);
198 ret = clk_enable(pc->clk);
202 pwm_get_state(pwm, &curstate);
203 enabled = curstate.enabled;
205 if (state->polarity != curstate.polarity && enabled &&
206 !pc->data->supports_lock) {
207 ret = rockchip_pwm_enable(chip, pwm, false);
213 rockchip_pwm_config(chip, pwm, state);
214 if (state->enabled != enabled) {
215 ret = rockchip_pwm_enable(chip, pwm, state->enabled);
221 clk_disable(pc->clk);
222 clk_disable(pc->pclk);
227 static const struct pwm_ops rockchip_pwm_ops = {
228 .get_state = rockchip_pwm_get_state,
229 .apply = rockchip_pwm_apply,
232 static const struct rockchip_pwm_data pwm_data_v1 = {
240 .supports_polarity = false,
241 .supports_lock = false,
242 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
245 static const struct rockchip_pwm_data pwm_data_v2 = {
253 .supports_polarity = true,
254 .supports_lock = false,
255 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
259 static const struct rockchip_pwm_data pwm_data_vop = {
267 .supports_polarity = true,
268 .supports_lock = false,
269 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
273 static const struct rockchip_pwm_data pwm_data_v3 = {
281 .supports_polarity = true,
282 .supports_lock = true,
283 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
287 static const struct of_device_id rockchip_pwm_dt_ids[] = {
288 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
289 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
290 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
291 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
294 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
296 static int rockchip_pwm_probe(struct platform_device *pdev)
298 struct pwm_chip *chip;
299 struct rockchip_pwm_chip *pc;
300 u32 enable_conf, ctrl;
304 chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*pc));
306 return PTR_ERR(chip);
307 pc = to_rockchip_pwm_chip(chip);
309 pc->base = devm_platform_ioremap_resource(pdev, 0);
310 if (IS_ERR(pc->base))
311 return PTR_ERR(pc->base);
313 pc->clk = devm_clk_get(&pdev->dev, "pwm");
314 if (IS_ERR(pc->clk)) {
315 pc->clk = devm_clk_get(&pdev->dev, NULL);
317 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
318 "Can't get PWM clk\n");
321 count = of_count_phandle_with_args(pdev->dev.of_node,
322 "clocks", "#clock-cells");
324 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
328 if (IS_ERR(pc->pclk))
329 return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");
331 ret = clk_prepare_enable(pc->clk);
333 return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n");
335 ret = clk_prepare_enable(pc->pclk);
337 dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n");
341 platform_set_drvdata(pdev, chip);
343 pc->data = device_get_match_data(&pdev->dev);
344 chip->ops = &rockchip_pwm_ops;
346 enable_conf = pc->data->enable_conf;
347 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
348 enabled = (ctrl & enable_conf) == enable_conf;
350 ret = pwmchip_add(chip);
352 dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
356 /* Keep the PWM clk enabled if the PWM appears to be up and running. */
358 clk_disable(pc->clk);
360 clk_disable(pc->pclk);
365 clk_disable_unprepare(pc->pclk);
367 clk_disable_unprepare(pc->clk);
372 static void rockchip_pwm_remove(struct platform_device *pdev)
374 struct pwm_chip *chip = platform_get_drvdata(pdev);
375 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
377 pwmchip_remove(chip);
379 clk_unprepare(pc->pclk);
380 clk_unprepare(pc->clk);
383 static struct platform_driver rockchip_pwm_driver = {
385 .name = "rockchip-pwm",
386 .of_match_table = rockchip_pwm_dt_ids,
388 .probe = rockchip_pwm_probe,
389 .remove_new = rockchip_pwm_remove,
391 module_platform_driver(rockchip_pwm_driver);
393 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
394 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
395 MODULE_LICENSE("GPL v2");