drivers/pwm/pwm-rockchip.c

   1 /*
   2  * PWM driver for Rockchip SoCs
   3  *
   4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/time.h>
  20
  21 #define PWM_CTRL_TIMER_EN       (1 << 0)
  22 #define PWM_CTRL_OUTPUT_EN      (1 << 3)
  23
  24 #define PWM_ENABLE              (1 << 0)
  25 #define PWM_CONTINUOUS          (1 << 1)
  26 #define PWM_DUTY_POSITIVE       (1 << 3)
  27 #define PWM_DUTY_NEGATIVE       (0 << 3)
  28 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
  29 #define PWM_INACTIVE_POSITIVE   (1 << 4)
  30 #define PWM_POLARITY_MASK       (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
  31 #define PWM_OUTPUT_LEFT         (0 << 5)
  32 #define PWM_LP_DISABLE          (0 << 8)
  33
  34 struct rockchip_pwm_chip {
  35         struct pwm_chip chip;
  36         struct clk *clk;
  37         struct clk *pclk;
  38         const struct rockchip_pwm_data *data;
  39         void __iomem *base;
  40 };
  41
  42 struct rockchip_pwm_regs {
  43         unsigned long duty;
  44         unsigned long period;
  45         unsigned long cntr;
  46         unsigned long ctrl;
  47 };
  48
  49 struct rockchip_pwm_data {
  50         struct rockchip_pwm_regs regs;
  51         unsigned int prescaler;
  52         bool supports_polarity;
  53         u32 enable_conf;
  54 };
  55
  56 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
  57 {
  58         return container_of(c, struct rockchip_pwm_chip, chip);
  59 }
  60
  61 static void rockchip_pwm_get_state(struct pwm_chip *chip,
  62                                    struct pwm_device *pwm,
  63                                    struct pwm_state *state)
  64 {
  65         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
  66         u32 enable_conf = pc->data->enable_conf;
  67         unsigned long clk_rate;
  68         u64 tmp;
  69         u32 val;
  70         int ret;
  71
  72         ret = clk_enable(pc->pclk);
  73         if (ret)
  74                 return;
  75
  76         clk_rate = clk_get_rate(pc->clk);
  77
  78         tmp = readl_relaxed(pc->base + pc->data->regs.period);
  79         tmp *= pc->data->prescaler * NSEC_PER_SEC;
  80         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  81
  82         tmp = readl_relaxed(pc->base + pc->data->regs.duty);
  83         tmp *= pc->data->prescaler * NSEC_PER_SEC;
  84         state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
  85
  86         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
  87         if (pc->data->supports_polarity)
  88                 state->enabled = ((val & enable_conf) != enable_conf) ?
  89                                  false : true;
  90         else
  91                 state->enabled = ((val & enable_conf) == enable_conf) ?
  92                                  true : false;
  93
  94         if (pc->data->supports_polarity) {
  95                 if (!(val & PWM_DUTY_POSITIVE))
  96                         state->polarity = PWM_POLARITY_INVERSED;
  97         }
  98
  99         clk_disable(pc->pclk);
 100 }
 101
 102 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 103                                struct pwm_state *state)
 104 {
 105         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 106         unsigned long period, duty;
 107         u64 clk_rate, div;
 108         u32 ctrl;
 109
 110         clk_rate = clk_get_rate(pc->clk);
 111
 112         /*
 113          * Since period and duty cycle registers have a width of 32
 114          * bits, every possible input period can be obtained using the
 115          * default prescaler value for all practical clock rate values.
 116          */
 117         div = clk_rate * state->period;
 118         period = DIV_ROUND_CLOSEST_ULL(div,
 119                                        pc->data->prescaler * NSEC_PER_SEC);
 120
 121         div = clk_rate * state->duty_cycle;
 122         duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
 123
 124         writel(period, pc->base + pc->data->regs.period);
 125         writel(duty, pc->base + pc->data->regs.duty);
 126
 127         ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
 128         if (pc->data->supports_polarity) {
 129                 ctrl &= ~PWM_POLARITY_MASK;
 130                 if (state->polarity == PWM_POLARITY_INVERSED)
 131                         ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
 132                 else
 133                         ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
 134         }
 135         writel(ctrl, pc->base + pc->data->regs.ctrl);
 136 }
 137
 138 static int rockchip_pwm_enable(struct pwm_chip *chip,
 139                                struct pwm_device *pwm,
 140                                bool enable)
 141 {
 142         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 143         u32 enable_conf = pc->data->enable_conf;
 144         int ret;
 145         u32 val;
 146
 147         if (enable) {
 148                 ret = clk_enable(pc->clk);
 149                 if (ret)
 150                         return ret;
 151         }
 152
 153         val = readl_relaxed(pc->base + pc->data->regs.ctrl);
 154
 155         if (enable)
 156                 val |= enable_conf;
 157         else
 158                 val &= ~enable_conf;
 159
 160         writel_relaxed(val, pc->base + pc->data->regs.ctrl);
 161
 162         if (!enable)
 163                 clk_disable(pc->clk);
 164
 165         return 0;
 166 }
 167
 168 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 169                               struct pwm_state *state)
 170 {
 171         struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 172         struct pwm_state curstate;
 173         bool enabled;
 174         int ret = 0;
 175
 176         ret = clk_enable(pc->pclk);
 177         if (ret)
 178                 return ret;
 179
 180         pwm_get_state(pwm, &curstate);
 181         enabled = curstate.enabled;
 182
 183         if (state->polarity != curstate.polarity && enabled) {
 184                 ret = rockchip_pwm_enable(chip, pwm, false);
 185                 if (ret)
 186                         goto out;
 187                 enabled = false;
 188         }
 189
 190         rockchip_pwm_config(chip, pwm, state);
 191         if (state->enabled != enabled) {
 192                 ret = rockchip_pwm_enable(chip, pwm, state->enabled);
 193                 if (ret)
 194                         goto out;
 195         }
 196
 197         /*
 198          * Update the state with the real hardware, which can differ a bit
 199          * because of period/duty_cycle approximation.
 200          */
 201         rockchip_pwm_get_state(chip, pwm, state);
 202
 203 out:
 204         clk_disable(pc->pclk);
 205
 206         return ret;
 207 }
 208
 209 static const struct pwm_ops rockchip_pwm_ops = {
 210         .get_state = rockchip_pwm_get_state,
 211         .apply = rockchip_pwm_apply,
 212         .owner = THIS_MODULE,
 213 };
 214
 215 static const struct rockchip_pwm_data pwm_data_v1 = {
 216         .regs = {
 217                 .duty = 0x04,
 218                 .period = 0x08,
 219                 .cntr = 0x00,
 220                 .ctrl = 0x0c,
 221         },
 222         .prescaler = 2,
 223         .supports_polarity = false,
 224         .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
 225 };
 226
 227 static const struct rockchip_pwm_data pwm_data_v2 = {
 228         .regs = {
 229                 .duty = 0x08,
 230                 .period = 0x04,
 231                 .cntr = 0x00,
 232                 .ctrl = 0x0c,
 233         },
 234         .prescaler = 1,
 235         .supports_polarity = true,
 236         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 237                        PWM_CONTINUOUS,
 238 };
 239
 240 static const struct rockchip_pwm_data pwm_data_vop = {
 241         .regs = {
 242                 .duty = 0x08,
 243                 .period = 0x04,
 244                 .cntr = 0x0c,
 245                 .ctrl = 0x00,
 246         },
 247         .prescaler = 1,
 248         .supports_polarity = true,
 249         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
 250                        PWM_CONTINUOUS,
 251 };
 252
 253 static const struct of_device_id rockchip_pwm_dt_ids[] = {
 254         { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
 255         { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
 256         { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
 257         { /* sentinel */ }
 258 };
 259 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
 260
 261 static int rockchip_pwm_probe(struct platform_device *pdev)
 262 {
 263         const struct of_device_id *id;
 264         struct rockchip_pwm_chip *pc;
 265         struct resource *r;
 266         int ret, count;
 267
 268         id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
 269         if (!id)
 270                 return -EINVAL;
 271
 272         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 273         if (!pc)
 274                 return -ENOMEM;
 275
 276         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 277         pc->base = devm_ioremap_resource(&pdev->dev, r);
 278         if (IS_ERR(pc->base))
 279                 return PTR_ERR(pc->base);
 280
 281         pc->clk = devm_clk_get(&pdev->dev, "pwm");
 282         if (IS_ERR(pc->clk)) {
 283                 pc->clk = devm_clk_get(&pdev->dev, NULL);
 284                 if (IS_ERR(pc->clk)) {
 285                         ret = PTR_ERR(pc->clk);
 286                         if (ret != -EPROBE_DEFER)
 287                                 dev_err(&pdev->dev, "Can't get bus clk: %d\n",
 288                                         ret);
 289                         return ret;
 290                 }
 291         }
 292
 293         count = of_count_phandle_with_args(pdev->dev.of_node,
 294                                            "clocks", "#clock-cells");
 295         if (count == 2)
 296                 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
 297         else
 298                 pc->pclk = pc->clk;
 299
 300         if (IS_ERR(pc->pclk)) {
 301                 ret = PTR_ERR(pc->pclk);
 302                 if (ret != -EPROBE_DEFER)
 303                         dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
 304                 return ret;
 305         }
 306
 307         ret = clk_prepare_enable(pc->clk);
 308         if (ret) {
 309                 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
 310                 return ret;
 311         }
 312
 313         ret = clk_prepare(pc->pclk);
 314         if (ret) {
 315                 dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
 316                 goto err_clk;
 317         }
 318
 319         platform_set_drvdata(pdev, pc);
 320
 321         pc->data = id->data;
 322         pc->chip.dev = &pdev->dev;
 323         pc->chip.ops = &rockchip_pwm_ops;
 324         pc->chip.base = -1;
 325         pc->chip.npwm = 1;
 326
 327         if (pc->data->supports_polarity) {
 328                 pc->chip.of_xlate = of_pwm_xlate_with_flags;
 329                 pc->chip.of_pwm_n_cells = 3;
 330         }
 331
 332         ret = pwmchip_add(&pc->chip);
 333         if (ret < 0) {
 334                 clk_unprepare(pc->clk);
 335                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 336                 goto err_pclk;
 337         }
 338
 339         /* Keep the PWM clk enabled if the PWM appears to be up and running. */
 340         if (!pwm_is_enabled(pc->chip.pwms))
 341                 clk_disable(pc->clk);
 342
 343         return 0;
 344
 345 err_pclk:
 346         clk_unprepare(pc->pclk);
 347 err_clk:
 348         clk_disable_unprepare(pc->clk);
 349
 350         return ret;
 351 }
 352
 353 static int rockchip_pwm_remove(struct platform_device *pdev)
 354 {
 355         struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
 356
 357         /*
 358          * Disable the PWM clk before unpreparing it if the PWM device is still
 359          * running. This should only happen when the last PWM user left it
 360          * enabled, or when nobody requested a PWM that was previously enabled
 361          * by the bootloader.
 362          *
 363          * FIXME: Maybe the core should disable all PWM devices in
 364          * pwmchip_remove(). In this case we'd only have to call
 365          * clk_unprepare() after pwmchip_remove().
 366          *
 367          */
 368         if (pwm_is_enabled(pc->chip.pwms))
 369                 clk_disable(pc->clk);
 370
 371         clk_unprepare(pc->pclk);
 372         clk_unprepare(pc->clk);
 373
 374         return pwmchip_remove(&pc->chip);
 375 }
 376
 377 static struct platform_driver rockchip_pwm_driver = {
 378         .driver = {
 379                 .name = "rockchip-pwm",
 380                 .of_match_table = rockchip_pwm_dt_ids,
 381         },
 382         .probe = rockchip_pwm_probe,
 383         .remove = rockchip_pwm_remove,
 384 };
 385 module_platform_driver(rockchip_pwm_driver);
 386
 387 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
 388 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
 389 MODULE_LICENSE("GPL v2");