1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car PWM Timer driver
5 * Copyright (C) 2015 Renesas Electronics Corporation
8 * - The hardware cannot generate a 0% duty cycle.
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/log2.h>
15 #include <linux/math64.h>
16 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/slab.h>
23 #define RCAR_PWM_MAX_DIVISION 24
24 #define RCAR_PWM_MAX_CYCLE 1023
26 #define RCAR_PWMCR 0x00
27 #define RCAR_PWMCR_CC0_MASK 0x000f0000
28 #define RCAR_PWMCR_CC0_SHIFT 16
29 #define RCAR_PWMCR_CCMD BIT(15)
30 #define RCAR_PWMCR_SYNC BIT(11)
31 #define RCAR_PWMCR_SS0 BIT(4)
32 #define RCAR_PWMCR_EN0 BIT(0)
34 #define RCAR_PWMCNT 0x04
35 #define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
36 #define RCAR_PWMCNT_CYC0_SHIFT 16
37 #define RCAR_PWMCNT_PH0_MASK 0x000003ff
38 #define RCAR_PWMCNT_PH0_SHIFT 0
40 struct rcar_pwm_chip {
46 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
48 return container_of(chip, struct rcar_pwm_chip, chip);
51 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
54 writel(data, rp->base + offset);
57 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
59 return readl(rp->base + offset);
62 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
67 value = rcar_pwm_read(rp, offset);
70 rcar_pwm_write(rp, value, offset);
73 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
75 unsigned long clk_rate = clk_get_rate(rp->clk);
81 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
82 tmp = (u64)period_ns * clk_rate + div - 1;
83 tmp = div64_u64(tmp, div);
84 div = ilog2(tmp - 1) + 1;
86 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
89 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
94 value = rcar_pwm_read(rp, RCAR_PWMCR);
95 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
98 value |= RCAR_PWMCR_CCMD;
102 value |= div << RCAR_PWMCR_CC0_SHIFT;
103 rcar_pwm_write(rp, value, RCAR_PWMCR);
106 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
109 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
110 unsigned long clk_rate = clk_get_rate(rp->clk);
113 one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
114 do_div(one_cycle, clk_rate);
116 tmp = period_ns * 100ULL;
117 do_div(tmp, one_cycle);
118 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
120 tmp = duty_ns * 100ULL;
121 do_div(tmp, one_cycle);
122 ph = tmp & RCAR_PWMCNT_PH0_MASK;
124 /* Avoid prohibited setting */
125 if (cyc == 0 || ph == 0)
128 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
133 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
135 return pm_runtime_get_sync(chip->dev);
138 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
140 pm_runtime_put(chip->dev);
143 static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
147 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
148 value = rcar_pwm_read(rp, RCAR_PWMCNT);
149 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
150 (value & RCAR_PWMCNT_PH0_MASK) == 0)
153 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
158 static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
160 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
163 static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
164 const struct pwm_state *state)
166 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
169 /* This HW/driver only supports normal polarity */
170 if (state->polarity != PWM_POLARITY_NORMAL)
173 if (!state->enabled) {
174 rcar_pwm_disable(rp);
178 div = rcar_pwm_get_clock_division(rp, state->period);
182 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
184 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
186 rcar_pwm_set_clock_control(rp, div);
188 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
189 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
192 ret = rcar_pwm_enable(rp);
197 static const struct pwm_ops rcar_pwm_ops = {
198 .request = rcar_pwm_request,
199 .free = rcar_pwm_free,
200 .apply = rcar_pwm_apply,
201 .owner = THIS_MODULE,
204 static int rcar_pwm_probe(struct platform_device *pdev)
206 struct rcar_pwm_chip *rcar_pwm;
207 struct resource *res;
210 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
211 if (rcar_pwm == NULL)
214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215 rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
216 if (IS_ERR(rcar_pwm->base))
217 return PTR_ERR(rcar_pwm->base);
219 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
220 if (IS_ERR(rcar_pwm->clk)) {
221 dev_err(&pdev->dev, "cannot get clock\n");
222 return PTR_ERR(rcar_pwm->clk);
225 platform_set_drvdata(pdev, rcar_pwm);
227 rcar_pwm->chip.dev = &pdev->dev;
228 rcar_pwm->chip.ops = &rcar_pwm_ops;
229 rcar_pwm->chip.base = -1;
230 rcar_pwm->chip.npwm = 1;
232 pm_runtime_enable(&pdev->dev);
234 ret = pwmchip_add(&rcar_pwm->chip);
236 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
237 pm_runtime_disable(&pdev->dev);
244 static int rcar_pwm_remove(struct platform_device *pdev)
246 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
249 ret = pwmchip_remove(&rcar_pwm->chip);
251 pm_runtime_disable(&pdev->dev);
256 static const struct of_device_id rcar_pwm_of_table[] = {
257 { .compatible = "renesas,pwm-rcar", },
260 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
262 static struct platform_driver rcar_pwm_driver = {
263 .probe = rcar_pwm_probe,
264 .remove = rcar_pwm_remove,
267 .of_match_table = of_match_ptr(rcar_pwm_of_table),
270 module_platform_driver(rcar_pwm_driver);
272 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
273 MODULE_DESCRIPTION("Renesas PWM Timer Driver");
274 MODULE_LICENSE("GPL v2");
275 MODULE_ALIAS("platform:pwm-rcar");