1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
12 #include <linux/of_address.h>
13 #include <linux/platform_device.h>
14 #include <linux/pwm.h>
15 #include <linux/slab.h>
16 #include <linux/stmp_device.h>
23 #define PWM_ACTIVE0 0x10
24 #define PWM_PERIOD0 0x20
25 #define PERIOD_PERIOD(p) ((p) & 0xffff)
26 #define PERIOD_PERIOD_MAX 0x10000
27 #define PERIOD_ACTIVE_HIGH (3 << 16)
28 #define PERIOD_INACTIVE_LOW (2 << 18)
29 #define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
30 #define PERIOD_CDIV(div) (((div) & 0x7) << 20)
31 #define PERIOD_CDIV_MAX 8
33 static const unsigned int cdiv[PERIOD_CDIV_MAX] = {
34 1, 2, 4, 8, 16, 64, 256, 1024
43 #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
45 static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
46 const struct pwm_state *state)
48 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
50 unsigned int period_cycles, duty_cycles;
54 if (state->polarity != PWM_POLARITY_NORMAL)
58 * If the PWM channel is disabled, make sure to turn on the
59 * clock before calling clk_get_rate() and writing to the
60 * registers. Otherwise, just keep it enabled.
62 if (!pwm_is_enabled(pwm)) {
63 ret = clk_prepare_enable(mxs->clk);
68 if (!state->enabled && pwm_is_enabled(pwm))
69 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
71 rate = clk_get_rate(mxs->clk);
74 c = c * state->period;
75 do_div(c, 1000000000);
76 if (c < PERIOD_PERIOD_MAX)
79 if (div >= PERIOD_CDIV_MAX)
84 c *= state->duty_cycle;
85 do_div(c, state->period);
89 * The data sheet the says registers must be written to in
90 * this order (ACTIVEn, then PERIODn). Also, the new settings
91 * only take effect at the beginning of a new period, avoiding
94 writel(duty_cycles << 16,
95 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
96 writel(PERIOD_PERIOD(period_cycles) | PERIOD_POLARITY_NORMAL | PERIOD_CDIV(div),
97 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
100 if (!pwm_is_enabled(pwm)) {
102 * The clock was enabled above. Just enable
103 * the channel in the control register.
105 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
108 clk_disable_unprepare(mxs->clk);
113 static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
114 int duty_ns, int period_ns)
116 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
118 unsigned int period_cycles, duty_cycles;
120 unsigned long long c;
122 rate = clk_get_rate(mxs->clk);
124 c = rate / cdiv[div];
126 do_div(c, 1000000000);
127 if (c < PERIOD_PERIOD_MAX)
130 if (div >= PERIOD_CDIV_MAX)
136 do_div(c, period_ns);
140 * If the PWM channel is disabled, make sure to turn on the clock
141 * before writing the register. Otherwise, keep it enabled.
143 if (!pwm_is_enabled(pwm)) {
144 ret = clk_prepare_enable(mxs->clk);
149 writel(duty_cycles << 16,
150 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
151 writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
152 PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
153 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
156 * If the PWM is not enabled, turn the clock off again to save power.
158 if (!pwm_is_enabled(pwm))
159 clk_disable_unprepare(mxs->clk);
164 static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
166 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
169 ret = clk_prepare_enable(mxs->clk);
173 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
178 static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
180 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
182 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
184 clk_disable_unprepare(mxs->clk);
187 static const struct pwm_ops mxs_pwm_ops = {
188 .apply = mxs_pwm_apply,
189 .config = mxs_pwm_config,
190 .enable = mxs_pwm_enable,
191 .disable = mxs_pwm_disable,
192 .owner = THIS_MODULE,
195 static int mxs_pwm_probe(struct platform_device *pdev)
197 struct device_node *np = pdev->dev.of_node;
198 struct mxs_pwm_chip *mxs;
201 mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
205 mxs->base = devm_platform_ioremap_resource(pdev, 0);
206 if (IS_ERR(mxs->base))
207 return PTR_ERR(mxs->base);
209 mxs->clk = devm_clk_get(&pdev->dev, NULL);
210 if (IS_ERR(mxs->clk))
211 return PTR_ERR(mxs->clk);
213 mxs->chip.dev = &pdev->dev;
214 mxs->chip.ops = &mxs_pwm_ops;
217 ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
219 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
223 ret = pwmchip_add(&mxs->chip);
225 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
229 platform_set_drvdata(pdev, mxs);
231 ret = stmp_reset_block(mxs->base);
238 pwmchip_remove(&mxs->chip);
242 static int mxs_pwm_remove(struct platform_device *pdev)
244 struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
246 return pwmchip_remove(&mxs->chip);
249 static const struct of_device_id mxs_pwm_dt_ids[] = {
250 { .compatible = "fsl,imx23-pwm", },
253 MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
255 static struct platform_driver mxs_pwm_driver = {
258 .of_match_table = mxs_pwm_dt_ids,
260 .probe = mxs_pwm_probe,
261 .remove = mxs_pwm_remove,
263 module_platform_driver(mxs_pwm_driver);
265 MODULE_ALIAS("platform:mxs-pwm");
266 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
267 MODULE_DESCRIPTION("Freescale MXS PWM Driver");
268 MODULE_LICENSE("GPL v2");