drivers/pwm/pwm-mediatek.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek Pulse Width Modulator driver
   4  *
   5  * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
   6  * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
   7  *
   8  */
   9
  10 #include <linux/err.h>
  11 #include <linux/io.h>
  12 #include <linux/ioport.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pwm.h>
  20 #include <linux/slab.h>
  21 #include <linux/types.h>
  22
  23 /* PWM registers and bits definitions */
  24 #define PWMCON                  0x00
  25 #define PWMHDUR                 0x04
  26 #define PWMLDUR                 0x08
  27 #define PWMGDUR                 0x0c
  28 #define PWMWAVENUM              0x28
  29 #define PWMDWIDTH               0x2c
  30 #define PWM45DWIDTH_FIXUP       0x30
  31 #define PWMTHRES                0x30
  32 #define PWM45THRES_FIXUP        0x34
  33
  34 #define PWM_CLK_DIV_MAX         7
  35
  36 struct pwm_mediatek_of_data {
  37         unsigned int num_pwms;
  38         bool pwm45_fixup;
  39 };
  40
  41 /**
  42  * struct pwm_mediatek_chip - struct representing PWM chip
  43  * @chip: linux PWM chip representation
  44  * @regs: base address of PWM chip
  45  * @clk_top: the top clock generator
  46  * @clk_main: the clock used by PWM core
  47  * @clk_pwms: the clock used by each PWM channel
  48  * @clk_freq: the fix clock frequency of legacy MIPS SoC
  49  * @soc: pointer to chip's platform data
  50  */
  51 struct pwm_mediatek_chip {
  52         struct pwm_chip chip;
  53         void __iomem *regs;
  54         struct clk *clk_top;
  55         struct clk *clk_main;
  56         struct clk **clk_pwms;
  57         const struct pwm_mediatek_of_data *soc;
  58 };
  59
  60 static const unsigned int pwm_mediatek_reg_offset[] = {
  61         0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
  62 };
  63
  64 static inline struct pwm_mediatek_chip *
  65 to_pwm_mediatek_chip(struct pwm_chip *chip)
  66 {
  67         return container_of(chip, struct pwm_mediatek_chip, chip);
  68 }
  69
  70 static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
  71                                    struct pwm_device *pwm)
  72 {
  73         struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
  74         int ret;
  75
  76         ret = clk_prepare_enable(pc->clk_top);
  77         if (ret < 0)
  78                 return ret;
  79
  80         ret = clk_prepare_enable(pc->clk_main);
  81         if (ret < 0)
  82                 goto disable_clk_top;
  83
  84         ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
  85         if (ret < 0)
  86                 goto disable_clk_main;
  87
  88         return 0;
  89
  90 disable_clk_main:
  91         clk_disable_unprepare(pc->clk_main);
  92 disable_clk_top:
  93         clk_disable_unprepare(pc->clk_top);
  94
  95         return ret;
  96 }
  97
  98 static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
  99                                      struct pwm_device *pwm)
 100 {
 101         struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
 102
 103         clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
 104         clk_disable_unprepare(pc->clk_main);
 105         clk_disable_unprepare(pc->clk_top);
 106 }
 107
 108 static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
 109                                      unsigned int num, unsigned int offset)
 110 {
 111         return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
 112 }
 113
 114 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
 115                                        unsigned int num, unsigned int offset,
 116                                        u32 value)
 117 {
 118         writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
 119 }
 120
 121 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
 122                                int duty_ns, int period_ns)
 123 {
 124         struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
 125         u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
 126             reg_thres = PWMTHRES;
 127         u64 resolution;
 128         int ret;
 129
 130         ret = pwm_mediatek_clk_enable(chip, pwm);
 131
 132         if (ret < 0)
 133                 return ret;
 134
 135         /* Using resolution in picosecond gets accuracy higher */
 136         resolution = (u64)NSEC_PER_SEC * 1000;
 137         do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
 138
 139         cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
 140         while (cnt_period > 8191) {
 141                 resolution *= 2;
 142                 clkdiv++;
 143                 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
 144                                                    resolution);
 145         }
 146
 147         if (clkdiv > PWM_CLK_DIV_MAX) {
 148                 pwm_mediatek_clk_disable(chip, pwm);
 149                 dev_err(chip->dev, "period %d not supported\n", period_ns);
 150                 return -EINVAL;
 151         }
 152
 153         if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
 154                 /*
 155                  * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
 156                  * from the other PWMs on MT7623.
 157                  */
 158                 reg_width = PWM45DWIDTH_FIXUP;
 159                 reg_thres = PWM45THRES_FIXUP;
 160         }
 161
 162         cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
 163         pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
 164         pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
 165         pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
 166
 167         pwm_mediatek_clk_disable(chip, pwm);
 168
 169         return 0;
 170 }
 171
 172 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 173 {
 174         struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
 175         u32 value;
 176         int ret;
 177
 178         ret = pwm_mediatek_clk_enable(chip, pwm);
 179         if (ret < 0)
 180                 return ret;
 181
 182         value = readl(pc->regs);
 183         value |= BIT(pwm->hwpwm);
 184         writel(value, pc->regs);
 185
 186         return 0;
 187 }
 188
 189 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 190 {
 191         struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
 192         u32 value;
 193
 194         value = readl(pc->regs);
 195         value &= ~BIT(pwm->hwpwm);
 196         writel(value, pc->regs);
 197
 198         pwm_mediatek_clk_disable(chip, pwm);
 199 }
 200
 201 static const struct pwm_ops pwm_mediatek_ops = {
 202         .config = pwm_mediatek_config,
 203         .enable = pwm_mediatek_enable,
 204         .disable = pwm_mediatek_disable,
 205         .owner = THIS_MODULE,
 206 };
 207
 208 static int pwm_mediatek_probe(struct platform_device *pdev)
 209 {
 210         struct pwm_mediatek_chip *pc;
 211         struct resource *res;
 212         unsigned int i;
 213         int ret;
 214
 215         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 216         if (!pc)
 217                 return -ENOMEM;
 218
 219         pc->soc = of_device_get_match_data(&pdev->dev);
 220
 221         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 222         pc->regs = devm_ioremap_resource(&pdev->dev, res);
 223         if (IS_ERR(pc->regs))
 224                 return PTR_ERR(pc->regs);
 225
 226         pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
 227                                     sizeof(*pc->clk_pwms), GFP_KERNEL);
 228         if (!pc->clk_pwms)
 229                 return -ENOMEM;
 230
 231         pc->clk_top = devm_clk_get(&pdev->dev, "top");
 232         if (IS_ERR(pc->clk_top)) {
 233                 dev_err(&pdev->dev, "clock: top fail: %ld\n",
 234                         PTR_ERR(pc->clk_top));
 235                 return PTR_ERR(pc->clk_top);
 236         }
 237
 238         pc->clk_main = devm_clk_get(&pdev->dev, "main");
 239         if (IS_ERR(pc->clk_main)) {
 240                 dev_err(&pdev->dev, "clock: main fail: %ld\n",
 241                         PTR_ERR(pc->clk_main));
 242                 return PTR_ERR(pc->clk_main);
 243         }
 244
 245         for (i = 0; i < pc->soc->num_pwms; i++) {
 246                 char name[8];
 247
 248                 snprintf(name, sizeof(name), "pwm%d", i + 1);
 249
 250                 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
 251                 if (IS_ERR(pc->clk_pwms[i])) {
 252                         dev_err(&pdev->dev, "clock: %s fail: %ld\n",
 253                                 name, PTR_ERR(pc->clk_pwms[i]));
 254                         return PTR_ERR(pc->clk_pwms[i]);
 255                 }
 256         }
 257
 258         platform_set_drvdata(pdev, pc);
 259
 260         pc->chip.dev = &pdev->dev;
 261         pc->chip.ops = &pwm_mediatek_ops;
 262         pc->chip.base = -1;
 263         pc->chip.npwm = pc->soc->num_pwms;
 264
 265         ret = pwmchip_add(&pc->chip);
 266         if (ret < 0) {
 267                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 268                 return ret;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static int pwm_mediatek_remove(struct platform_device *pdev)
 275 {
 276         struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
 277
 278         return pwmchip_remove(&pc->chip);
 279 }
 280
 281 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
 282         .num_pwms = 8,
 283         .pwm45_fixup = false,
 284 };
 285
 286 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
 287         .num_pwms = 6,
 288         .pwm45_fixup = false,
 289 };
 290
 291 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
 292         .num_pwms = 5,
 293         .pwm45_fixup = true,
 294 };
 295
 296 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
 297         .num_pwms = 4,
 298         .pwm45_fixup = true,
 299 };
 300
 301 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
 302         .num_pwms = 1,
 303         .pwm45_fixup = false,
 304 };
 305
 306 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 307         .num_pwms = 5,
 308         .pwm45_fixup = false,
 309 };
 310
 311 static const struct of_device_id pwm_mediatek_of_match[] = {
 312         { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
 313         { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
 314         { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
 315         { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
 316         { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
 317         { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
 318         { },
 319 };
 320 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
 321
 322 static struct platform_driver pwm_mediatek_driver = {
 323         .driver = {
 324                 .name = "pwm-mediatek",
 325                 .of_match_table = pwm_mediatek_of_match,
 326         },
 327         .probe = pwm_mediatek_probe,
 328         .remove = pwm_mediatek_remove,
 329 };
 330 module_platform_driver(pwm_mediatek_driver);
 331
 332 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 333 MODULE_LICENSE("GPL v2");