drivers/pwm/pwm-lpss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Intel Low Power Subsystem PWM controller driver
   4  *
   5  * Copyright (C) 2014, Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  * Author: Chew Kean Ho <kean.ho.chew@intel.com>
   8  * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
   9  * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
  10  * Author: Alan Cox <alan@linux.intel.com>
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/time.h>
  20
  21 #include "pwm-lpss.h"
  22
  23 #define PWM                             0x00000000
  24 #define PWM_ENABLE                      BIT(31)
  25 #define PWM_SW_UPDATE                   BIT(30)
  26 #define PWM_BASE_UNIT_SHIFT             8
  27 #define PWM_ON_TIME_DIV_MASK            0x000000ff
  28
  29 /* Size of each PWM register space if multiple */
  30 #define PWM_SIZE                        0x400
  31
  32 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
  33 {
  34         return container_of(chip, struct pwm_lpss_chip, chip);
  35 }
  36
  37 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
  38 {
  39         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  40
  41         return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  42 }
  43
  44 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
  45 {
  46         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  47
  48         writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  49 }
  50
  51 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
  52 {
  53         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  54         const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
  55         const unsigned int ms = 500 * USEC_PER_MSEC;
  56         u32 val;
  57         int err;
  58
  59         /*
  60          * PWM Configuration register has SW_UPDATE bit that is set when a new
  61          * configuration is written to the register. The bit is automatically
  62          * cleared at the start of the next output cycle by the IP block.
  63          *
  64          * If one writes a new configuration to the register while it still has
  65          * the bit enabled, PWM may freeze. That is, while one can still write
  66          * to the register, it won't have an effect. Thus, we try to sleep long
  67          * enough that the bit gets cleared and make sure the bit is not
  68          * enabled while we update the configuration.
  69          */
  70         err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
  71         if (err)
  72                 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
  73
  74         return err;
  75 }
  76
  77 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
  78 {
  79         return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
  80 }
  81
  82 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
  83                              int duty_ns, int period_ns)
  84 {
  85         unsigned long long on_time_div;
  86         unsigned long c = lpwm->info->clk_rate, base_unit_range;
  87         unsigned long long base_unit, freq = NSEC_PER_SEC;
  88         u32 orig_ctrl, ctrl;
  89
  90         do_div(freq, period_ns);
  91
  92         /*
  93          * The equation is:
  94          * base_unit = round(base_unit_range * freq / c)
  95          */
  96         base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
  97         freq *= base_unit_range;
  98
  99         base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
 100
 101         on_time_div = 255ULL * duty_ns;
 102         do_div(on_time_div, period_ns);
 103         on_time_div = 255ULL - on_time_div;
 104
 105         orig_ctrl = ctrl = pwm_lpss_read(pwm);
 106         ctrl &= ~PWM_ON_TIME_DIV_MASK;
 107         ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
 108         base_unit &= base_unit_range;
 109         ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
 110         ctrl |= on_time_div;
 111
 112         if (orig_ctrl != ctrl) {
 113                 pwm_lpss_write(pwm, ctrl);
 114                 pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
 115         }
 116 }
 117
 118 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
 119 {
 120         if (cond)
 121                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
 122 }
 123
 124 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 125                           const struct pwm_state *state)
 126 {
 127         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
 128         int ret;
 129
 130         if (state->enabled) {
 131                 if (!pwm_is_enabled(pwm)) {
 132                         pm_runtime_get_sync(chip->dev);
 133                         ret = pwm_lpss_is_updating(pwm);
 134                         if (ret) {
 135                                 pm_runtime_put(chip->dev);
 136                                 return ret;
 137                         }
 138                         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
 139                         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
 140                         ret = pwm_lpss_wait_for_update(pwm);
 141                         if (ret) {
 142                                 pm_runtime_put(chip->dev);
 143                                 return ret;
 144                         }
 145                         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
 146                 } else {
 147                         ret = pwm_lpss_is_updating(pwm);
 148                         if (ret)
 149                                 return ret;
 150                         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
 151                         return pwm_lpss_wait_for_update(pwm);
 152                 }
 153         } else if (pwm_is_enabled(pwm)) {
 154                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
 155                 pm_runtime_put(chip->dev);
 156         }
 157
 158         return 0;
 159 }
 160
 161 static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 162                                struct pwm_state *state)
 163 {
 164         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
 165         unsigned long base_unit_range;
 166         unsigned long long base_unit, freq, on_time_div;
 167         u32 ctrl;
 168
 169         pm_runtime_get_sync(chip->dev);
 170
 171         base_unit_range = BIT(lpwm->info->base_unit_bits);
 172
 173         ctrl = pwm_lpss_read(pwm);
 174         on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
 175         base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
 176
 177         freq = base_unit * lpwm->info->clk_rate;
 178         do_div(freq, base_unit_range);
 179         if (freq == 0)
 180                 state->period = NSEC_PER_SEC;
 181         else
 182                 state->period = NSEC_PER_SEC / (unsigned long)freq;
 183
 184         on_time_div *= state->period;
 185         do_div(on_time_div, 255);
 186         state->duty_cycle = on_time_div;
 187
 188         state->polarity = PWM_POLARITY_NORMAL;
 189         state->enabled = !!(ctrl & PWM_ENABLE);
 190
 191         pm_runtime_put(chip->dev);
 192 }
 193
 194 static const struct pwm_ops pwm_lpss_ops = {
 195         .apply = pwm_lpss_apply,
 196         .get_state = pwm_lpss_get_state,
 197         .owner = THIS_MODULE,
 198 };
 199
 200 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
 201                                      const struct pwm_lpss_boardinfo *info)
 202 {
 203         struct pwm_lpss_chip *lpwm;
 204         unsigned long c;
 205         int i, ret;
 206         u32 ctrl;
 207
 208         if (WARN_ON(info->npwm > MAX_PWMS))
 209                 return ERR_PTR(-ENODEV);
 210
 211         lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
 212         if (!lpwm)
 213                 return ERR_PTR(-ENOMEM);
 214
 215         lpwm->regs = devm_ioremap_resource(dev, r);
 216         if (IS_ERR(lpwm->regs))
 217                 return ERR_CAST(lpwm->regs);
 218
 219         lpwm->info = info;
 220
 221         c = lpwm->info->clk_rate;
 222         if (!c)
 223                 return ERR_PTR(-EINVAL);
 224
 225         lpwm->chip.dev = dev;
 226         lpwm->chip.ops = &pwm_lpss_ops;
 227         lpwm->chip.base = -1;
 228         lpwm->chip.npwm = info->npwm;
 229
 230         ret = pwmchip_add(&lpwm->chip);
 231         if (ret) {
 232                 dev_err(dev, "failed to add PWM chip: %d\n", ret);
 233                 return ERR_PTR(ret);
 234         }
 235
 236         for (i = 0; i < lpwm->info->npwm; i++) {
 237                 ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
 238                 if (ctrl & PWM_ENABLE)
 239                         pm_runtime_get(dev);
 240         }
 241
 242         return lpwm;
 243 }
 244 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
 245
 246 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
 247 {
 248         int i;
 249
 250         for (i = 0; i < lpwm->info->npwm; i++) {
 251                 if (pwm_is_enabled(&lpwm->chip.pwms[i]))
 252                         pm_runtime_put(lpwm->chip.dev);
 253         }
 254         return pwmchip_remove(&lpwm->chip);
 255 }
 256 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
 257
 258 int pwm_lpss_suspend(struct device *dev)
 259 {
 260         struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
 261         int i;
 262
 263         for (i = 0; i < lpwm->info->npwm; i++)
 264                 lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
 265
 266         return 0;
 267 }
 268 EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
 269
 270 int pwm_lpss_resume(struct device *dev)
 271 {
 272         struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
 273         int i;
 274
 275         for (i = 0; i < lpwm->info->npwm; i++)
 276                 writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
 277
 278         return 0;
 279 }
 280 EXPORT_SYMBOL_GPL(pwm_lpss_resume);
 281
 282 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
 283 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 284 MODULE_LICENSE("GPL v2");