drivers/pwm/pwm-imx27.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * simple driver for PWM (Pulse Width Modulator) controller
   4  *
   5  * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
   6  *
   7  * Limitations:
   8  * - When disabled the output is driven to 0 independent of the configured
   9  *   polarity.
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/bitops.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pwm.h>
  24 #include <linux/slab.h>
  25
  26 #define MX3_PWMCR                       0x00    /* PWM Control Register */
  27 #define MX3_PWMSR                       0x04    /* PWM Status Register */
  28 #define MX3_PWMSAR                      0x0C    /* PWM Sample Register */
  29 #define MX3_PWMPR                       0x10    /* PWM Period Register */
  30
  31 #define MX3_PWMCR_FWM                   GENMASK(27, 26)
  32 #define MX3_PWMCR_STOPEN                BIT(25)
  33 #define MX3_PWMCR_DOZEN                 BIT(24)
  34 #define MX3_PWMCR_WAITEN                BIT(23)
  35 #define MX3_PWMCR_DBGEN                 BIT(22)
  36 #define MX3_PWMCR_BCTR                  BIT(21)
  37 #define MX3_PWMCR_HCTR                  BIT(20)
  38
  39 #define MX3_PWMCR_POUTC                 GENMASK(19, 18)
  40 #define MX3_PWMCR_POUTC_NORMAL          0
  41 #define MX3_PWMCR_POUTC_INVERTED        1
  42 #define MX3_PWMCR_POUTC_OFF             2
  43
  44 #define MX3_PWMCR_CLKSRC                GENMASK(17, 16)
  45 #define MX3_PWMCR_CLKSRC_OFF            0
  46 #define MX3_PWMCR_CLKSRC_IPG            1
  47 #define MX3_PWMCR_CLKSRC_IPG_HIGH       2
  48 #define MX3_PWMCR_CLKSRC_IPG_32K        3
  49
  50 #define MX3_PWMCR_PRESCALER             GENMASK(15, 4)
  51
  52 #define MX3_PWMCR_SWR                   BIT(3)
  53
  54 #define MX3_PWMCR_REPEAT                GENMASK(2, 1)
  55 #define MX3_PWMCR_REPEAT_1X             0
  56 #define MX3_PWMCR_REPEAT_2X             1
  57 #define MX3_PWMCR_REPEAT_4X             2
  58 #define MX3_PWMCR_REPEAT_8X             3
  59
  60 #define MX3_PWMCR_EN                    BIT(0)
  61
  62 #define MX3_PWMSR_FWE                   BIT(6)
  63 #define MX3_PWMSR_CMP                   BIT(5)
  64 #define MX3_PWMSR_ROV                   BIT(4)
  65 #define MX3_PWMSR_FE                    BIT(3)
  66
  67 #define MX3_PWMSR_FIFOAV                GENMASK(2, 0)
  68 #define MX3_PWMSR_FIFOAV_EMPTY          0
  69 #define MX3_PWMSR_FIFOAV_1WORD          1
  70 #define MX3_PWMSR_FIFOAV_2WORDS         2
  71 #define MX3_PWMSR_FIFOAV_3WORDS         3
  72 #define MX3_PWMSR_FIFOAV_4WORDS         4
  73
  74 #define MX3_PWMCR_PRESCALER_SET(x)      FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
  75 #define MX3_PWMCR_PRESCALER_GET(x)      (FIELD_GET(MX3_PWMCR_PRESCALER, \
  76                                                    (x)) + 1)
  77
  78 #define MX3_PWM_SWR_LOOP                5
  79
  80 /* PWMPR register value of 0xffff has the same effect as 0xfffe */
  81 #define MX3_PWMPR_MAX                   0xfffe
  82
  83 struct pwm_imx27_chip {
  84         struct clk      *clk_ipg;
  85         struct clk      *clk_per;
  86         void __iomem    *mmio_base;
  87         struct pwm_chip chip;
  88
  89         /*
  90          * The driver cannot read the current duty cycle from the hardware if
  91          * the hardware is disabled. Cache the last programmed duty cycle
  92          * value to return in that case.
  93          */
  94         unsigned int duty_cycle;
  95 };
  96
  97 #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
  98
  99 static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
 100 {
 101         int ret;
 102
 103         ret = clk_prepare_enable(imx->clk_ipg);
 104         if (ret)
 105                 return ret;
 106
 107         ret = clk_prepare_enable(imx->clk_per);
 108         if (ret) {
 109                 clk_disable_unprepare(imx->clk_ipg);
 110                 return ret;
 111         }
 112
 113         return 0;
 114 }
 115
 116 static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
 117 {
 118         clk_disable_unprepare(imx->clk_per);
 119         clk_disable_unprepare(imx->clk_ipg);
 120 }
 121
 122 static void pwm_imx27_get_state(struct pwm_chip *chip,
 123                                 struct pwm_device *pwm, struct pwm_state *state)
 124 {
 125         struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
 126         u32 period, prescaler, pwm_clk, val;
 127         u64 tmp;
 128         int ret;
 129
 130         ret = pwm_imx27_clk_prepare_enable(imx);
 131         if (ret < 0)
 132                 return;
 133
 134         val = readl(imx->mmio_base + MX3_PWMCR);
 135
 136         if (val & MX3_PWMCR_EN)
 137                 state->enabled = true;
 138         else
 139                 state->enabled = false;
 140
 141         switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
 142         case MX3_PWMCR_POUTC_NORMAL:
 143                 state->polarity = PWM_POLARITY_NORMAL;
 144                 break;
 145         case MX3_PWMCR_POUTC_INVERTED:
 146                 state->polarity = PWM_POLARITY_INVERSED;
 147                 break;
 148         default:
 149                 dev_warn(chip->dev, "can't set polarity, output disconnected");
 150         }
 151
 152         prescaler = MX3_PWMCR_PRESCALER_GET(val);
 153         pwm_clk = clk_get_rate(imx->clk_per);
 154         pwm_clk = DIV_ROUND_CLOSEST_ULL(pwm_clk, prescaler);
 155         val = readl(imx->mmio_base + MX3_PWMPR);
 156         period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
 157
 158         /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
 159         tmp = NSEC_PER_SEC * (u64)(period + 2);
 160         state->period = DIV_ROUND_CLOSEST_ULL(tmp, pwm_clk);
 161
 162         /*
 163          * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
 164          * use the cached value.
 165          */
 166         if (state->enabled)
 167                 val = readl(imx->mmio_base + MX3_PWMSAR);
 168         else
 169                 val = imx->duty_cycle;
 170
 171         tmp = NSEC_PER_SEC * (u64)(val);
 172         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pwm_clk);
 173
 174         pwm_imx27_clk_disable_unprepare(imx);
 175 }
 176
 177 static void pwm_imx27_sw_reset(struct pwm_chip *chip)
 178 {
 179         struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
 180         struct device *dev = chip->dev;
 181         int wait_count = 0;
 182         u32 cr;
 183
 184         writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
 185         do {
 186                 usleep_range(200, 1000);
 187                 cr = readl(imx->mmio_base + MX3_PWMCR);
 188         } while ((cr & MX3_PWMCR_SWR) &&
 189                  (wait_count++ < MX3_PWM_SWR_LOOP));
 190
 191         if (cr & MX3_PWMCR_SWR)
 192                 dev_warn(dev, "software reset timeout\n");
 193 }
 194
 195 static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
 196                                      struct pwm_device *pwm)
 197 {
 198         struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
 199         struct device *dev = chip->dev;
 200         unsigned int period_ms;
 201         int fifoav;
 202         u32 sr;
 203
 204         sr = readl(imx->mmio_base + MX3_PWMSR);
 205         fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
 206         if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
 207                 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
 208                                          NSEC_PER_MSEC);
 209                 msleep(period_ms);
 210
 211                 sr = readl(imx->mmio_base + MX3_PWMSR);
 212                 if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
 213                         dev_warn(dev, "there is no free FIFO slot\n");
 214         }
 215 }
 216
 217 static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 218                            const struct pwm_state *state)
 219 {
 220         unsigned long period_cycles, duty_cycles, prescale;
 221         struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
 222         struct pwm_state cstate;
 223         unsigned long long c;
 224         int ret;
 225         u32 cr;
 226
 227         pwm_get_state(pwm, &cstate);
 228
 229         c = clk_get_rate(imx->clk_per);
 230         c *= state->period;
 231
 232         do_div(c, 1000000000);
 233         period_cycles = c;
 234
 235         prescale = period_cycles / 0x10000 + 1;
 236
 237         period_cycles /= prescale;
 238         c = (unsigned long long)period_cycles * state->duty_cycle;
 239         do_div(c, state->period);
 240         duty_cycles = c;
 241
 242         /*
 243          * according to imx pwm RM, the real period value should be PERIOD
 244          * value in PWMPR plus 2.
 245          */
 246         if (period_cycles > 2)
 247                 period_cycles -= 2;
 248         else
 249                 period_cycles = 0;
 250
 251         /*
 252          * Wait for a free FIFO slot if the PWM is already enabled, and flush
 253          * the FIFO if the PWM was disabled and is about to be enabled.
 254          */
 255         if (cstate.enabled) {
 256                 pwm_imx27_wait_fifo_slot(chip, pwm);
 257         } else {
 258                 ret = pwm_imx27_clk_prepare_enable(imx);
 259                 if (ret)
 260                         return ret;
 261
 262                 pwm_imx27_sw_reset(chip);
 263         }
 264
 265         writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
 266         writel(period_cycles, imx->mmio_base + MX3_PWMPR);
 267
 268         /*
 269          * Store the duty cycle for future reference in cases where the
 270          * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
 271          */
 272         imx->duty_cycle = duty_cycles;
 273
 274         cr = MX3_PWMCR_PRESCALER_SET(prescale) |
 275              MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
 276              FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
 277              MX3_PWMCR_DBGEN;
 278
 279         if (state->polarity == PWM_POLARITY_INVERSED)
 280                 cr |= FIELD_PREP(MX3_PWMCR_POUTC,
 281                                 MX3_PWMCR_POUTC_INVERTED);
 282
 283         if (state->enabled)
 284                 cr |= MX3_PWMCR_EN;
 285
 286         writel(cr, imx->mmio_base + MX3_PWMCR);
 287
 288         if (!state->enabled)
 289                 pwm_imx27_clk_disable_unprepare(imx);
 290
 291         return 0;
 292 }
 293
 294 static const struct pwm_ops pwm_imx27_ops = {
 295         .apply = pwm_imx27_apply,
 296         .get_state = pwm_imx27_get_state,
 297         .owner = THIS_MODULE,
 298 };
 299
 300 static const struct of_device_id pwm_imx27_dt_ids[] = {
 301         { .compatible = "fsl,imx27-pwm", },
 302         { /* sentinel */ }
 303 };
 304 MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
 305
 306 static int pwm_imx27_probe(struct platform_device *pdev)
 307 {
 308         struct pwm_imx27_chip *imx;
 309         int ret;
 310         u32 pwmcr;
 311
 312         imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
 313         if (imx == NULL)
 314                 return -ENOMEM;
 315
 316         platform_set_drvdata(pdev, imx);
 317
 318         imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 319         if (IS_ERR(imx->clk_ipg)) {
 320                 int ret = PTR_ERR(imx->clk_ipg);
 321
 322                 if (ret != -EPROBE_DEFER)
 323                         dev_err(&pdev->dev,
 324                                 "getting ipg clock failed with %d\n",
 325                                 ret);
 326                 return ret;
 327         }
 328
 329         imx->clk_per = devm_clk_get(&pdev->dev, "per");
 330         if (IS_ERR(imx->clk_per)) {
 331                 int ret = PTR_ERR(imx->clk_per);
 332
 333                 if (ret != -EPROBE_DEFER)
 334                         dev_err(&pdev->dev,
 335                                 "failed to get peripheral clock: %d\n",
 336                                 ret);
 337
 338                 return ret;
 339         }
 340
 341         imx->chip.ops = &pwm_imx27_ops;
 342         imx->chip.dev = &pdev->dev;
 343         imx->chip.base = -1;
 344         imx->chip.npwm = 1;
 345
 346         imx->chip.of_xlate = of_pwm_xlate_with_flags;
 347         imx->chip.of_pwm_n_cells = 3;
 348
 349         imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
 350         if (IS_ERR(imx->mmio_base))
 351                 return PTR_ERR(imx->mmio_base);
 352
 353         ret = pwm_imx27_clk_prepare_enable(imx);
 354         if (ret)
 355                 return ret;
 356
 357         /* keep clks on if pwm is running */
 358         pwmcr = readl(imx->mmio_base + MX3_PWMCR);
 359         if (!(pwmcr & MX3_PWMCR_EN))
 360                 pwm_imx27_clk_disable_unprepare(imx);
 361
 362         return pwmchip_add(&imx->chip);
 363 }
 364
 365 static int pwm_imx27_remove(struct platform_device *pdev)
 366 {
 367         struct pwm_imx27_chip *imx;
 368
 369         imx = platform_get_drvdata(pdev);
 370
 371         return pwmchip_remove(&imx->chip);
 372 }
 373
 374 static struct platform_driver imx_pwm_driver = {
 375         .driver = {
 376                 .name = "pwm-imx27",
 377                 .of_match_table = pwm_imx27_dt_ids,
 378         },
 379         .probe = pwm_imx27_probe,
 380         .remove = pwm_imx27_remove,
 381 };
 382 module_platform_driver(imx_pwm_driver);
 383
 384 MODULE_LICENSE("GPL v2");
 385 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");