1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
9 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pwm.h>
14 #define PWM_CONTROL 0x000
15 #define PWM_CONTROL_SHIFT(x) ((x) * 8)
16 #define PWM_CONTROL_MASK 0xff
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
18 #define PWM_ENABLE (1 << 0)
19 #define PWM_POLARITY (1 << 4)
21 #define PERIOD(x) (((x) * 0x10) + 0x10)
22 #define DUTY(x) (((x) * 0x10) + 0x14)
24 #define PERIOD_MIN 0x2
32 static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
34 return pwmchip_get_drvdata(chip);
37 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
39 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
42 value = readl(pc->base + PWM_CONTROL);
43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
45 writel(value, pc->base + PWM_CONTROL);
50 static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
52 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
55 value = readl(pc->base + PWM_CONTROL);
56 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
57 writel(value, pc->base + PWM_CONTROL);
60 static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
61 const struct pwm_state *state)
64 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
65 unsigned long long period_cycles;
71 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
72 * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
73 * multiplication period * rate doesn't overflow.
74 * To calculate the maximal possible period that guarantees the
77 * round(period * rate / NSEC_PER_SEC) <= U32_MAX
78 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
79 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
80 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
81 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
82 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
84 max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
86 if (state->period > max_period)
90 period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
92 /* don't accept a period that is too small */
93 if (period_cycles < PERIOD_MIN)
96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
99 val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
100 writel(val, pc->base + DUTY(pwm->hwpwm));
103 val = readl(pc->base + PWM_CONTROL);
105 if (state->polarity == PWM_POLARITY_NORMAL)
106 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
108 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
112 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
114 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
116 writel(val, pc->base + PWM_CONTROL);
121 static const struct pwm_ops bcm2835_pwm_ops = {
122 .request = bcm2835_pwm_request,
123 .free = bcm2835_pwm_free,
124 .apply = bcm2835_pwm_apply,
127 static void devm_clk_rate_exclusive_put(void *data)
129 struct clk *clk = data;
131 clk_rate_exclusive_put(clk);
134 static int bcm2835_pwm_probe(struct platform_device *pdev)
136 struct pwm_chip *chip;
137 struct bcm2835_pwm *pc;
140 chip = devm_pwmchip_alloc(&pdev->dev, 2, sizeof(*pc));
142 return PTR_ERR(chip);
143 pc = to_bcm2835_pwm(chip);
145 pc->base = devm_platform_ioremap_resource(pdev, 0);
146 if (IS_ERR(pc->base))
147 return PTR_ERR(pc->base);
149 pc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
151 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
152 "clock not found\n");
154 ret = clk_rate_exclusive_get(pc->clk);
156 return dev_err_probe(&pdev->dev, ret,
157 "fail to get exclusive rate\n");
159 ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put,
164 pc->rate = clk_get_rate(pc->clk);
166 return dev_err_probe(&pdev->dev, -EINVAL,
167 "failed to get clock rate\n");
169 chip->ops = &bcm2835_pwm_ops;
172 platform_set_drvdata(pdev, pc);
174 ret = devm_pwmchip_add(&pdev->dev, chip);
176 return dev_err_probe(&pdev->dev, ret,
177 "failed to add pwmchip\n");
182 static int bcm2835_pwm_suspend(struct device *dev)
184 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
186 clk_disable_unprepare(pc->clk);
191 static int bcm2835_pwm_resume(struct device *dev)
193 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
195 return clk_prepare_enable(pc->clk);
198 static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend,
201 static const struct of_device_id bcm2835_pwm_of_match[] = {
202 { .compatible = "brcm,bcm2835-pwm", },
205 MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
207 static struct platform_driver bcm2835_pwm_driver = {
209 .name = "bcm2835-pwm",
210 .of_match_table = bcm2835_pwm_of_match,
211 .pm = pm_ptr(&bcm2835_pwm_pm_ops),
213 .probe = bcm2835_pwm_probe,
215 module_platform_driver(bcm2835_pwm_driver);
217 MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
218 MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
219 MODULE_LICENSE("GPL v2");