1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel Pulse Width Modulation Controller
5 * Copyright (C) 2013 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
8 * Links to reference manuals for the supported PWM chips can be found in
9 * Documentation/arm/microchip.rst.
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
15 * Software bugs/possible improvements:
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
19 * functionality could be used.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_device.h>
30 #include <linux/platform_device.h>
31 #include <linux/pwm.h>
32 #include <linux/slab.h>
34 /* The following is global registers for PWM controller */
40 #define PWM_SR_ALL_CH_ON 0x0F
42 /* The following register is PWM channel related registers */
43 #define PWM_CH_REG_OFFSET 0x200
44 #define PWM_CH_REG_SIZE 0x20
47 /* Bit field in CMR */
48 #define PWM_CMR_CPOL (1 << 9)
49 #define PWM_CMR_UPD_CDTY (1 << 10)
50 #define PWM_CMR_CPRE_MSK 0xF
52 /* The following registers for PWM v1 */
53 #define PWMV1_CDTY 0x04
54 #define PWMV1_CPRD 0x08
55 #define PWMV1_CUPD 0x10
57 /* The following registers for PWM v2 */
58 #define PWMV2_CDTY 0x04
59 #define PWMV2_CDTYUPD 0x08
60 #define PWMV2_CPRD 0x0C
61 #define PWMV2_CPRDUPD 0x10
63 #define PWM_MAX_PRES 10
65 struct atmel_pwm_registers {
72 struct atmel_pwm_config {
76 struct atmel_pwm_data {
77 struct atmel_pwm_registers regs;
78 struct atmel_pwm_config cfg;
81 struct atmel_pwm_chip {
85 const struct atmel_pwm_data *data;
87 unsigned int updated_pwms;
88 /* ISR is cleared when read, ensure only one thread does that */
89 struct mutex isr_lock;
92 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
94 return container_of(chip, struct atmel_pwm_chip, chip);
97 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
100 return readl_relaxed(chip->base + offset);
103 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
104 unsigned long offset, unsigned long val)
106 writel_relaxed(val, chip->base + offset);
109 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
110 unsigned int ch, unsigned long offset)
112 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
114 return atmel_pwm_readl(chip, base + offset);
117 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
118 unsigned int ch, unsigned long offset,
121 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
123 atmel_pwm_writel(chip, base + offset, val);
126 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
127 const struct pwm_state *state,
128 unsigned long *cprd, u32 *pres)
130 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
131 unsigned long long cycles = state->period;
134 /* Calculate the period cycles and prescale value */
135 cycles *= clk_get_rate(atmel_pwm->clk);
136 do_div(cycles, NSEC_PER_SEC);
139 * The register for the period length is cfg.period_bits bits wide.
140 * So for each bit the number of clock cycles is wider divide the input
141 * clock frequency by two using pres and shift cprd accordingly.
143 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
145 if (shift > PWM_MAX_PRES) {
146 dev_err(chip->dev, "pres exceeds the maximum value\n");
148 } else if (shift > 0) {
160 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
161 unsigned long cprd, unsigned long *cdty)
163 unsigned long long cycles = state->duty_cycle;
166 do_div(cycles, state->period);
167 *cdty = cprd - cycles;
170 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
173 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
176 if (atmel_pwm->data->regs.duty_upd ==
177 atmel_pwm->data->regs.period_upd) {
178 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
179 val &= ~PWM_CMR_UPD_CDTY;
180 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
183 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
184 atmel_pwm->data->regs.duty_upd, cdty);
187 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
188 struct pwm_device *pwm,
189 unsigned long cprd, unsigned long cdty)
191 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
193 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
194 atmel_pwm->data->regs.duty, cdty);
195 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
196 atmel_pwm->data->regs.period, cprd);
199 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
202 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
203 unsigned long timeout = jiffies + 2 * HZ;
206 * Wait for at least a complete period to have passed before disabling a
207 * channel to be sure that CDTY has been updated
209 mutex_lock(&atmel_pwm->isr_lock);
210 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
212 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
213 time_before(jiffies, timeout)) {
214 usleep_range(10, 100);
215 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
218 mutex_unlock(&atmel_pwm->isr_lock);
219 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
222 * Wait for the PWM channel disable operation to be effective before
223 * stopping the clock.
225 timeout = jiffies + 2 * HZ;
227 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
228 time_before(jiffies, timeout))
229 usleep_range(10, 100);
232 clk_disable(atmel_pwm->clk);
235 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
236 const struct pwm_state *state)
238 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
239 struct pwm_state cstate;
240 unsigned long cprd, cdty;
244 pwm_get_state(pwm, &cstate);
246 if (state->enabled) {
247 if (cstate.enabled &&
248 cstate.polarity == state->polarity &&
249 cstate.period == state->period) {
250 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
251 atmel_pwm->data->regs.period);
252 atmel_pwm_calculate_cdty(state, cprd, &cdty);
253 atmel_pwm_update_cdty(chip, pwm, cdty);
257 ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
261 "failed to calculate cprd and prescaler\n");
265 atmel_pwm_calculate_cdty(state, cprd, &cdty);
267 if (cstate.enabled) {
268 atmel_pwm_disable(chip, pwm, false);
270 ret = clk_enable(atmel_pwm->clk);
272 dev_err(chip->dev, "failed to enable clock\n");
277 /* It is necessary to preserve CPOL, inside CMR */
278 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
279 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
280 if (state->polarity == PWM_POLARITY_NORMAL)
281 val &= ~PWM_CMR_CPOL;
284 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
285 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
286 mutex_lock(&atmel_pwm->isr_lock);
287 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
288 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
289 mutex_unlock(&atmel_pwm->isr_lock);
290 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
291 } else if (cstate.enabled) {
292 atmel_pwm_disable(chip, pwm, true);
298 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
299 struct pwm_state *state)
301 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
304 sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
305 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
307 if (sr & (1 << pwm->hwpwm)) {
308 unsigned long rate = clk_get_rate(atmel_pwm->clk);
309 u32 cdty, cprd, pres;
312 pres = cmr & PWM_CMR_CPRE_MSK;
314 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
315 atmel_pwm->data->regs.period);
316 tmp = (u64)cprd * NSEC_PER_SEC;
318 state->period = DIV64_U64_ROUND_UP(tmp, rate);
320 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
321 atmel_pwm->data->regs.duty);
322 tmp = (u64)cdty * NSEC_PER_SEC;
324 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
326 state->enabled = true;
328 state->enabled = false;
331 if (cmr & PWM_CMR_CPOL)
332 state->polarity = PWM_POLARITY_INVERSED;
334 state->polarity = PWM_POLARITY_NORMAL;
337 static const struct pwm_ops atmel_pwm_ops = {
338 .apply = atmel_pwm_apply,
339 .get_state = atmel_pwm_get_state,
340 .owner = THIS_MODULE,
343 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
345 .period = PWMV1_CPRD,
346 .period_upd = PWMV1_CUPD,
348 .duty_upd = PWMV1_CUPD,
351 /* 16 bits to keep period and duty. */
356 static const struct atmel_pwm_data atmel_sama5_pwm_data = {
358 .period = PWMV2_CPRD,
359 .period_upd = PWMV2_CPRDUPD,
361 .duty_upd = PWMV2_CDTYUPD,
364 /* 16 bits to keep period and duty. */
369 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
371 .period = PWMV1_CPRD,
372 .period_upd = PWMV1_CUPD,
374 .duty_upd = PWMV1_CUPD,
377 /* 32 bits to keep period and duty. */
382 static const struct of_device_id atmel_pwm_dt_ids[] = {
384 .compatible = "atmel,at91sam9rl-pwm",
385 .data = &atmel_sam9rl_pwm_data,
387 .compatible = "atmel,sama5d3-pwm",
388 .data = &atmel_sama5_pwm_data,
390 .compatible = "atmel,sama5d2-pwm",
391 .data = &atmel_sama5_pwm_data,
393 .compatible = "microchip,sam9x60-pwm",
394 .data = &mchp_sam9x60_pwm_data,
399 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
401 static int atmel_pwm_probe(struct platform_device *pdev)
403 struct atmel_pwm_chip *atmel_pwm;
406 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
410 mutex_init(&atmel_pwm->isr_lock);
411 atmel_pwm->data = of_device_get_match_data(&pdev->dev);
412 atmel_pwm->updated_pwms = 0;
414 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
415 if (IS_ERR(atmel_pwm->base))
416 return PTR_ERR(atmel_pwm->base);
418 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
419 if (IS_ERR(atmel_pwm->clk))
420 return PTR_ERR(atmel_pwm->clk);
422 ret = clk_prepare(atmel_pwm->clk);
424 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
428 atmel_pwm->chip.dev = &pdev->dev;
429 atmel_pwm->chip.ops = &atmel_pwm_ops;
430 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
431 atmel_pwm->chip.of_pwm_n_cells = 3;
432 atmel_pwm->chip.base = -1;
433 atmel_pwm->chip.npwm = 4;
435 ret = pwmchip_add(&atmel_pwm->chip);
437 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
441 platform_set_drvdata(pdev, atmel_pwm);
446 clk_unprepare(atmel_pwm->clk);
450 static int atmel_pwm_remove(struct platform_device *pdev)
452 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
454 clk_unprepare(atmel_pwm->clk);
455 mutex_destroy(&atmel_pwm->isr_lock);
457 return pwmchip_remove(&atmel_pwm->chip);
460 static struct platform_driver atmel_pwm_driver = {
463 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
465 .probe = atmel_pwm_probe,
466 .remove = atmel_pwm_remove,
468 module_platform_driver(atmel_pwm_driver);
470 MODULE_ALIAS("platform:atmel-pwm");
471 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
472 MODULE_DESCRIPTION("Atmel PWM driver");
473 MODULE_LICENSE("GPL v2");