drivers/pwm/pwm-atmel-tcb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) Overkiz SAS 2012
   4  *
   5  * Author: Boris BREZILLON <b.brezillon@overkiz.com>
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/ioport.h>
  18 #include <linux/io.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pwm.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26 #include <soc/at91/atmel_tcb.h>
  27
  28 #define NPWM    2
  29
  30 #define ATMEL_TC_ACMR_MASK      (ATMEL_TC_ACPA | ATMEL_TC_ACPC |        \
  31                                  ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
  32
  33 #define ATMEL_TC_BCMR_MASK      (ATMEL_TC_BCPB | ATMEL_TC_BCPC |        \
  34                                  ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
  35
  36 struct atmel_tcb_pwm_device {
  37         enum pwm_polarity polarity;     /* PWM polarity */
  38         unsigned div;                   /* PWM clock divider */
  39         unsigned duty;                  /* PWM duty expressed in clk cycles */
  40         unsigned period;                /* PWM period expressed in clk cycles */
  41 };
  42
  43 struct atmel_tcb_channel {
  44         u32 enabled;
  45         u32 cmr;
  46         u32 ra;
  47         u32 rb;
  48         u32 rc;
  49 };
  50
  51 struct atmel_tcb_pwm_chip {
  52         struct pwm_chip chip;
  53         spinlock_t lock;
  54         u8 channel;
  55         u8 width;
  56         struct regmap *regmap;
  57         struct clk *clk;
  58         struct clk *gclk;
  59         struct clk *slow_clk;
  60         struct atmel_tcb_pwm_device *pwms[NPWM];
  61         struct atmel_tcb_channel bkup;
  62 };
  63
  64 const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
  65
  66 static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
  67 {
  68         return container_of(chip, struct atmel_tcb_pwm_chip, chip);
  69 }
  70
  71 static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
  72                                       struct pwm_device *pwm,
  73                                       enum pwm_polarity polarity)
  74 {
  75         struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
  76
  77         tcbpwm->polarity = polarity;
  78
  79         return 0;
  80 }
  81
  82 static int atmel_tcb_pwm_request(struct pwm_chip *chip,
  83                                  struct pwm_device *pwm)
  84 {
  85         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  86         struct atmel_tcb_pwm_device *tcbpwm;
  87         unsigned cmr;
  88         int ret;
  89
  90         tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
  91         if (!tcbpwm)
  92                 return -ENOMEM;
  93
  94         ret = clk_prepare_enable(tcbpwmc->clk);
  95         if (ret) {
  96                 devm_kfree(chip->dev, tcbpwm);
  97                 return ret;
  98         }
  99
 100         pwm_set_chip_data(pwm, tcbpwm);
 101         tcbpwm->polarity = PWM_POLARITY_NORMAL;
 102         tcbpwm->duty = 0;
 103         tcbpwm->period = 0;
 104         tcbpwm->div = 0;
 105
 106         spin_lock(&tcbpwmc->lock);
 107         regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
 108         /*
 109          * Get init config from Timer Counter registers if
 110          * Timer Counter is already configured as a PWM generator.
 111          */
 112         if (cmr & ATMEL_TC_WAVE) {
 113                 if (pwm->hwpwm == 0)
 114                         regmap_read(tcbpwmc->regmap,
 115                                     ATMEL_TC_REG(tcbpwmc->channel, RA),
 116                                     &tcbpwm->duty);
 117                 else
 118                         regmap_read(tcbpwmc->regmap,
 119                                     ATMEL_TC_REG(tcbpwmc->channel, RB),
 120                                     &tcbpwm->duty);
 121
 122                 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
 123                 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
 124                             &tcbpwm->period);
 125                 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
 126                         ATMEL_TC_BCMR_MASK);
 127         } else
 128                 cmr = 0;
 129
 130         cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
 131         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
 132         spin_unlock(&tcbpwmc->lock);
 133
 134         tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
 135
 136         return 0;
 137 }
 138
 139 static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 140 {
 141         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 142         struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
 143
 144         clk_disable_unprepare(tcbpwmc->clk);
 145         tcbpwmc->pwms[pwm->hwpwm] = NULL;
 146         devm_kfree(chip->dev, tcbpwm);
 147 }
 148
 149 static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 150 {
 151         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 152         struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
 153         unsigned cmr;
 154         enum pwm_polarity polarity = tcbpwm->polarity;
 155
 156         /*
 157          * If duty is 0 the timer will be stopped and we have to
 158          * configure the output correctly on software trigger:
 159          *  - set output to high if PWM_POLARITY_INVERSED
 160          *  - set output to low if PWM_POLARITY_NORMAL
 161          *
 162          * This is why we're reverting polarity in this case.
 163          */
 164         if (tcbpwm->duty == 0)
 165                 polarity = !polarity;
 166
 167         spin_lock(&tcbpwmc->lock);
 168         regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
 169
 170         /* flush old setting and set the new one */
 171         if (pwm->hwpwm == 0) {
 172                 cmr &= ~ATMEL_TC_ACMR_MASK;
 173                 if (polarity == PWM_POLARITY_INVERSED)
 174                         cmr |= ATMEL_TC_ASWTRG_CLEAR;
 175                 else
 176                         cmr |= ATMEL_TC_ASWTRG_SET;
 177         } else {
 178                 cmr &= ~ATMEL_TC_BCMR_MASK;
 179                 if (polarity == PWM_POLARITY_INVERSED)
 180                         cmr |= ATMEL_TC_BSWTRG_CLEAR;
 181                 else
 182                         cmr |= ATMEL_TC_BSWTRG_SET;
 183         }
 184
 185         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
 186
 187         /*
 188          * Use software trigger to apply the new setting.
 189          * If both PWM devices in this group are disabled we stop the clock.
 190          */
 191         if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
 192                 regmap_write(tcbpwmc->regmap,
 193                              ATMEL_TC_REG(tcbpwmc->channel, CCR),
 194                              ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
 195                 tcbpwmc->bkup.enabled = 1;
 196         } else {
 197                 regmap_write(tcbpwmc->regmap,
 198                              ATMEL_TC_REG(tcbpwmc->channel, CCR),
 199                              ATMEL_TC_SWTRG);
 200                 tcbpwmc->bkup.enabled = 0;
 201         }
 202
 203         spin_unlock(&tcbpwmc->lock);
 204 }
 205
 206 static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 207 {
 208         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 209         struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
 210         u32 cmr;
 211         enum pwm_polarity polarity = tcbpwm->polarity;
 212
 213         /*
 214          * If duty is 0 the timer will be stopped and we have to
 215          * configure the output correctly on software trigger:
 216          *  - set output to high if PWM_POLARITY_INVERSED
 217          *  - set output to low if PWM_POLARITY_NORMAL
 218          *
 219          * This is why we're reverting polarity in this case.
 220          */
 221         if (tcbpwm->duty == 0)
 222                 polarity = !polarity;
 223
 224         spin_lock(&tcbpwmc->lock);
 225         regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
 226
 227         /* flush old setting and set the new one */
 228         cmr &= ~ATMEL_TC_TCCLKS;
 229
 230         if (pwm->hwpwm == 0) {
 231                 cmr &= ~ATMEL_TC_ACMR_MASK;
 232
 233                 /* Set CMR flags according to given polarity */
 234                 if (polarity == PWM_POLARITY_INVERSED)
 235                         cmr |= ATMEL_TC_ASWTRG_CLEAR;
 236                 else
 237                         cmr |= ATMEL_TC_ASWTRG_SET;
 238         } else {
 239                 cmr &= ~ATMEL_TC_BCMR_MASK;
 240                 if (polarity == PWM_POLARITY_INVERSED)
 241                         cmr |= ATMEL_TC_BSWTRG_CLEAR;
 242                 else
 243                         cmr |= ATMEL_TC_BSWTRG_SET;
 244         }
 245
 246         /*
 247          * If duty is 0 or equal to period there's no need to register
 248          * a specific action on RA/RB and RC compare.
 249          * The output will be configured on software trigger and keep
 250          * this config till next config call.
 251          */
 252         if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
 253                 if (pwm->hwpwm == 0) {
 254                         if (polarity == PWM_POLARITY_INVERSED)
 255                                 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
 256                         else
 257                                 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
 258                 } else {
 259                         if (polarity == PWM_POLARITY_INVERSED)
 260                                 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
 261                         else
 262                                 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
 263                 }
 264         }
 265
 266         cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
 267
 268         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
 269
 270         if (pwm->hwpwm == 0)
 271                 regmap_write(tcbpwmc->regmap,
 272                              ATMEL_TC_REG(tcbpwmc->channel, RA),
 273                              tcbpwm->duty);
 274         else
 275                 regmap_write(tcbpwmc->regmap,
 276                              ATMEL_TC_REG(tcbpwmc->channel, RB),
 277                              tcbpwm->duty);
 278
 279         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
 280                      tcbpwm->period);
 281
 282         /* Use software trigger to apply the new setting */
 283         regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
 284                      ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
 285         tcbpwmc->bkup.enabled = 1;
 286         spin_unlock(&tcbpwmc->lock);
 287         return 0;
 288 }
 289
 290 static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 291                                 int duty_ns, int period_ns)
 292 {
 293         struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
 294         struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
 295         struct atmel_tcb_pwm_device *atcbpwm = NULL;
 296         int i = 0;
 297         int slowclk = 0;
 298         unsigned period;
 299         unsigned duty;
 300         unsigned rate = clk_get_rate(tcbpwmc->clk);
 301         unsigned long long min;
 302         unsigned long long max;
 303
 304         /*
 305          * Find best clk divisor:
 306          * the smallest divisor which can fulfill the period_ns requirements.
 307          * If there is a gclk, the first divisor is actuallly the gclk selector
 308          */
 309         if (tcbpwmc->gclk)
 310                 i = 1;
 311         for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
 312                 if (atmel_tcb_divisors[i] == 0) {
 313                         slowclk = i;
 314                         continue;
 315                 }
 316                 min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
 317                 max = min << tcbpwmc->width;
 318                 if (max >= period_ns)
 319                         break;
 320         }
 321
 322         /*
 323          * If none of the divisor are small enough to represent period_ns
 324          * take slow clock (32KHz).
 325          */
 326         if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
 327                 i = slowclk;
 328                 rate = clk_get_rate(tcbpwmc->slow_clk);
 329                 min = div_u64(NSEC_PER_SEC, rate);
 330                 max = min << tcbpwmc->width;
 331
 332                 /* If period is too big return ERANGE error */
 333                 if (max < period_ns)
 334                         return -ERANGE;
 335         }
 336
 337         duty = div_u64(duty_ns, min);
 338         period = div_u64(period_ns, min);
 339
 340         if (pwm->hwpwm == 0)
 341                 atcbpwm = tcbpwmc->pwms[1];
 342         else
 343                 atcbpwm = tcbpwmc->pwms[0];
 344
 345         /*
 346          * PWM devices provided by the TCB driver are grouped by 2.
 347          * PWM devices in a given group must be configured with the
 348          * same period_ns.
 349          *
 350          * We're checking the period value of the second PWM device
 351          * in this group before applying the new config.
 352          */
 353         if ((atcbpwm && atcbpwm->duty > 0 &&
 354                         atcbpwm->duty != atcbpwm->period) &&
 355                 (atcbpwm->div != i || atcbpwm->period != period)) {
 356                 dev_err(chip->dev,
 357                         "failed to configure period_ns: PWM group already configured with a different value\n");
 358                 return -EINVAL;
 359         }
 360
 361         tcbpwm->period = period;
 362         tcbpwm->div = i;
 363         tcbpwm->duty = duty;
 364
 365         /* If the PWM is enabled, call enable to apply the new conf */
 366         if (pwm_is_enabled(pwm))
 367                 atmel_tcb_pwm_enable(chip, pwm);
 368
 369         return 0;
 370 }
 371
 372 static const struct pwm_ops atmel_tcb_pwm_ops = {
 373         .request = atmel_tcb_pwm_request,
 374         .free = atmel_tcb_pwm_free,
 375         .config = atmel_tcb_pwm_config,
 376         .set_polarity = atmel_tcb_pwm_set_polarity,
 377         .enable = atmel_tcb_pwm_enable,
 378         .disable = atmel_tcb_pwm_disable,
 379         .owner = THIS_MODULE,
 380 };
 381
 382 static struct atmel_tcb_config tcb_rm9200_config = {
 383         .counter_width = 16,
 384 };
 385
 386 static struct atmel_tcb_config tcb_sam9x5_config = {
 387         .counter_width = 32,
 388 };
 389
 390 static struct atmel_tcb_config tcb_sama5d2_config = {
 391         .counter_width = 32,
 392         .has_gclk = 1,
 393 };
 394
 395 static const struct of_device_id atmel_tcb_of_match[] = {
 396         { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
 397         { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
 398         { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
 399         { /* sentinel */ }
 400 };
 401
 402 static int atmel_tcb_pwm_probe(struct platform_device *pdev)
 403 {
 404         const struct of_device_id *match;
 405         struct atmel_tcb_pwm_chip *tcbpwm;
 406         const struct atmel_tcb_config *config;
 407         struct device_node *np = pdev->dev.of_node;
 408         struct regmap *regmap;
 409         struct clk *clk, *gclk = NULL;
 410         struct clk *slow_clk;
 411         char clk_name[] = "t0_clk";
 412         int err;
 413         int channel;
 414
 415         err = of_property_read_u32(np, "reg", &channel);
 416         if (err < 0) {
 417                 dev_err(&pdev->dev,
 418                         "failed to get Timer Counter Block channel from device tree (error: %d)\n",
 419                         err);
 420                 return err;
 421         }
 422
 423         regmap = syscon_node_to_regmap(np->parent);
 424         if (IS_ERR(regmap))
 425                 return PTR_ERR(regmap);
 426
 427         slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
 428         if (IS_ERR(slow_clk))
 429                 return PTR_ERR(slow_clk);
 430
 431         clk_name[1] += channel;
 432         clk = of_clk_get_by_name(np->parent, clk_name);
 433         if (IS_ERR(clk))
 434                 clk = of_clk_get_by_name(np->parent, "t0_clk");
 435         if (IS_ERR(clk))
 436                 return PTR_ERR(clk);
 437
 438         match = of_match_node(atmel_tcb_of_match, np->parent);
 439         config = match->data;
 440
 441         if (config->has_gclk) {
 442                 gclk = of_clk_get_by_name(np->parent, "gclk");
 443                 if (IS_ERR(gclk))
 444                         return PTR_ERR(gclk);
 445         }
 446
 447         tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
 448         if (tcbpwm == NULL) {
 449                 err = -ENOMEM;
 450                 goto err_slow_clk;
 451         }
 452
 453         tcbpwm->chip.dev = &pdev->dev;
 454         tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
 455         tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
 456         tcbpwm->chip.of_pwm_n_cells = 3;
 457         tcbpwm->chip.base = -1;
 458         tcbpwm->chip.npwm = NPWM;
 459         tcbpwm->channel = channel;
 460         tcbpwm->regmap = regmap;
 461         tcbpwm->clk = clk;
 462         tcbpwm->gclk = gclk;
 463         tcbpwm->slow_clk = slow_clk;
 464         tcbpwm->width = config->counter_width;
 465
 466         err = clk_prepare_enable(slow_clk);
 467         if (err)
 468                 goto err_slow_clk;
 469
 470         spin_lock_init(&tcbpwm->lock);
 471
 472         err = pwmchip_add(&tcbpwm->chip);
 473         if (err < 0)
 474                 goto err_disable_clk;
 475
 476         platform_set_drvdata(pdev, tcbpwm);
 477
 478         return 0;
 479
 480 err_disable_clk:
 481         clk_disable_unprepare(tcbpwm->slow_clk);
 482
 483 err_slow_clk:
 484         clk_put(slow_clk);
 485
 486         return err;
 487 }
 488
 489 static int atmel_tcb_pwm_remove(struct platform_device *pdev)
 490 {
 491         struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
 492         int err;
 493
 494         clk_disable_unprepare(tcbpwm->slow_clk);
 495         clk_put(tcbpwm->slow_clk);
 496         clk_put(tcbpwm->clk);
 497
 498         err = pwmchip_remove(&tcbpwm->chip);
 499         if (err < 0)
 500                 return err;
 501
 502         return 0;
 503 }
 504
 505 static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
 506         { .compatible = "atmel,tcb-pwm", },
 507         { /* sentinel */ }
 508 };
 509 MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
 510
 511 #ifdef CONFIG_PM_SLEEP
 512 static int atmel_tcb_pwm_suspend(struct device *dev)
 513 {
 514         struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
 515         struct atmel_tcb_channel *chan = &tcbpwm->bkup;
 516         unsigned int channel = tcbpwm->channel;
 517
 518         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
 519         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
 520         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
 521         regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
 522
 523         return 0;
 524 }
 525
 526 static int atmel_tcb_pwm_resume(struct device *dev)
 527 {
 528         struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
 529         struct atmel_tcb_channel *chan = &tcbpwm->bkup;
 530         unsigned int channel = tcbpwm->channel;
 531
 532         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
 533         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
 534         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
 535         regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
 536
 537         if (chan->enabled)
 538                 regmap_write(tcbpwm->regmap,
 539                              ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 540                              ATMEL_TC_REG(channel, CCR));
 541
 542         return 0;
 543 }
 544 #endif
 545
 546 static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
 547                          atmel_tcb_pwm_resume);
 548
 549 static struct platform_driver atmel_tcb_pwm_driver = {
 550         .driver = {
 551                 .name = "atmel-tcb-pwm",
 552                 .of_match_table = atmel_tcb_pwm_dt_ids,
 553                 .pm = &atmel_tcb_pwm_pm_ops,
 554         },
 555         .probe = atmel_tcb_pwm_probe,
 556         .remove = atmel_tcb_pwm_remove,
 557 };
 558 module_platform_driver(atmel_tcb_pwm_driver);
 559
 560 MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
 561 MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
 562 MODULE_LICENSE("GPL v2");