1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
4 #include <linux/bits.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36 static struct class timecard_class = {
66 #define OCP_CTRL_ENABLE BIT(0)
67 #define OCP_CTRL_ADJUST_TIME BIT(1)
68 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
69 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
70 #define OCP_CTRL_ADJUST_SERVO BIT(8)
71 #define OCP_CTRL_READ_TIME_REQ BIT(30)
72 #define OCP_CTRL_READ_TIME_DONE BIT(31)
74 #define OCP_STATUS_IN_SYNC BIT(0)
75 #define OCP_STATUS_IN_HOLDOVER BIT(1)
77 #define OCP_SELECT_CLK_NONE 0
78 #define OCP_SELECT_CLK_REG 0xfe
93 #define TOD_CTRL_PROTOCOL BIT(28)
94 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
95 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
96 #define TOD_CTRL_ENABLE BIT(0)
97 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
98 #define TOD_CTRL_GNSS_SHIFT 24
100 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
101 #define TOD_STATUS_UTC_VALID BIT(8)
102 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
103 #define TOD_STATUS_LEAP_VALID BIT(16)
131 #define PPS_STATUS_FILTER_ERR BIT(0)
132 #define PPS_STATUS_SUPERV_ERR BIT(1)
145 struct irig_master_reg {
154 #define IRIG_M_CTRL_ENABLE BIT(0)
156 struct irig_slave_reg {
165 #define IRIG_S_CTRL_ENABLE BIT(0)
167 struct dcf_master_reg {
175 #define DCF_M_CTRL_ENABLE BIT(0)
177 struct dcf_slave_reg {
185 #define DCF_S_CTRL_ENABLE BIT(0)
207 struct frequency_reg {
212 struct board_config_reg {
213 u32 mro50_serial_activate;
216 #define FREQ_STATUS_VALID BIT(31)
217 #define FREQ_STATUS_ERROR BIT(30)
218 #define FREQ_STATUS_OVERRUN BIT(29)
219 #define FREQ_STATUS_MASK GENMASK(23, 0)
221 struct ptp_ocp_flash_info {
228 struct ptp_ocp_firmware_header {
230 __be16 pci_vendor_id;
231 __be16 pci_device_id;
237 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
239 struct ptp_ocp_i2c_info {
241 unsigned long fixed_rate;
246 struct ptp_ocp_ext_info {
248 irqreturn_t (*irq_fcn)(int irq, void *priv);
249 int (*enable)(void *priv, u32 req, bool enable);
252 struct ptp_ocp_ext_src {
255 struct ptp_ocp_ext_info *info;
259 enum ptp_ocp_sma_mode {
264 struct ptp_ocp_sma_connector {
265 enum ptp_ocp_sma_mode mode;
272 struct ocp_attr_group {
274 const struct attribute_group *group;
277 #define OCP_CAP_BASIC BIT(0)
278 #define OCP_CAP_SIGNAL BIT(1)
279 #define OCP_CAP_FREQ BIT(2)
281 struct ptp_ocp_signal {
291 struct ptp_ocp_serial_port {
296 #define OCP_BOARD_ID_LEN 13
297 #define OCP_SERIAL_LEN 6
300 struct pci_dev *pdev;
303 struct ocp_reg __iomem *reg;
304 struct tod_reg __iomem *tod;
305 struct pps_reg __iomem *pps_to_ext;
306 struct pps_reg __iomem *pps_to_clk;
307 struct board_config_reg __iomem *board_config;
308 struct gpio_reg __iomem *pps_select;
309 struct gpio_reg __iomem *sma_map1;
310 struct gpio_reg __iomem *sma_map2;
311 struct irig_master_reg __iomem *irig_out;
312 struct irig_slave_reg __iomem *irig_in;
313 struct dcf_master_reg __iomem *dcf_out;
314 struct dcf_slave_reg __iomem *dcf_in;
315 struct tod_reg __iomem *nmea_out;
316 struct frequency_reg __iomem *freq_in[4];
317 struct ptp_ocp_ext_src *signal_out[4];
318 struct ptp_ocp_ext_src *pps;
319 struct ptp_ocp_ext_src *ts0;
320 struct ptp_ocp_ext_src *ts1;
321 struct ptp_ocp_ext_src *ts2;
322 struct ptp_ocp_ext_src *ts3;
323 struct ptp_ocp_ext_src *ts4;
324 struct ocp_art_gpio_reg __iomem *art_sma;
325 struct img_reg __iomem *image;
326 struct ptp_clock *ptp;
327 struct ptp_clock_info ptp_info;
328 struct platform_device *i2c_ctrl;
329 struct platform_device *spi_flash;
330 struct clk_hw *i2c_clk;
331 struct timer_list watchdog;
332 const struct attribute_group **attr_group;
333 const struct ptp_ocp_eeprom_map *eeprom_map;
334 struct dentry *debug_root;
338 struct ptp_ocp_serial_port gnss_port;
339 struct ptp_ocp_serial_port gnss2_port;
340 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */
341 struct ptp_ocp_serial_port nmea_port;
345 u8 board_id[OCP_BOARD_ID_LEN];
346 u8 serial[OCP_SERIAL_LEN];
347 bool has_eeprom_data;
351 u32 ts_window_adjust;
353 struct ptp_ocp_signal signal[4];
354 struct ptp_ocp_sma_connector sma[4];
355 const struct ocp_sma_op *sma_op;
358 #define OCP_REQ_TIMESTAMP BIT(0)
359 #define OCP_REQ_PPS BIT(1)
361 struct ocp_resource {
362 unsigned long offset;
365 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
367 unsigned long bp_offset;
368 const char * const name;
371 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
372 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
373 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
374 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
375 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
376 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
377 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
378 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
379 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
380 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
381 struct ptp_perout_request *req);
382 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
383 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
385 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
387 static const struct ocp_attr_group fb_timecard_groups[];
389 static const struct ocp_attr_group art_timecard_groups[];
391 struct ptp_ocp_eeprom_map {
395 const void * const tag;
398 #define EEPROM_ENTRY(addr, member) \
400 .len = sizeof_field(struct ptp_ocp, member), \
401 .bp_offset = offsetof(struct ptp_ocp, member)
403 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
404 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
407 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
408 { EEPROM_ENTRY(0x43, board_id) },
409 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
413 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
414 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
415 { EEPROM_ENTRY(0x200 + 0x63, serial) },
419 #define bp_assign_entry(bp, res, val) ({ \
420 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
421 *(typeof(val) *)addr = val; \
424 #define OCP_RES_LOCATION(member) \
425 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
427 #define OCP_MEM_RESOURCE(member) \
428 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
430 #define OCP_SERIAL_RESOURCE(member) \
431 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
433 #define OCP_I2C_RESOURCE(member) \
434 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
436 #define OCP_SPI_RESOURCE(member) \
437 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
439 #define OCP_EXT_RESOURCE(member) \
440 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
442 /* This is the MSI vector mapping used.
451 * 8: HWICAP (notused)
454 * 11: Signal Generator 1
455 * 12: Signal Generator 2
456 * 13: Signal Generator 3
457 * 14: Signal Generator 4
463 * 11: Orolia TS0 (GNSS)
469 static struct ocp_resource ocp_fb_resource[] = {
471 OCP_MEM_RESOURCE(reg),
472 .offset = 0x01000000, .size = 0x10000,
475 OCP_EXT_RESOURCE(ts0),
476 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
477 .extra = &(struct ptp_ocp_ext_info) {
479 .irq_fcn = ptp_ocp_ts_irq,
480 .enable = ptp_ocp_ts_enable,
484 OCP_EXT_RESOURCE(ts1),
485 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
486 .extra = &(struct ptp_ocp_ext_info) {
488 .irq_fcn = ptp_ocp_ts_irq,
489 .enable = ptp_ocp_ts_enable,
493 OCP_EXT_RESOURCE(ts2),
494 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
495 .extra = &(struct ptp_ocp_ext_info) {
497 .irq_fcn = ptp_ocp_ts_irq,
498 .enable = ptp_ocp_ts_enable,
502 OCP_EXT_RESOURCE(ts3),
503 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
504 .extra = &(struct ptp_ocp_ext_info) {
506 .irq_fcn = ptp_ocp_ts_irq,
507 .enable = ptp_ocp_ts_enable,
511 OCP_EXT_RESOURCE(ts4),
512 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
513 .extra = &(struct ptp_ocp_ext_info) {
515 .irq_fcn = ptp_ocp_ts_irq,
516 .enable = ptp_ocp_ts_enable,
519 /* Timestamp for PHC and/or PPS generator */
521 OCP_EXT_RESOURCE(pps),
522 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
523 .extra = &(struct ptp_ocp_ext_info) {
525 .irq_fcn = ptp_ocp_ts_irq,
526 .enable = ptp_ocp_ts_enable,
530 OCP_EXT_RESOURCE(signal_out[0]),
531 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
532 .extra = &(struct ptp_ocp_ext_info) {
534 .irq_fcn = ptp_ocp_signal_irq,
535 .enable = ptp_ocp_signal_enable,
539 OCP_EXT_RESOURCE(signal_out[1]),
540 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
541 .extra = &(struct ptp_ocp_ext_info) {
543 .irq_fcn = ptp_ocp_signal_irq,
544 .enable = ptp_ocp_signal_enable,
548 OCP_EXT_RESOURCE(signal_out[2]),
549 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
550 .extra = &(struct ptp_ocp_ext_info) {
552 .irq_fcn = ptp_ocp_signal_irq,
553 .enable = ptp_ocp_signal_enable,
557 OCP_EXT_RESOURCE(signal_out[3]),
558 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
559 .extra = &(struct ptp_ocp_ext_info) {
561 .irq_fcn = ptp_ocp_signal_irq,
562 .enable = ptp_ocp_signal_enable,
566 OCP_MEM_RESOURCE(pps_to_ext),
567 .offset = 0x01030000, .size = 0x10000,
570 OCP_MEM_RESOURCE(pps_to_clk),
571 .offset = 0x01040000, .size = 0x10000,
574 OCP_MEM_RESOURCE(tod),
575 .offset = 0x01050000, .size = 0x10000,
578 OCP_MEM_RESOURCE(irig_in),
579 .offset = 0x01070000, .size = 0x10000,
582 OCP_MEM_RESOURCE(irig_out),
583 .offset = 0x01080000, .size = 0x10000,
586 OCP_MEM_RESOURCE(dcf_in),
587 .offset = 0x01090000, .size = 0x10000,
590 OCP_MEM_RESOURCE(dcf_out),
591 .offset = 0x010A0000, .size = 0x10000,
594 OCP_MEM_RESOURCE(nmea_out),
595 .offset = 0x010B0000, .size = 0x10000,
598 OCP_MEM_RESOURCE(image),
599 .offset = 0x00020000, .size = 0x1000,
602 OCP_MEM_RESOURCE(pps_select),
603 .offset = 0x00130000, .size = 0x1000,
606 OCP_MEM_RESOURCE(sma_map1),
607 .offset = 0x00140000, .size = 0x1000,
610 OCP_MEM_RESOURCE(sma_map2),
611 .offset = 0x00220000, .size = 0x1000,
614 OCP_I2C_RESOURCE(i2c_ctrl),
615 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
616 .extra = &(struct ptp_ocp_i2c_info) {
618 .fixed_rate = 50000000,
619 .data_size = sizeof(struct xiic_i2c_platform_data),
620 .data = &(struct xiic_i2c_platform_data) {
622 .devices = (struct i2c_board_info[]) {
623 { I2C_BOARD_INFO("24c02", 0x50) },
624 { I2C_BOARD_INFO("24mac402", 0x58),
625 .platform_data = "mac" },
631 OCP_SERIAL_RESOURCE(gnss_port),
632 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
633 .extra = &(struct ptp_ocp_serial_port) {
638 OCP_SERIAL_RESOURCE(gnss2_port),
639 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
640 .extra = &(struct ptp_ocp_serial_port) {
645 OCP_SERIAL_RESOURCE(mac_port),
646 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
647 .extra = &(struct ptp_ocp_serial_port) {
652 OCP_SERIAL_RESOURCE(nmea_port),
653 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
656 OCP_SPI_RESOURCE(spi_flash),
657 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
658 .extra = &(struct ptp_ocp_flash_info) {
659 .name = "xilinx_spi", .pci_offset = 0,
660 .data_size = sizeof(struct xspi_platform_data),
661 .data = &(struct xspi_platform_data) {
665 .devices = &(struct spi_board_info) {
666 .modalias = "spi-nor",
672 OCP_MEM_RESOURCE(freq_in[0]),
673 .offset = 0x01200000, .size = 0x10000,
676 OCP_MEM_RESOURCE(freq_in[1]),
677 .offset = 0x01210000, .size = 0x10000,
680 OCP_MEM_RESOURCE(freq_in[2]),
681 .offset = 0x01220000, .size = 0x10000,
684 OCP_MEM_RESOURCE(freq_in[3]),
685 .offset = 0x01230000, .size = 0x10000,
688 .setup = ptp_ocp_fb_board_init,
693 #define OCP_ART_CONFIG_SIZE 144
694 #define OCP_ART_TEMP_TABLE_SIZE 368
696 struct ocp_art_gpio_reg {
703 static struct ocp_resource ocp_art_resource[] = {
705 OCP_MEM_RESOURCE(reg),
706 .offset = 0x01000000, .size = 0x10000,
709 OCP_SERIAL_RESOURCE(gnss_port),
710 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
711 .extra = &(struct ptp_ocp_serial_port) {
716 OCP_MEM_RESOURCE(art_sma),
717 .offset = 0x003C0000, .size = 0x1000,
719 /* Timestamp associated with GNSS1 receiver PPS */
721 OCP_EXT_RESOURCE(ts0),
722 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
723 .extra = &(struct ptp_ocp_ext_info) {
725 .irq_fcn = ptp_ocp_ts_irq,
726 .enable = ptp_ocp_ts_enable,
730 OCP_EXT_RESOURCE(ts1),
731 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
732 .extra = &(struct ptp_ocp_ext_info) {
734 .irq_fcn = ptp_ocp_ts_irq,
735 .enable = ptp_ocp_ts_enable,
739 OCP_EXT_RESOURCE(ts2),
740 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
741 .extra = &(struct ptp_ocp_ext_info) {
743 .irq_fcn = ptp_ocp_ts_irq,
744 .enable = ptp_ocp_ts_enable,
748 OCP_EXT_RESOURCE(ts3),
749 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
750 .extra = &(struct ptp_ocp_ext_info) {
752 .irq_fcn = ptp_ocp_ts_irq,
753 .enable = ptp_ocp_ts_enable,
757 OCP_EXT_RESOURCE(ts4),
758 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
759 .extra = &(struct ptp_ocp_ext_info) {
761 .irq_fcn = ptp_ocp_ts_irq,
762 .enable = ptp_ocp_ts_enable,
765 /* Timestamp associated with Internal PPS of the card */
767 OCP_EXT_RESOURCE(pps),
768 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
769 .extra = &(struct ptp_ocp_ext_info) {
771 .irq_fcn = ptp_ocp_ts_irq,
772 .enable = ptp_ocp_ts_enable,
776 OCP_SPI_RESOURCE(spi_flash),
777 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
778 .extra = &(struct ptp_ocp_flash_info) {
779 .name = "spi_altera", .pci_offset = 0,
780 .data_size = sizeof(struct altera_spi_platform_data),
781 .data = &(struct altera_spi_platform_data) {
784 .devices = &(struct spi_board_info) {
785 .modalias = "spi-nor",
791 OCP_I2C_RESOURCE(i2c_ctrl),
792 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
793 .extra = &(struct ptp_ocp_i2c_info) {
794 .name = "ocores-i2c",
795 .fixed_rate = 400000,
796 .data_size = sizeof(struct ocores_i2c_platform_data),
797 .data = &(struct ocores_i2c_platform_data) {
801 .devices = &(struct i2c_board_info) {
802 I2C_BOARD_INFO("24c08", 0x50),
808 OCP_SERIAL_RESOURCE(mac_port),
809 .offset = 0x00190000, .irq_vec = 7,
810 .extra = &(struct ptp_ocp_serial_port) {
815 OCP_MEM_RESOURCE(board_config),
816 .offset = 0x210000, .size = 0x1000,
819 .setup = ptp_ocp_art_board_init,
824 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
825 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
826 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
827 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
830 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
832 static DEFINE_MUTEX(ptp_ocp_lock);
833 static DEFINE_IDR(ptp_ocp_idr);
835 struct ocp_selector {
840 static const struct ocp_selector ptp_ocp_clock[] = {
841 { .name = "NONE", .value = 0 },
842 { .name = "TOD", .value = 1 },
843 { .name = "IRIG", .value = 2 },
844 { .name = "PPS", .value = 3 },
845 { .name = "PTP", .value = 4 },
846 { .name = "RTC", .value = 5 },
847 { .name = "DCF", .value = 6 },
848 { .name = "REGS", .value = 0xfe },
849 { .name = "EXT", .value = 0xff },
853 #define SMA_DISABLE BIT(16)
854 #define SMA_ENABLE BIT(15)
855 #define SMA_SELECT_MASK GENMASK(14, 0)
857 static const struct ocp_selector ptp_ocp_sma_in[] = {
858 { .name = "10Mhz", .value = 0x0000 },
859 { .name = "PPS1", .value = 0x0001 },
860 { .name = "PPS2", .value = 0x0002 },
861 { .name = "TS1", .value = 0x0004 },
862 { .name = "TS2", .value = 0x0008 },
863 { .name = "IRIG", .value = 0x0010 },
864 { .name = "DCF", .value = 0x0020 },
865 { .name = "TS3", .value = 0x0040 },
866 { .name = "TS4", .value = 0x0080 },
867 { .name = "FREQ1", .value = 0x0100 },
868 { .name = "FREQ2", .value = 0x0200 },
869 { .name = "FREQ3", .value = 0x0400 },
870 { .name = "FREQ4", .value = 0x0800 },
871 { .name = "None", .value = SMA_DISABLE },
875 static const struct ocp_selector ptp_ocp_sma_out[] = {
876 { .name = "10Mhz", .value = 0x0000 },
877 { .name = "PHC", .value = 0x0001 },
878 { .name = "MAC", .value = 0x0002 },
879 { .name = "GNSS1", .value = 0x0004 },
880 { .name = "GNSS2", .value = 0x0008 },
881 { .name = "IRIG", .value = 0x0010 },
882 { .name = "DCF", .value = 0x0020 },
883 { .name = "GEN1", .value = 0x0040 },
884 { .name = "GEN2", .value = 0x0080 },
885 { .name = "GEN3", .value = 0x0100 },
886 { .name = "GEN4", .value = 0x0200 },
887 { .name = "GND", .value = 0x2000 },
888 { .name = "VCC", .value = 0x4000 },
892 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
893 { .name = "PPS1", .value = 0x0001 },
894 { .name = "10Mhz", .value = 0x0008 },
898 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
899 { .name = "PHC", .value = 0x0002 },
900 { .name = "GNSS", .value = 0x0004 },
901 { .name = "10Mhz", .value = 0x0010 },
906 const struct ocp_selector *tbl[2];
907 void (*init)(struct ptp_ocp *bp);
908 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
909 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
910 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
914 ptp_ocp_sma_init(struct ptp_ocp *bp)
916 return bp->sma_op->init(bp);
920 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
922 return bp->sma_op->get(bp, sma_nr);
926 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
928 return bp->sma_op->set_inputs(bp, sma_nr, val);
932 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
934 return bp->sma_op->set_output(bp, sma_nr, val);
938 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
942 for (i = 0; tbl[i].name; i++)
943 if (tbl[i].value == val)
949 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
954 for (i = 0; tbl[i].name; i++) {
955 select = tbl[i].name;
956 if (!strncasecmp(name, select, strlen(select)))
963 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
969 for (i = 0; tbl[i].name; i++)
970 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
973 count += sysfs_emit_at(buf, count, "\n");
978 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
979 struct ptp_system_timestamp *sts)
981 u32 ctrl, time_sec, time_ns;
984 ptp_read_system_prets(sts);
986 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
987 iowrite32(ctrl, &bp->reg->ctrl);
989 for (i = 0; i < 100; i++) {
990 ctrl = ioread32(&bp->reg->ctrl);
991 if (ctrl & OCP_CTRL_READ_TIME_DONE)
994 ptp_read_system_postts(sts);
996 if (sts && bp->ts_window_adjust) {
997 s64 ns = timespec64_to_ns(&sts->post_ts);
999 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1002 time_ns = ioread32(&bp->reg->time_ns);
1003 time_sec = ioread32(&bp->reg->time_sec);
1005 ts->tv_sec = time_sec;
1006 ts->tv_nsec = time_ns;
1008 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1012 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1013 struct ptp_system_timestamp *sts)
1015 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1016 unsigned long flags;
1019 spin_lock_irqsave(&bp->lock, flags);
1020 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1021 spin_unlock_irqrestore(&bp->lock, flags);
1027 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1029 u32 ctrl, time_sec, time_ns;
1032 time_ns = ts->tv_nsec;
1033 time_sec = ts->tv_sec;
1035 select = ioread32(&bp->reg->select);
1036 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1038 iowrite32(time_ns, &bp->reg->adjust_ns);
1039 iowrite32(time_sec, &bp->reg->adjust_sec);
1041 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1042 iowrite32(ctrl, &bp->reg->ctrl);
1044 /* restore clock selection */
1045 iowrite32(select >> 16, &bp->reg->select);
1049 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1051 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1052 unsigned long flags;
1054 spin_lock_irqsave(&bp->lock, flags);
1055 __ptp_ocp_settime_locked(bp, ts);
1056 spin_unlock_irqrestore(&bp->lock, flags);
1062 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1066 select = ioread32(&bp->reg->select);
1067 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1069 iowrite32(adj_val, &bp->reg->offset_ns);
1070 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1072 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1073 iowrite32(ctrl, &bp->reg->ctrl);
1075 /* restore clock selection */
1076 iowrite32(select >> 16, &bp->reg->select);
1080 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1082 struct timespec64 ts;
1083 unsigned long flags;
1086 spin_lock_irqsave(&bp->lock, flags);
1087 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1089 set_normalized_timespec64(&ts, ts.tv_sec,
1090 ts.tv_nsec + delta_ns);
1091 __ptp_ocp_settime_locked(bp, &ts);
1093 spin_unlock_irqrestore(&bp->lock, flags);
1097 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1099 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1100 unsigned long flags;
1103 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1104 ptp_ocp_adjtime_coarse(bp, delta_ns);
1108 sign = delta_ns < 0 ? BIT(31) : 0;
1109 adj_ns = sign ? -delta_ns : delta_ns;
1111 spin_lock_irqsave(&bp->lock, flags);
1112 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1113 spin_unlock_irqrestore(&bp->lock, flags);
1119 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1121 if (scaled_ppm == 0)
1128 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1134 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1137 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1138 struct ptp_ocp_ext_src *ext = NULL;
1143 case PTP_CLK_REQ_EXTTS:
1144 req = OCP_REQ_TIMESTAMP;
1145 switch (rq->extts.index) {
1166 case PTP_CLK_REQ_PPS:
1170 case PTP_CLK_REQ_PEROUT:
1171 switch (rq->perout.index) {
1173 /* This is a request for 1PPS on an output SMA.
1174 * Allow, but assume manual configuration.
1176 if (on && (rq->perout.period.sec != 1 ||
1177 rq->perout.period.nsec != 0))
1184 req = rq->perout.index - 1;
1185 ext = bp->signal_out[req];
1186 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1198 err = ext->info->enable(ext, req, on);
1204 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1205 enum ptp_pin_function func, unsigned chan)
1207 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1212 snprintf(buf, sizeof(buf), "IN: None");
1215 /* Allow timestamps, but require sysfs configuration. */
1218 /* channel 0 is 1PPS from PHC.
1219 * channels 1..4 are the frequency generators.
1222 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1224 snprintf(buf, sizeof(buf), "OUT: PHC");
1230 return ptp_ocp_sma_store(bp, buf, pin + 1);
1233 static const struct ptp_clock_info ptp_ocp_clock_info = {
1234 .owner = THIS_MODULE,
1235 .name = KBUILD_MODNAME,
1236 .max_adj = 100000000,
1237 .gettimex64 = ptp_ocp_gettimex,
1238 .settime64 = ptp_ocp_settime,
1239 .adjtime = ptp_ocp_adjtime,
1240 .adjfine = ptp_ocp_null_adjfine,
1241 .adjphase = ptp_ocp_null_adjphase,
1242 .enable = ptp_ocp_enable,
1243 .verify = ptp_ocp_verify,
1250 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1254 select = ioread32(&bp->reg->select);
1255 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1257 iowrite32(0, &bp->reg->drift_ns);
1259 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1260 iowrite32(ctrl, &bp->reg->ctrl);
1262 /* restore clock selection */
1263 iowrite32(select >> 16, &bp->reg->select);
1267 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1269 unsigned long flags;
1271 spin_lock_irqsave(&bp->lock, flags);
1273 bp->utc_tai_offset = val;
1276 iowrite32(val, &bp->irig_out->adj_sec);
1278 iowrite32(val, &bp->dcf_out->adj_sec);
1280 iowrite32(val, &bp->nmea_out->adj_sec);
1282 spin_unlock_irqrestore(&bp->lock, flags);
1286 ptp_ocp_watchdog(struct timer_list *t)
1288 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1289 unsigned long flags;
1290 u32 status, utc_offset;
1292 status = ioread32(&bp->pps_to_clk->status);
1294 if (status & PPS_STATUS_SUPERV_ERR) {
1295 iowrite32(status, &bp->pps_to_clk->status);
1296 if (!bp->gnss_lost) {
1297 spin_lock_irqsave(&bp->lock, flags);
1298 __ptp_ocp_clear_drift_locked(bp);
1299 spin_unlock_irqrestore(&bp->lock, flags);
1300 bp->gnss_lost = ktime_get_real_seconds();
1303 } else if (bp->gnss_lost) {
1307 /* if GNSS provides correct data we can rely on
1308 * it to get leap second information
1311 status = ioread32(&bp->tod->utc_status);
1312 utc_offset = status & TOD_STATUS_UTC_MASK;
1313 if (status & TOD_STATUS_UTC_VALID &&
1314 utc_offset != bp->utc_tai_offset)
1315 ptp_ocp_utc_distribute(bp, utc_offset);
1318 mod_timer(&bp->watchdog, jiffies + HZ);
1322 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1328 ctrl = ioread32(&bp->reg->ctrl);
1329 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1331 iowrite32(ctrl, &bp->reg->ctrl);
1333 start = ktime_get_ns();
1335 ctrl = ioread32(&bp->reg->ctrl);
1337 end = ktime_get_ns();
1339 delay = end - start;
1340 bp->ts_window_adjust = (delay >> 5) * 3;
1344 ptp_ocp_init_clock(struct ptp_ocp *bp)
1346 struct timespec64 ts;
1350 ctrl = OCP_CTRL_ENABLE;
1351 iowrite32(ctrl, &bp->reg->ctrl);
1353 /* NO DRIFT Correction */
1354 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1355 iowrite32(0x2000, &bp->reg->servo_offset_p);
1356 iowrite32(0x1000, &bp->reg->servo_offset_i);
1357 iowrite32(0, &bp->reg->servo_drift_p);
1358 iowrite32(0, &bp->reg->servo_drift_i);
1360 /* latch servo values */
1361 ctrl |= OCP_CTRL_ADJUST_SERVO;
1362 iowrite32(ctrl, &bp->reg->ctrl);
1364 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1365 dev_err(&bp->pdev->dev, "clock not enabled\n");
1369 ptp_ocp_estimate_pci_timing(bp);
1371 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1373 ktime_get_clocktai_ts64(&ts);
1374 ptp_ocp_settime(&bp->ptp_info, &ts);
1377 /* If there is a clock supervisor, then enable the watchdog */
1378 if (bp->pps_to_clk) {
1379 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1380 mod_timer(&bp->watchdog, jiffies + HZ);
1387 ptp_ocp_tod_init(struct ptp_ocp *bp)
1391 ctrl = ioread32(&bp->tod->ctrl);
1392 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1393 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1394 iowrite32(ctrl, &bp->tod->ctrl);
1396 reg = ioread32(&bp->tod->utc_status);
1397 if (reg & TOD_STATUS_UTC_VALID)
1398 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1402 ptp_ocp_tod_proto_name(const int idx)
1404 static const char * const proto_name[] = {
1405 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1406 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1408 return proto_name[idx];
1412 ptp_ocp_tod_gnss_name(int idx)
1414 static const char * const gnss_name[] = {
1415 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1418 if (idx >= ARRAY_SIZE(gnss_name))
1419 idx = ARRAY_SIZE(gnss_name) - 1;
1420 return gnss_name[idx];
1423 struct ptp_ocp_nvmem_match_info {
1425 const void * const tag;
1429 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1431 const struct ptp_ocp_nvmem_match_info *info = data;
1434 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1437 while ((dev = dev->parent))
1438 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1439 return info->bp == dev_get_drvdata(dev);
1443 static inline struct nvmem_device *
1444 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1446 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1448 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1452 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1454 if (!IS_ERR_OR_NULL(*nvmemp))
1455 nvmem_device_put(*nvmemp);
1460 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1462 const struct ptp_ocp_eeprom_map *map;
1463 struct nvmem_device *nvmem;
1473 for (map = bp->eeprom_map; map->len; map++) {
1474 if (map->tag != tag) {
1476 ptp_ocp_nvmem_device_put(&nvmem);
1479 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1480 if (IS_ERR(nvmem)) {
1481 ret = PTR_ERR(nvmem);
1485 ret = nvmem_device_read(nvmem, map->off, map->len,
1486 BP_MAP_ENTRY_ADDR(bp, map));
1487 if (ret != map->len)
1491 bp->has_eeprom_data = true;
1494 ptp_ocp_nvmem_device_put(&nvmem);
1498 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1502 static struct device *
1503 ptp_ocp_find_flash(struct ptp_ocp *bp)
1505 struct device *dev, *last;
1508 dev = &bp->spi_flash->dev;
1510 while ((dev = device_find_any_child(dev))) {
1511 if (!strcmp("mtd", dev_bus_name(dev)))
1522 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1523 const u8 **data, size_t *size)
1525 struct ptp_ocp *bp = devlink_priv(devlink);
1526 const struct ptp_ocp_firmware_header *hdr;
1527 size_t offset, length;
1530 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1531 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1532 devlink_flash_update_status_notify(devlink,
1533 "No firmware header found, cancel firmware upgrade",
1538 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1539 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1540 devlink_flash_update_status_notify(devlink,
1541 "Firmware image compatibility check failed",
1546 offset = sizeof(*hdr);
1547 length = be32_to_cpu(hdr->image_size);
1548 if (length != (fw->size - offset)) {
1549 devlink_flash_update_status_notify(devlink,
1550 "Firmware image size check failed",
1555 crc = crc16(0xffff, &fw->data[offset], length);
1556 if (be16_to_cpu(hdr->crc) != crc) {
1557 devlink_flash_update_status_notify(devlink,
1558 "Firmware image CRC check failed",
1563 *data = &fw->data[offset];
1570 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1571 const struct firmware *fw)
1573 struct mtd_info *mtd = dev_get_drvdata(dev);
1574 struct ptp_ocp *bp = devlink_priv(devlink);
1575 size_t off, len, size, resid, wrote;
1576 struct erase_info erase;
1581 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1586 base = bp->flash_start;
1591 devlink_flash_update_status_notify(devlink, "Flashing",
1594 len = min_t(size_t, resid, blksz);
1595 erase.addr = base + off;
1598 err = mtd_erase(mtd, &erase);
1602 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1614 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1615 struct devlink_flash_update_params *params,
1616 struct netlink_ext_ack *extack)
1618 struct ptp_ocp *bp = devlink_priv(devlink);
1623 dev = ptp_ocp_find_flash(bp);
1625 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1629 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1632 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1634 msg = err ? "Flash error" : "Flash complete";
1635 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1642 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1643 struct netlink_ext_ack *extack)
1645 struct ptp_ocp *bp = devlink_priv(devlink);
1646 const char *fw_image;
1650 err = devlink_info_driver_name_put(req, KBUILD_MODNAME);
1654 fw_image = bp->fw_loader ? "loader" : "fw";
1655 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1656 err = devlink_info_version_running_put(req, fw_image, buf);
1660 if (!bp->has_eeprom_data) {
1661 ptp_ocp_read_eeprom(bp);
1662 if (!bp->has_eeprom_data)
1666 sprintf(buf, "%pM", bp->serial);
1667 err = devlink_info_serial_number_put(req, buf);
1671 err = devlink_info_version_fixed_put(req,
1672 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1680 static const struct devlink_ops ptp_ocp_devlink_ops = {
1681 .flash_update = ptp_ocp_devlink_flash_update,
1682 .info_get = ptp_ocp_devlink_info_get,
1685 static void __iomem *
1686 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1688 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1690 return devm_ioremap_resource(&bp->pdev->dev, &res);
1693 static void __iomem *
1694 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1696 resource_size_t start;
1698 start = pci_resource_start(bp->pdev, 0) + r->offset;
1699 return __ptp_ocp_get_mem(bp, start, r->size);
1703 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1705 struct resource r = DEFINE_RES_IRQ(irq);
1710 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1712 struct resource r = DEFINE_RES_MEM(start, size);
1717 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1719 struct ptp_ocp_flash_info *info;
1720 struct pci_dev *pdev = bp->pdev;
1721 struct platform_device *p;
1722 struct resource res[2];
1723 resource_size_t start;
1726 start = pci_resource_start(pdev, 0) + r->offset;
1727 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1728 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1731 id = pci_dev_id(pdev) << 1;
1732 id += info->pci_offset;
1734 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1740 bp_assign_entry(bp, r, p);
1745 static struct platform_device *
1746 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1748 struct ptp_ocp_i2c_info *info;
1749 struct resource res[2];
1750 resource_size_t start;
1753 start = pci_resource_start(pdev, 0) + r->offset;
1754 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1755 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1757 return platform_device_register_resndata(&pdev->dev, info->name,
1759 info->data, info->data_size);
1763 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1765 struct pci_dev *pdev = bp->pdev;
1766 struct ptp_ocp_i2c_info *info;
1767 struct platform_device *p;
1773 id = pci_dev_id(bp->pdev);
1775 sprintf(buf, "AXI.%d", id);
1776 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1779 return PTR_ERR(clk);
1782 sprintf(buf, "%s.%d", info->name, id);
1783 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1784 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1788 bp_assign_entry(bp, r, p);
1793 /* The expectation is that this is triggered only on error. */
1795 ptp_ocp_signal_irq(int irq, void *priv)
1797 struct ptp_ocp_ext_src *ext = priv;
1798 struct signal_reg __iomem *reg = ext->mem;
1799 struct ptp_ocp *bp = ext->bp;
1803 gen = ext->info->index - 1;
1805 enable = ioread32(®->enable);
1806 status = ioread32(®->status);
1808 /* disable generator on error */
1809 if (status || !enable) {
1810 iowrite32(0, ®->intr_mask);
1811 iowrite32(0, ®->enable);
1812 bp->signal[gen].running = false;
1815 iowrite32(0, ®->intr); /* ack interrupt */
1821 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1823 struct ptp_system_timestamp sts;
1824 struct timespec64 ts;
1832 s->pulse = ktime_divns(s->period * s->duty, 100);
1834 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1838 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1840 /* roundup() does not work on 32-bit systems */
1841 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1842 s->start = ktime_add(s->start, s->phase);
1845 if (s->duty < 1 || s->duty > 99)
1848 if (s->pulse < 1 || s->pulse > s->period)
1851 if (s->start < start_ns)
1854 bp->signal[gen] = *s;
1860 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1861 struct ptp_perout_request *req)
1863 struct ptp_ocp_signal s = { };
1865 s.polarity = bp->signal[gen].polarity;
1866 s.period = ktime_set(req->period.sec, req->period.nsec);
1870 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1871 s.pulse = ktime_set(req->on.sec, req->on.nsec);
1872 s.duty = ktime_divns(s.pulse * 100, s.period);
1875 if (req->flags & PTP_PEROUT_PHASE)
1876 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1878 s.start = ktime_set(req->start.sec, req->start.nsec);
1880 return ptp_ocp_signal_set(bp, gen, &s);
1884 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1886 struct ptp_ocp_ext_src *ext = priv;
1887 struct signal_reg __iomem *reg = ext->mem;
1888 struct ptp_ocp *bp = ext->bp;
1889 struct timespec64 ts;
1892 gen = ext->info->index - 1;
1894 iowrite32(0, ®->intr_mask);
1895 iowrite32(0, ®->enable);
1896 bp->signal[gen].running = false;
1900 ts = ktime_to_timespec64(bp->signal[gen].start);
1901 iowrite32(ts.tv_sec, ®->start_sec);
1902 iowrite32(ts.tv_nsec, ®->start_ns);
1904 ts = ktime_to_timespec64(bp->signal[gen].period);
1905 iowrite32(ts.tv_sec, ®->period_sec);
1906 iowrite32(ts.tv_nsec, ®->period_ns);
1908 ts = ktime_to_timespec64(bp->signal[gen].pulse);
1909 iowrite32(ts.tv_sec, ®->pulse_sec);
1910 iowrite32(ts.tv_nsec, ®->pulse_ns);
1912 iowrite32(bp->signal[gen].polarity, ®->polarity);
1913 iowrite32(0, ®->repeat_count);
1915 iowrite32(0, ®->intr); /* clear interrupt state */
1916 iowrite32(1, ®->intr_mask); /* enable interrupt */
1917 iowrite32(3, ®->enable); /* valid & enable */
1919 bp->signal[gen].running = true;
1925 ptp_ocp_ts_irq(int irq, void *priv)
1927 struct ptp_ocp_ext_src *ext = priv;
1928 struct ts_reg __iomem *reg = ext->mem;
1929 struct ptp_clock_event ev;
1932 if (ext == ext->bp->pps) {
1933 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1934 ev.type = PTP_CLOCK_PPS;
1935 ptp_clock_event(ext->bp->ptp, &ev);
1938 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1942 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1943 sec = ioread32(®->time_sec);
1944 nsec = ioread32(®->time_ns);
1946 ev.type = PTP_CLOCK_EXTTS;
1947 ev.index = ext->info->index;
1948 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1950 ptp_clock_event(ext->bp->ptp, &ev);
1953 iowrite32(1, ®->intr); /* write 1 to ack */
1959 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1961 struct ptp_ocp_ext_src *ext = priv;
1962 struct ts_reg __iomem *reg = ext->mem;
1963 struct ptp_ocp *bp = ext->bp;
1965 if (ext == bp->pps) {
1966 u32 old_map = bp->pps_req_map;
1969 bp->pps_req_map |= req;
1971 bp->pps_req_map &= ~req;
1973 /* if no state change, just return */
1974 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1979 iowrite32(1, ®->enable);
1980 iowrite32(1, ®->intr_mask);
1981 iowrite32(1, ®->intr);
1983 iowrite32(0, ®->intr_mask);
1984 iowrite32(0, ®->enable);
1991 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1993 ext->info->enable(ext, ~0, false);
1994 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1999 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2001 struct pci_dev *pdev = bp->pdev;
2002 struct ptp_ocp_ext_src *ext;
2005 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2009 ext->mem = ptp_ocp_get_mem(bp, r);
2010 if (IS_ERR(ext->mem)) {
2011 err = PTR_ERR(ext->mem);
2016 ext->info = r->extra;
2017 ext->irq_vec = r->irq_vec;
2019 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2020 ext, "ocp%d.%s", bp->id, r->name);
2022 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2026 bp_assign_entry(bp, r, ext);
2036 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2038 struct pci_dev *pdev = bp->pdev;
2039 struct uart_8250_port uart;
2041 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2042 * the serial port device claim and release the pci resource.
2044 memset(&uart, 0, sizeof(uart));
2045 uart.port.dev = &pdev->dev;
2046 uart.port.iotype = UPIO_MEM;
2047 uart.port.regshift = 2;
2048 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2049 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2050 uart.port.uartclk = 50000000;
2051 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2052 uart.port.type = PORT_16550A;
2054 return serial8250_register_8250_port(&uart);
2058 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2060 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2061 struct ptp_ocp_serial_port port = {};
2063 port.line = ptp_ocp_serial_line(bp, r);
2068 port.baud = p->baud;
2070 bp_assign_entry(bp, r, port);
2076 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2080 mem = ptp_ocp_get_mem(bp, r);
2082 return PTR_ERR(mem);
2084 bp_assign_entry(bp, r, mem);
2090 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2095 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2096 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2097 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2101 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2105 iowrite32(0, ®->enable); /* disable */
2107 val = ioread32(®->polarity);
2108 s->polarity = val ? true : false;
2113 ptp_ocp_signal_init(struct ptp_ocp *bp)
2117 for (i = 0; i < 4; i++)
2118 if (bp->signal_out[i])
2119 _ptp_ocp_signal_init(&bp->signal[i],
2120 bp->signal_out[i]->mem);
2124 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2126 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2127 kfree(bp->attr_group);
2131 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2132 const struct ocp_attr_group *attr_tbl)
2138 for (i = 0; attr_tbl[i].cap; i++)
2139 if (attr_tbl[i].cap & bp->fw_cap)
2142 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2144 if (!bp->attr_group)
2148 for (i = 0; attr_tbl[i].cap; i++)
2149 if (attr_tbl[i].cap & bp->fw_cap)
2150 bp->attr_group[count++] = attr_tbl[i].group;
2152 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2154 bp->attr_group[0] = NULL;
2160 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2165 ctrl = ioread32(reg);
2169 ctrl |= enable ? bit : 0;
2170 iowrite32(ctrl, reg);
2175 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2177 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2178 IRIG_M_CTRL_ENABLE, enable);
2182 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2184 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2185 IRIG_S_CTRL_ENABLE, enable);
2189 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2191 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2192 DCF_M_CTRL_ENABLE, enable);
2196 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2198 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2199 DCF_S_CTRL_ENABLE, enable);
2203 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2205 ptp_ocp_irig_out(bp, val & 0x00100010);
2206 ptp_ocp_dcf_out(bp, val & 0x00200020);
2210 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2212 ptp_ocp_irig_in(bp, val & 0x00100010);
2213 ptp_ocp_dcf_in(bp, val & 0x00200020);
2217 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2222 if (bp->sma[sma_nr - 1].fixed_fcn)
2223 return (sma_nr - 1) & 1;
2225 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2226 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2228 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2229 shift = sma_nr & 1 ? 0 : 16;
2231 return (ioread32(gpio) >> shift) & 0xffff;
2235 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2237 u32 reg, mask, shift;
2238 unsigned long flags;
2241 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2242 shift = sma_nr & 1 ? 0 : 16;
2244 mask = 0xffff << (16 - shift);
2246 spin_lock_irqsave(&bp->lock, flags);
2248 reg = ioread32(gpio);
2249 reg = (reg & mask) | (val << shift);
2251 __handle_signal_outputs(bp, reg);
2253 iowrite32(reg, gpio);
2255 spin_unlock_irqrestore(&bp->lock, flags);
2261 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2263 u32 reg, mask, shift;
2264 unsigned long flags;
2267 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2268 shift = sma_nr & 1 ? 0 : 16;
2270 mask = 0xffff << (16 - shift);
2272 spin_lock_irqsave(&bp->lock, flags);
2274 reg = ioread32(gpio);
2275 reg = (reg & mask) | (val << shift);
2277 __handle_signal_inputs(bp, reg);
2279 iowrite32(reg, gpio);
2281 spin_unlock_irqrestore(&bp->lock, flags);
2287 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2293 bp->sma[0].mode = SMA_MODE_IN;
2294 bp->sma[1].mode = SMA_MODE_IN;
2295 bp->sma[2].mode = SMA_MODE_OUT;
2296 bp->sma[3].mode = SMA_MODE_OUT;
2297 for (i = 0; i < 4; i++)
2298 bp->sma[i].default_fcn = i & 1;
2300 /* If no SMA1 map, the pin functions and directions are fixed. */
2301 if (!bp->sma_map1) {
2302 for (i = 0; i < 4; i++) {
2303 bp->sma[i].fixed_fcn = true;
2304 bp->sma[i].fixed_dir = true;
2309 /* If SMA2 GPIO output map is all 1, it is not present.
2310 * This indicates the firmware has fixed direction SMA pins.
2312 reg = ioread32(&bp->sma_map2->gpio2);
2313 if (reg == 0xffffffff) {
2314 for (i = 0; i < 4; i++)
2315 bp->sma[i].fixed_dir = true;
2317 reg = ioread32(&bp->sma_map1->gpio1);
2318 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2319 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2321 reg = ioread32(&bp->sma_map1->gpio2);
2322 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2323 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2327 static const struct ocp_sma_op ocp_fb_sma_op = {
2328 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2329 .init = ptp_ocp_sma_fb_init,
2330 .get = ptp_ocp_sma_fb_get,
2331 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2332 .set_output = ptp_ocp_sma_fb_set_output,
2336 ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2338 struct ptp_pin_desc *config;
2341 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2345 for (i = 0; i < 4; i++) {
2346 sprintf(config[i].name, "sma%d", i + 1);
2347 config[i].index = i;
2350 bp->ptp_info.n_pins = 4;
2351 bp->ptp_info.pin_config = config;
2357 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2359 u64 cap = OCP_CAP_BASIC;
2362 version = ioread32(&bp->image->version);
2364 /* if lower 16 bits are empty, this is the fw loader. */
2365 if ((version & 0xffff) == 0) {
2366 version = version >> 16;
2367 bp->fw_loader = true;
2370 bp->fw_tag = version >> 15;
2371 bp->fw_version = version & 0x7fff;
2376 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2380 cap |= OCP_CAP_SIGNAL;
2382 cap |= OCP_CAP_FREQ;
2388 /* FB specific board initializers; last "resource" registered. */
2390 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2394 bp->flash_start = 1024 * 4096;
2395 bp->eeprom_map = fb_eeprom_map;
2396 bp->fw_version = ioread32(&bp->image->version);
2397 bp->sma_op = &ocp_fb_sma_op;
2399 ptp_ocp_fb_set_version(bp);
2401 ptp_ocp_tod_init(bp);
2402 ptp_ocp_nmea_out_init(bp);
2403 ptp_ocp_sma_init(bp);
2404 ptp_ocp_signal_init(bp);
2406 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2410 err = ptp_ocp_fb_set_pins(bp);
2414 return ptp_ocp_init_clock(bp);
2418 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2420 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2423 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2424 r->irq_vec, r->name);
2429 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2431 struct ocp_resource *r, *table;
2434 table = (struct ocp_resource *)driver_data;
2435 for (r = table; r->setup; r++) {
2436 if (!ptp_ocp_allow_irq(bp, r))
2438 err = r->setup(bp, r);
2440 dev_err(&bp->pdev->dev,
2441 "Could not register %s: err %d\n",
2450 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2456 bp->sma[0].mode = SMA_MODE_IN;
2457 bp->sma[1].mode = SMA_MODE_IN;
2458 bp->sma[2].mode = SMA_MODE_OUT;
2459 bp->sma[3].mode = SMA_MODE_OUT;
2461 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2462 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2463 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2464 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2466 /* If no SMA map, the pin functions and directions are fixed. */
2468 for (i = 0; i < 4; i++) {
2469 bp->sma[i].fixed_fcn = true;
2470 bp->sma[i].fixed_dir = true;
2475 for (i = 0; i < 4; i++) {
2476 reg = ioread32(&bp->art_sma->map[i].gpio);
2478 switch (reg & 0xff) {
2480 bp->sma[i].fixed_fcn = true;
2481 bp->sma[i].fixed_dir = true;
2485 bp->sma[i].mode = SMA_MODE_IN;
2488 bp->sma[i].mode = SMA_MODE_OUT;
2495 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2497 if (bp->sma[sma_nr - 1].fixed_fcn)
2498 return bp->sma[sma_nr - 1].default_fcn;
2500 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2503 /* note: store 0 is considered invalid. */
2505 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2507 unsigned long flags;
2512 val &= SMA_SELECT_MASK;
2513 if (hweight32(val) > 1)
2516 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2518 spin_lock_irqsave(&bp->lock, flags);
2519 reg = ioread32(gpio);
2520 if (((reg >> 16) & val) == 0) {
2523 reg = (reg & 0xff00) | (val & 0xff);
2524 iowrite32(reg, gpio);
2526 spin_unlock_irqrestore(&bp->lock, flags);
2531 static const struct ocp_sma_op ocp_art_sma_op = {
2532 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2533 .init = ptp_ocp_art_sma_init,
2534 .get = ptp_ocp_art_sma_get,
2535 .set_inputs = ptp_ocp_art_sma_set,
2536 .set_output = ptp_ocp_art_sma_set,
2539 /* ART specific board initializers; last "resource" registered. */
2541 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2545 bp->flash_start = 0x1000000;
2546 bp->eeprom_map = art_eeprom_map;
2547 bp->fw_cap = OCP_CAP_BASIC;
2548 bp->fw_version = ioread32(&bp->reg->version);
2550 bp->sma_op = &ocp_art_sma_op;
2552 /* Enable MAC serial port during initialisation */
2553 iowrite32(1, &bp->board_config->mro50_serial_activate);
2555 ptp_ocp_sma_init(bp);
2557 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2561 return ptp_ocp_init_clock(bp);
2565 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2571 count = sysfs_emit(buf, "OUT: ");
2572 name = ptp_ocp_select_name_from_val(tbl, val);
2574 name = ptp_ocp_select_name_from_val(tbl, def_val);
2575 count += sysfs_emit_at(buf, count, "%s\n", name);
2580 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2587 count = sysfs_emit(buf, "IN: ");
2588 for (i = 0; tbl[i].name; i++) {
2589 if (val & tbl[i].value) {
2591 count += sysfs_emit_at(buf, count, "%s ", name);
2594 if (!val && def_val >= 0) {
2595 name = ptp_ocp_select_name_from_val(tbl, def_val);
2596 count += sysfs_emit_at(buf, count, "%s ", name);
2600 count += sysfs_emit_at(buf, count, "\n");
2605 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2606 enum ptp_ocp_sma_mode *mode)
2608 int idx, count, dir;
2612 argv = argv_split(GFP_KERNEL, buf, &count);
2621 dir = *mode == SMA_MODE_IN ? 0 : 1;
2622 if (!strcasecmp("IN:", argv[0])) {
2626 if (!strcasecmp("OUT:", argv[0])) {
2630 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2633 for (; idx < count; idx++)
2634 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2644 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2645 int default_in_val, int default_out_val)
2647 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2648 const struct ocp_selector * const *tbl;
2651 tbl = bp->sma_op->tbl;
2652 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2654 if (sma->mode == SMA_MODE_IN) {
2657 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2660 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2664 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2666 struct ptp_ocp *bp = dev_get_drvdata(dev);
2668 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2672 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2674 struct ptp_ocp *bp = dev_get_drvdata(dev);
2676 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2680 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2682 struct ptp_ocp *bp = dev_get_drvdata(dev);
2684 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2688 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2690 struct ptp_ocp *bp = dev_get_drvdata(dev);
2692 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2696 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2698 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2699 enum ptp_ocp_sma_mode mode;
2703 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2707 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2710 if (sma->fixed_fcn) {
2711 if (val != sma->default_fcn)
2716 sma->disabled = !!(val & SMA_DISABLE);
2718 if (mode != sma->mode) {
2719 if (mode == SMA_MODE_IN)
2720 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2722 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2726 if (!sma->fixed_dir)
2727 val |= SMA_ENABLE; /* add enable bit */
2732 if (mode == SMA_MODE_IN)
2733 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2735 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2741 sma1_store(struct device *dev, struct device_attribute *attr,
2742 const char *buf, size_t count)
2744 struct ptp_ocp *bp = dev_get_drvdata(dev);
2747 err = ptp_ocp_sma_store(bp, buf, 1);
2748 return err ? err : count;
2752 sma2_store(struct device *dev, struct device_attribute *attr,
2753 const char *buf, size_t count)
2755 struct ptp_ocp *bp = dev_get_drvdata(dev);
2758 err = ptp_ocp_sma_store(bp, buf, 2);
2759 return err ? err : count;
2763 sma3_store(struct device *dev, struct device_attribute *attr,
2764 const char *buf, size_t count)
2766 struct ptp_ocp *bp = dev_get_drvdata(dev);
2769 err = ptp_ocp_sma_store(bp, buf, 3);
2770 return err ? err : count;
2774 sma4_store(struct device *dev, struct device_attribute *attr,
2775 const char *buf, size_t count)
2777 struct ptp_ocp *bp = dev_get_drvdata(dev);
2780 err = ptp_ocp_sma_store(bp, buf, 4);
2781 return err ? err : count;
2783 static DEVICE_ATTR_RW(sma1);
2784 static DEVICE_ATTR_RW(sma2);
2785 static DEVICE_ATTR_RW(sma3);
2786 static DEVICE_ATTR_RW(sma4);
2789 available_sma_inputs_show(struct device *dev,
2790 struct device_attribute *attr, char *buf)
2792 struct ptp_ocp *bp = dev_get_drvdata(dev);
2794 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2796 static DEVICE_ATTR_RO(available_sma_inputs);
2799 available_sma_outputs_show(struct device *dev,
2800 struct device_attribute *attr, char *buf)
2802 struct ptp_ocp *bp = dev_get_drvdata(dev);
2804 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2806 static DEVICE_ATTR_RO(available_sma_outputs);
2808 #define EXT_ATTR_RO(_group, _name, _val) \
2809 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2810 { __ATTR_RO(_name), (void *)_val }
2811 #define EXT_ATTR_RW(_group, _name, _val) \
2812 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2813 { __ATTR_RW(_name), (void *)_val }
2814 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2816 /* period [duty [phase [polarity]]] */
2818 signal_store(struct device *dev, struct device_attribute *attr,
2819 const char *buf, size_t count)
2821 struct dev_ext_attribute *ea = to_ext_attr(attr);
2822 struct ptp_ocp *bp = dev_get_drvdata(dev);
2823 struct ptp_ocp_signal s = { };
2824 int gen = (uintptr_t)ea->var;
2828 argv = argv_split(GFP_KERNEL, buf, &argc);
2833 s.duty = bp->signal[gen].duty;
2834 s.phase = bp->signal[gen].phase;
2835 s.period = bp->signal[gen].period;
2836 s.polarity = bp->signal[gen].polarity;
2841 err = kstrtobool(argv[argc], &s.polarity);
2847 err = kstrtou64(argv[argc], 0, &s.phase);
2853 err = kstrtoint(argv[argc], 0, &s.duty);
2859 err = kstrtou64(argv[argc], 0, &s.period);
2867 err = ptp_ocp_signal_set(bp, gen, &s);
2871 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2875 return err ? err : count;
2879 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2881 struct dev_ext_attribute *ea = to_ext_attr(attr);
2882 struct ptp_ocp *bp = dev_get_drvdata(dev);
2883 struct ptp_ocp_signal *signal;
2884 struct timespec64 ts;
2888 i = (uintptr_t)ea->var;
2889 signal = &bp->signal[i];
2891 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2892 signal->duty, signal->phase, signal->polarity);
2894 ts = ktime_to_timespec64(signal->start);
2895 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2899 static EXT_ATTR_RW(signal, signal, 0);
2900 static EXT_ATTR_RW(signal, signal, 1);
2901 static EXT_ATTR_RW(signal, signal, 2);
2902 static EXT_ATTR_RW(signal, signal, 3);
2905 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2907 struct dev_ext_attribute *ea = to_ext_attr(attr);
2908 struct ptp_ocp *bp = dev_get_drvdata(dev);
2909 int i = (uintptr_t)ea->var;
2911 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2913 static EXT_ATTR_RO(signal, duty, 0);
2914 static EXT_ATTR_RO(signal, duty, 1);
2915 static EXT_ATTR_RO(signal, duty, 2);
2916 static EXT_ATTR_RO(signal, duty, 3);
2919 period_show(struct device *dev, struct device_attribute *attr, char *buf)
2921 struct dev_ext_attribute *ea = to_ext_attr(attr);
2922 struct ptp_ocp *bp = dev_get_drvdata(dev);
2923 int i = (uintptr_t)ea->var;
2925 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2927 static EXT_ATTR_RO(signal, period, 0);
2928 static EXT_ATTR_RO(signal, period, 1);
2929 static EXT_ATTR_RO(signal, period, 2);
2930 static EXT_ATTR_RO(signal, period, 3);
2933 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2935 struct dev_ext_attribute *ea = to_ext_attr(attr);
2936 struct ptp_ocp *bp = dev_get_drvdata(dev);
2937 int i = (uintptr_t)ea->var;
2939 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2941 static EXT_ATTR_RO(signal, phase, 0);
2942 static EXT_ATTR_RO(signal, phase, 1);
2943 static EXT_ATTR_RO(signal, phase, 2);
2944 static EXT_ATTR_RO(signal, phase, 3);
2947 polarity_show(struct device *dev, struct device_attribute *attr,
2950 struct dev_ext_attribute *ea = to_ext_attr(attr);
2951 struct ptp_ocp *bp = dev_get_drvdata(dev);
2952 int i = (uintptr_t)ea->var;
2954 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2956 static EXT_ATTR_RO(signal, polarity, 0);
2957 static EXT_ATTR_RO(signal, polarity, 1);
2958 static EXT_ATTR_RO(signal, polarity, 2);
2959 static EXT_ATTR_RO(signal, polarity, 3);
2962 running_show(struct device *dev, struct device_attribute *attr, char *buf)
2964 struct dev_ext_attribute *ea = to_ext_attr(attr);
2965 struct ptp_ocp *bp = dev_get_drvdata(dev);
2966 int i = (uintptr_t)ea->var;
2968 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2970 static EXT_ATTR_RO(signal, running, 0);
2971 static EXT_ATTR_RO(signal, running, 1);
2972 static EXT_ATTR_RO(signal, running, 2);
2973 static EXT_ATTR_RO(signal, running, 3);
2976 start_show(struct device *dev, struct device_attribute *attr, char *buf)
2978 struct dev_ext_attribute *ea = to_ext_attr(attr);
2979 struct ptp_ocp *bp = dev_get_drvdata(dev);
2980 int i = (uintptr_t)ea->var;
2981 struct timespec64 ts;
2983 ts = ktime_to_timespec64(bp->signal[i].start);
2984 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2986 static EXT_ATTR_RO(signal, start, 0);
2987 static EXT_ATTR_RO(signal, start, 1);
2988 static EXT_ATTR_RO(signal, start, 2);
2989 static EXT_ATTR_RO(signal, start, 3);
2992 seconds_store(struct device *dev, struct device_attribute *attr,
2993 const char *buf, size_t count)
2995 struct dev_ext_attribute *ea = to_ext_attr(attr);
2996 struct ptp_ocp *bp = dev_get_drvdata(dev);
2997 int idx = (uintptr_t)ea->var;
3001 err = kstrtou32(buf, 0, &val);
3008 val = (val << 8) | 0x1;
3010 iowrite32(val, &bp->freq_in[idx]->ctrl);
3016 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3018 struct dev_ext_attribute *ea = to_ext_attr(attr);
3019 struct ptp_ocp *bp = dev_get_drvdata(dev);
3020 int idx = (uintptr_t)ea->var;
3023 val = ioread32(&bp->freq_in[idx]->ctrl);
3025 val = (val >> 8) & 0xff;
3029 return sysfs_emit(buf, "%u\n", val);
3031 static EXT_ATTR_RW(freq, seconds, 0);
3032 static EXT_ATTR_RW(freq, seconds, 1);
3033 static EXT_ATTR_RW(freq, seconds, 2);
3034 static EXT_ATTR_RW(freq, seconds, 3);
3037 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3039 struct dev_ext_attribute *ea = to_ext_attr(attr);
3040 struct ptp_ocp *bp = dev_get_drvdata(dev);
3041 int idx = (uintptr_t)ea->var;
3044 val = ioread32(&bp->freq_in[idx]->status);
3045 if (val & FREQ_STATUS_ERROR)
3046 return sysfs_emit(buf, "error\n");
3047 if (val & FREQ_STATUS_OVERRUN)
3048 return sysfs_emit(buf, "overrun\n");
3049 if (val & FREQ_STATUS_VALID)
3050 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3053 static EXT_ATTR_RO(freq, frequency, 0);
3054 static EXT_ATTR_RO(freq, frequency, 1);
3055 static EXT_ATTR_RO(freq, frequency, 2);
3056 static EXT_ATTR_RO(freq, frequency, 3);
3059 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3061 struct ptp_ocp *bp = dev_get_drvdata(dev);
3063 if (!bp->has_eeprom_data)
3064 ptp_ocp_read_eeprom(bp);
3066 return sysfs_emit(buf, "%pM\n", bp->serial);
3068 static DEVICE_ATTR_RO(serialnum);
3071 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3073 struct ptp_ocp *bp = dev_get_drvdata(dev);
3077 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3079 ret = sysfs_emit(buf, "SYNC\n");
3083 static DEVICE_ATTR_RO(gnss_sync);
3086 utc_tai_offset_show(struct device *dev,
3087 struct device_attribute *attr, char *buf)
3089 struct ptp_ocp *bp = dev_get_drvdata(dev);
3091 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3095 utc_tai_offset_store(struct device *dev,
3096 struct device_attribute *attr,
3097 const char *buf, size_t count)
3099 struct ptp_ocp *bp = dev_get_drvdata(dev);
3103 err = kstrtou32(buf, 0, &val);
3107 ptp_ocp_utc_distribute(bp, val);
3111 static DEVICE_ATTR_RW(utc_tai_offset);
3114 ts_window_adjust_show(struct device *dev,
3115 struct device_attribute *attr, char *buf)
3117 struct ptp_ocp *bp = dev_get_drvdata(dev);
3119 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3123 ts_window_adjust_store(struct device *dev,
3124 struct device_attribute *attr,
3125 const char *buf, size_t count)
3127 struct ptp_ocp *bp = dev_get_drvdata(dev);
3131 err = kstrtou32(buf, 0, &val);
3135 bp->ts_window_adjust = val;
3139 static DEVICE_ATTR_RW(ts_window_adjust);
3142 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3144 struct ptp_ocp *bp = dev_get_drvdata(dev);
3147 val = ioread32(&bp->irig_out->ctrl);
3148 val = (val >> 16) & 0x07;
3149 return sysfs_emit(buf, "%d\n", val);
3153 irig_b_mode_store(struct device *dev,
3154 struct device_attribute *attr,
3155 const char *buf, size_t count)
3157 struct ptp_ocp *bp = dev_get_drvdata(dev);
3158 unsigned long flags;
3163 err = kstrtou8(buf, 0, &val);
3169 reg = ((val & 0x7) << 16);
3171 spin_lock_irqsave(&bp->lock, flags);
3172 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3173 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3174 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3175 spin_unlock_irqrestore(&bp->lock, flags);
3179 static DEVICE_ATTR_RW(irig_b_mode);
3182 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3184 struct ptp_ocp *bp = dev_get_drvdata(dev);
3188 select = ioread32(&bp->reg->select);
3189 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3191 return sysfs_emit(buf, "%s\n", p);
3195 clock_source_store(struct device *dev, struct device_attribute *attr,
3196 const char *buf, size_t count)
3198 struct ptp_ocp *bp = dev_get_drvdata(dev);
3199 unsigned long flags;
3202 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3206 spin_lock_irqsave(&bp->lock, flags);
3207 iowrite32(val, &bp->reg->select);
3208 spin_unlock_irqrestore(&bp->lock, flags);
3212 static DEVICE_ATTR_RW(clock_source);
3215 available_clock_sources_show(struct device *dev,
3216 struct device_attribute *attr, char *buf)
3218 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3220 static DEVICE_ATTR_RO(available_clock_sources);
3223 clock_status_drift_show(struct device *dev,
3224 struct device_attribute *attr, char *buf)
3226 struct ptp_ocp *bp = dev_get_drvdata(dev);
3230 val = ioread32(&bp->reg->status_drift);
3231 res = (val & ~INT_MAX) ? -1 : 1;
3232 res *= (val & INT_MAX);
3233 return sysfs_emit(buf, "%d\n", res);
3235 static DEVICE_ATTR_RO(clock_status_drift);
3238 clock_status_offset_show(struct device *dev,
3239 struct device_attribute *attr, char *buf)
3241 struct ptp_ocp *bp = dev_get_drvdata(dev);
3245 val = ioread32(&bp->reg->status_offset);
3246 res = (val & ~INT_MAX) ? -1 : 1;
3247 res *= (val & INT_MAX);
3248 return sysfs_emit(buf, "%d\n", res);
3250 static DEVICE_ATTR_RO(clock_status_offset);
3253 tod_correction_show(struct device *dev,
3254 struct device_attribute *attr, char *buf)
3256 struct ptp_ocp *bp = dev_get_drvdata(dev);
3260 val = ioread32(&bp->tod->adj_sec);
3261 res = (val & ~INT_MAX) ? -1 : 1;
3262 res *= (val & INT_MAX);
3263 return sysfs_emit(buf, "%d\n", res);
3267 tod_correction_store(struct device *dev, struct device_attribute *attr,
3268 const char *buf, size_t count)
3270 struct ptp_ocp *bp = dev_get_drvdata(dev);
3271 unsigned long flags;
3275 err = kstrtos32(buf, 0, &res);
3284 spin_lock_irqsave(&bp->lock, flags);
3285 iowrite32(val, &bp->tod->adj_sec);
3286 spin_unlock_irqrestore(&bp->lock, flags);
3290 static DEVICE_ATTR_RW(tod_correction);
3292 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3293 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3294 &dev_attr_signal##_nr##_signal.attr.attr, \
3295 &dev_attr_signal##_nr##_duty.attr.attr, \
3296 &dev_attr_signal##_nr##_phase.attr.attr, \
3297 &dev_attr_signal##_nr##_period.attr.attr, \
3298 &dev_attr_signal##_nr##_polarity.attr.attr, \
3299 &dev_attr_signal##_nr##_running.attr.attr, \
3300 &dev_attr_signal##_nr##_start.attr.attr, \
3304 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3305 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3306 static const struct attribute_group \
3307 fb_timecard_signal##_nr##_group = { \
3309 .attrs = fb_timecard_signal##_nr##_attrs, \
3312 DEVICE_SIGNAL_GROUP(gen1, 0);
3313 DEVICE_SIGNAL_GROUP(gen2, 1);
3314 DEVICE_SIGNAL_GROUP(gen3, 2);
3315 DEVICE_SIGNAL_GROUP(gen4, 3);
3317 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3318 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3319 &dev_attr_freq##_nr##_seconds.attr.attr, \
3320 &dev_attr_freq##_nr##_frequency.attr.attr, \
3324 #define DEVICE_FREQ_GROUP(_name, _nr) \
3325 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3326 static const struct attribute_group \
3327 fb_timecard_freq##_nr##_group = { \
3329 .attrs = fb_timecard_freq##_nr##_attrs, \
3332 DEVICE_FREQ_GROUP(freq1, 0);
3333 DEVICE_FREQ_GROUP(freq2, 1);
3334 DEVICE_FREQ_GROUP(freq3, 2);
3335 DEVICE_FREQ_GROUP(freq4, 3);
3338 disciplining_config_read(struct file *filp, struct kobject *kobj,
3339 struct bin_attribute *bin_attr, char *buf,
3340 loff_t off, size_t count)
3342 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3343 size_t size = OCP_ART_CONFIG_SIZE;
3344 struct nvmem_device *nvmem;
3347 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3349 return PTR_ERR(nvmem);
3356 if (off + count > size)
3359 // the configuration is in the very beginning of the EEPROM
3360 err = nvmem_device_read(nvmem, off, count, buf);
3367 ptp_ocp_nvmem_device_put(&nvmem);
3373 disciplining_config_write(struct file *filp, struct kobject *kobj,
3374 struct bin_attribute *bin_attr, char *buf,
3375 loff_t off, size_t count)
3377 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3378 struct nvmem_device *nvmem;
3381 /* Allow write of the whole area only */
3382 if (off || count != OCP_ART_CONFIG_SIZE)
3385 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3387 return PTR_ERR(nvmem);
3389 err = nvmem_device_write(nvmem, 0x00, count, buf);
3393 ptp_ocp_nvmem_device_put(&nvmem);
3397 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3400 temperature_table_read(struct file *filp, struct kobject *kobj,
3401 struct bin_attribute *bin_attr, char *buf,
3402 loff_t off, size_t count)
3404 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3405 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3406 struct nvmem_device *nvmem;
3409 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3411 return PTR_ERR(nvmem);
3418 if (off + count > size)
3421 // the configuration is in the very beginning of the EEPROM
3422 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3429 ptp_ocp_nvmem_device_put(&nvmem);
3435 temperature_table_write(struct file *filp, struct kobject *kobj,
3436 struct bin_attribute *bin_attr, char *buf,
3437 loff_t off, size_t count)
3439 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3440 struct nvmem_device *nvmem;
3443 /* Allow write of the whole area only */
3444 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3447 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3449 return PTR_ERR(nvmem);
3451 err = nvmem_device_write(nvmem, 0x90, count, buf);
3455 ptp_ocp_nvmem_device_put(&nvmem);
3459 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3461 static struct attribute *fb_timecard_attrs[] = {
3462 &dev_attr_serialnum.attr,
3463 &dev_attr_gnss_sync.attr,
3464 &dev_attr_clock_source.attr,
3465 &dev_attr_available_clock_sources.attr,
3466 &dev_attr_sma1.attr,
3467 &dev_attr_sma2.attr,
3468 &dev_attr_sma3.attr,
3469 &dev_attr_sma4.attr,
3470 &dev_attr_available_sma_inputs.attr,
3471 &dev_attr_available_sma_outputs.attr,
3472 &dev_attr_clock_status_drift.attr,
3473 &dev_attr_clock_status_offset.attr,
3474 &dev_attr_irig_b_mode.attr,
3475 &dev_attr_utc_tai_offset.attr,
3476 &dev_attr_ts_window_adjust.attr,
3477 &dev_attr_tod_correction.attr,
3481 static const struct attribute_group fb_timecard_group = {
3482 .attrs = fb_timecard_attrs,
3485 static const struct ocp_attr_group fb_timecard_groups[] = {
3486 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3487 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3488 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3489 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3490 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3491 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3492 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3493 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3494 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3498 static struct attribute *art_timecard_attrs[] = {
3499 &dev_attr_serialnum.attr,
3500 &dev_attr_clock_source.attr,
3501 &dev_attr_available_clock_sources.attr,
3502 &dev_attr_utc_tai_offset.attr,
3503 &dev_attr_ts_window_adjust.attr,
3504 &dev_attr_sma1.attr,
3505 &dev_attr_sma2.attr,
3506 &dev_attr_sma3.attr,
3507 &dev_attr_sma4.attr,
3508 &dev_attr_available_sma_inputs.attr,
3509 &dev_attr_available_sma_outputs.attr,
3513 static struct bin_attribute *bin_art_timecard_attrs[] = {
3514 &bin_attr_disciplining_config,
3515 &bin_attr_temperature_table,
3519 static const struct attribute_group art_timecard_group = {
3520 .attrs = art_timecard_attrs,
3521 .bin_attrs = bin_art_timecard_attrs,
3524 static const struct ocp_attr_group art_timecard_groups[] = {
3525 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3530 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3535 for (i = 0; i < 4; i++) {
3536 if (bp->sma[i].mode != SMA_MODE_IN)
3538 if (map[i][0] & (1 << bit)) {
3539 sprintf(buf, "sma%d", i + 1);
3549 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3554 strcpy(ans, "----");
3555 for (i = 0; i < 4; i++) {
3556 if (bp->sma[i].mode != SMA_MODE_OUT)
3558 if (map[i][1] & (1 << bit))
3559 ans += sprintf(ans, "sma%d ", i + 1);
3564 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3566 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3567 struct ptp_ocp_signal *signal = &bp->signal[nr];
3575 on = signal->running;
3576 sprintf(label, "GEN%d", nr + 1);
3577 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3578 label, on ? " ON" : "OFF",
3579 signal->period, signal->duty, signal->phase,
3582 val = ioread32(®->enable);
3583 seq_printf(s, " [%x", val);
3584 val = ioread32(®->status);
3585 seq_printf(s, " %x]", val);
3587 seq_printf(s, " start:%llu\n", signal->start);
3591 _frequency_summary_show(struct seq_file *s, int nr,
3592 struct frequency_reg __iomem *reg)
3601 sprintf(label, "FREQ%d", nr + 1);
3602 val = ioread32(®->ctrl);
3604 val = (val >> 8) & 0xff;
3605 seq_printf(s, "%7s: %s, sec:%u",
3610 val = ioread32(®->status);
3611 if (val & FREQ_STATUS_ERROR)
3612 seq_printf(s, ", error");
3613 if (val & FREQ_STATUS_OVERRUN)
3614 seq_printf(s, ", overrun");
3615 if (val & FREQ_STATUS_VALID)
3616 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3617 seq_printf(s, " reg:%x\n", val);
3621 ptp_ocp_summary_show(struct seq_file *s, void *data)
3623 struct device *dev = s->private;
3624 struct ptp_system_timestamp sts;
3625 struct ts_reg __iomem *ts_reg;
3626 char *buf, *src, *mac_src;
3627 struct timespec64 ts;
3634 buf = (char *)__get_free_page(GFP_KERNEL);
3638 bp = dev_get_drvdata(dev);
3640 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3641 if (bp->gnss_port.line != -1)
3642 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3643 bp->gnss_port.line);
3644 if (bp->gnss2_port.line != -1)
3645 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3646 bp->gnss2_port.line);
3647 if (bp->mac_port.line != -1)
3648 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3649 if (bp->nmea_port.line != -1)
3650 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3652 memset(sma_val, 0xff, sizeof(sma_val));
3656 reg = ioread32(&bp->sma_map1->gpio1);
3657 sma_val[0][0] = reg & 0xffff;
3658 sma_val[1][0] = reg >> 16;
3660 reg = ioread32(&bp->sma_map1->gpio2);
3661 sma_val[2][1] = reg & 0xffff;
3662 sma_val[3][1] = reg >> 16;
3664 reg = ioread32(&bp->sma_map2->gpio1);
3665 sma_val[2][0] = reg & 0xffff;
3666 sma_val[3][0] = reg >> 16;
3668 reg = ioread32(&bp->sma_map2->gpio2);
3669 sma_val[0][1] = reg & 0xffff;
3670 sma_val[1][1] = reg >> 16;
3673 sma1_show(dev, NULL, buf);
3674 seq_printf(s, " sma1: %04x,%04x %s",
3675 sma_val[0][0], sma_val[0][1], buf);
3677 sma2_show(dev, NULL, buf);
3678 seq_printf(s, " sma2: %04x,%04x %s",
3679 sma_val[1][0], sma_val[1][1], buf);
3681 sma3_show(dev, NULL, buf);
3682 seq_printf(s, " sma3: %04x,%04x %s",
3683 sma_val[2][0], sma_val[2][1], buf);
3685 sma4_show(dev, NULL, buf);
3686 seq_printf(s, " sma4: %04x,%04x %s",
3687 sma_val[3][0], sma_val[3][1], buf);
3690 ts_reg = bp->ts0->mem;
3691 on = ioread32(&ts_reg->enable);
3693 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3694 on ? " ON" : "OFF", src);
3698 ts_reg = bp->ts1->mem;
3699 on = ioread32(&ts_reg->enable);
3700 gpio_input_map(buf, bp, sma_val, 2, NULL);
3701 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3702 on ? " ON" : "OFF", buf);
3706 ts_reg = bp->ts2->mem;
3707 on = ioread32(&ts_reg->enable);
3708 gpio_input_map(buf, bp, sma_val, 3, NULL);
3709 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3710 on ? " ON" : "OFF", buf);
3714 ts_reg = bp->ts3->mem;
3715 on = ioread32(&ts_reg->enable);
3716 gpio_input_map(buf, bp, sma_val, 6, NULL);
3717 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3718 on ? " ON" : "OFF", buf);
3722 ts_reg = bp->ts4->mem;
3723 on = ioread32(&ts_reg->enable);
3724 gpio_input_map(buf, bp, sma_val, 7, NULL);
3725 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3726 on ? " ON" : "OFF", buf);
3730 ts_reg = bp->pps->mem;
3732 on = ioread32(&ts_reg->enable);
3733 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3734 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3735 on && map ? " ON" : "OFF", src);
3737 map = !!(bp->pps_req_map & OCP_REQ_PPS);
3738 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3739 on && map ? " ON" : "OFF", src);
3742 if (bp->fw_cap & OCP_CAP_SIGNAL)
3743 for (i = 0; i < 4; i++)
3744 _signal_summary_show(s, bp, i);
3746 if (bp->fw_cap & OCP_CAP_FREQ)
3747 for (i = 0; i < 4; i++)
3748 _frequency_summary_show(s, i, bp->freq_in[i]);
3751 ctrl = ioread32(&bp->irig_out->ctrl);
3752 on = ctrl & IRIG_M_CTRL_ENABLE;
3753 val = ioread32(&bp->irig_out->status);
3754 gpio_output_map(buf, bp, sma_val, 4);
3755 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3756 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3760 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3761 val = ioread32(&bp->irig_in->status);
3762 gpio_input_map(buf, bp, sma_val, 4, NULL);
3763 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3764 on ? " ON" : "OFF", val, buf);
3768 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3769 val = ioread32(&bp->dcf_out->status);
3770 gpio_output_map(buf, bp, sma_val, 5);
3771 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3772 on ? " ON" : "OFF", val, buf);
3776 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3777 val = ioread32(&bp->dcf_in->status);
3778 gpio_input_map(buf, bp, sma_val, 5, NULL);
3779 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3780 on ? " ON" : "OFF", val, buf);
3784 on = ioread32(&bp->nmea_out->ctrl) & 1;
3785 val = ioread32(&bp->nmea_out->status);
3786 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3787 on ? " ON" : "OFF", val);
3790 /* compute src for PPS1, used below. */
3791 if (bp->pps_select) {
3792 val = ioread32(&bp->pps_select->gpio1);
3796 gpio_input_map(src, bp, sma_val, 0, NULL);
3798 } else if (val & 0x02) {
3800 } else if (val & 0x04) {
3810 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3812 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3813 seq_printf(s, "MAC PPS2 src: %s\n", buf);
3815 /* assumes automatic switchover/selection */
3816 val = ioread32(&bp->reg->select);
3817 switch (val >> 16) {
3819 sprintf(buf, "----");
3822 sprintf(buf, "IRIG");
3825 sprintf(buf, "%s via PPS1", src);
3828 sprintf(buf, "DCF");
3831 strcpy(buf, "unknown");
3834 val = ioread32(&bp->reg->status);
3835 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3836 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3838 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3839 struct timespec64 sys_ts;
3840 s64 pre_ns, post_ns, ns;
3842 pre_ns = timespec64_to_ns(&sts.pre_ts);
3843 post_ns = timespec64_to_ns(&sts.post_ts);
3844 ns = (pre_ns + post_ns) / 2;
3845 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3846 sys_ts = ns_to_timespec64(ns);
3848 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3849 ts.tv_sec, ts.tv_nsec, &ts);
3850 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3851 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3852 bp->utc_tai_offset);
3853 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
3854 timespec64_to_ns(&ts) - ns,
3858 free_page((unsigned long)buf);
3861 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3864 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3866 struct device *dev = s->private;
3871 bp = dev_get_drvdata(dev);
3873 val = ioread32(&bp->tod->ctrl);
3874 if (!(val & TOD_CTRL_ENABLE)) {
3875 seq_printf(s, "TOD Slave disabled\n");
3878 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3880 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3881 idx += (val >> 16) & 3;
3882 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3884 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3885 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3887 val = ioread32(&bp->tod->version);
3888 seq_printf(s, "TOD Version %d.%d.%d\n",
3889 val >> 24, (val >> 16) & 0xff, val & 0xffff);
3891 val = ioread32(&bp->tod->status);
3892 seq_printf(s, "Status register: 0x%08X\n", val);
3894 val = ioread32(&bp->tod->adj_sec);
3895 idx = (val & ~INT_MAX) ? -1 : 1;
3896 idx *= (val & INT_MAX);
3897 seq_printf(s, "Correction seconds: %d\n", idx);
3899 val = ioread32(&bp->tod->utc_status);
3900 seq_printf(s, "UTC status register: 0x%08X\n", val);
3901 seq_printf(s, "UTC offset: %ld valid:%d\n",
3902 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3903 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3904 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3905 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3907 val = ioread32(&bp->tod->leap);
3908 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3912 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3914 static struct dentry *ptp_ocp_debugfs_root;
3917 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3921 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3923 debugfs_create_file("summary", 0444, bp->debug_root,
3924 &bp->dev, &ptp_ocp_summary_fops);
3926 debugfs_create_file("tod_status", 0444, bp->debug_root,
3927 &bp->dev, &ptp_ocp_tod_status_fops);
3931 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3933 debugfs_remove_recursive(bp->debug_root);
3937 ptp_ocp_debugfs_init(void)
3939 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3943 ptp_ocp_debugfs_fini(void)
3945 debugfs_remove_recursive(ptp_ocp_debugfs_root);
3949 ptp_ocp_dev_release(struct device *dev)
3951 struct ptp_ocp *bp = dev_get_drvdata(dev);
3953 mutex_lock(&ptp_ocp_lock);
3954 idr_remove(&ptp_ocp_idr, bp->id);
3955 mutex_unlock(&ptp_ocp_lock);
3959 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3963 mutex_lock(&ptp_ocp_lock);
3964 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3965 mutex_unlock(&ptp_ocp_lock);
3967 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3972 bp->ptp_info = ptp_ocp_clock_info;
3973 spin_lock_init(&bp->lock);
3974 bp->gnss_port.line = -1;
3975 bp->gnss2_port.line = -1;
3976 bp->mac_port.line = -1;
3977 bp->nmea_port.line = -1;
3980 device_initialize(&bp->dev);
3981 dev_set_name(&bp->dev, "ocp%d", bp->id);
3982 bp->dev.class = &timecard_class;
3983 bp->dev.parent = &pdev->dev;
3984 bp->dev.release = ptp_ocp_dev_release;
3985 dev_set_drvdata(&bp->dev, bp);
3987 err = device_add(&bp->dev);
3989 dev_err(&bp->dev, "device add failed: %d\n", err);
3993 pci_set_drvdata(pdev, bp);
3998 ptp_ocp_dev_release(&bp->dev);
3999 put_device(&bp->dev);
4004 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4006 struct device *dev = &bp->dev;
4008 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4009 dev_err(dev, "%s symlink failed\n", link);
4013 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4015 struct device *dev, *child;
4017 dev = &bp->pdev->dev;
4019 child = device_find_child_by_name(dev, name);
4021 dev_err(dev, "Could not find device %s\n", name);
4025 ptp_ocp_symlink(bp, child, link);
4030 ptp_ocp_complete(struct ptp_ocp *bp)
4032 struct pps_device *pps;
4035 if (bp->gnss_port.line != -1) {
4036 sprintf(buf, "ttyS%d", bp->gnss_port.line);
4037 ptp_ocp_link_child(bp, buf, "ttyGNSS");
4039 if (bp->gnss2_port.line != -1) {
4040 sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4041 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4043 if (bp->mac_port.line != -1) {
4044 sprintf(buf, "ttyS%d", bp->mac_port.line);
4045 ptp_ocp_link_child(bp, buf, "ttyMAC");
4047 if (bp->nmea_port.line != -1) {
4048 sprintf(buf, "ttyS%d", bp->nmea_port.line);
4049 ptp_ocp_link_child(bp, buf, "ttyNMEA");
4051 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4052 ptp_ocp_link_child(bp, buf, "ptp");
4054 pps = pps_lookup_dev(bp->ptp);
4056 ptp_ocp_symlink(bp, pps->dev, "pps");
4058 ptp_ocp_debugfs_add_device(bp);
4064 ptp_ocp_phc_info(struct ptp_ocp *bp)
4066 struct timespec64 ts;
4067 u32 version, select;
4070 version = ioread32(&bp->reg->version);
4071 select = ioread32(&bp->reg->select);
4072 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4073 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4074 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4075 ptp_clock_index(bp->ptp));
4077 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
4078 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4079 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4080 ts.tv_sec, ts.tv_nsec,
4081 sync ? "in-sync" : "UNSYNCED");
4085 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4088 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4092 ptp_ocp_info(struct ptp_ocp *bp)
4094 static int nmea_baud[] = {
4095 1200, 2400, 4800, 9600, 19200, 38400,
4096 57600, 115200, 230400, 460800, 921600,
4099 struct device *dev = &bp->pdev->dev;
4102 ptp_ocp_phc_info(bp);
4104 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4105 bp->gnss_port.baud);
4106 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4107 bp->gnss2_port.baud);
4108 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4109 if (bp->nmea_out && bp->nmea_port.line != -1) {
4110 bp->nmea_port.baud = -1;
4112 reg = ioread32(&bp->nmea_out->uart_baud);
4113 if (reg < ARRAY_SIZE(nmea_baud))
4114 bp->nmea_port.baud = nmea_baud[reg];
4116 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4117 bp->nmea_port.baud);
4122 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4124 struct device *dev = &bp->dev;
4126 sysfs_remove_link(&dev->kobj, "ttyGNSS");
4127 sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4128 sysfs_remove_link(&dev->kobj, "ttyMAC");
4129 sysfs_remove_link(&dev->kobj, "ptp");
4130 sysfs_remove_link(&dev->kobj, "pps");
4134 ptp_ocp_detach(struct ptp_ocp *bp)
4138 ptp_ocp_debugfs_remove_device(bp);
4139 ptp_ocp_detach_sysfs(bp);
4140 ptp_ocp_attr_group_del(bp);
4141 if (timer_pending(&bp->watchdog))
4142 del_timer_sync(&bp->watchdog);
4144 ptp_ocp_unregister_ext(bp->ts0);
4146 ptp_ocp_unregister_ext(bp->ts1);
4148 ptp_ocp_unregister_ext(bp->ts2);
4150 ptp_ocp_unregister_ext(bp->ts3);
4152 ptp_ocp_unregister_ext(bp->ts4);
4154 ptp_ocp_unregister_ext(bp->pps);
4155 for (i = 0; i < 4; i++)
4156 if (bp->signal_out[i])
4157 ptp_ocp_unregister_ext(bp->signal_out[i]);
4158 if (bp->gnss_port.line != -1)
4159 serial8250_unregister_port(bp->gnss_port.line);
4160 if (bp->gnss2_port.line != -1)
4161 serial8250_unregister_port(bp->gnss2_port.line);
4162 if (bp->mac_port.line != -1)
4163 serial8250_unregister_port(bp->mac_port.line);
4164 if (bp->nmea_port.line != -1)
4165 serial8250_unregister_port(bp->nmea_port.line);
4166 platform_device_unregister(bp->spi_flash);
4167 platform_device_unregister(bp->i2c_ctrl);
4169 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4171 pci_free_irq_vectors(bp->pdev);
4173 ptp_clock_unregister(bp->ptp);
4174 kfree(bp->ptp_info.pin_config);
4175 device_unregister(&bp->dev);
4179 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4181 struct devlink *devlink;
4185 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4187 dev_err(&pdev->dev, "devlink_alloc failed\n");
4191 err = pci_enable_device(pdev);
4193 dev_err(&pdev->dev, "pci_enable_device\n");
4197 bp = devlink_priv(devlink);
4198 err = ptp_ocp_device_init(bp, pdev);
4203 * Older FPGA firmware only returns 2 irq's.
4204 * allow this - if not all of the IRQ's are returned, skip the
4205 * extra devices and just register the clock.
4207 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4209 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4213 pci_set_master(pdev);
4215 err = ptp_ocp_register_resources(bp, id->driver_data);
4219 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4220 if (IS_ERR(bp->ptp)) {
4221 err = PTR_ERR(bp->ptp);
4222 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4227 err = ptp_ocp_complete(bp);
4232 devlink_register(devlink);
4238 pci_disable_device(pdev);
4240 devlink_free(devlink);
4245 ptp_ocp_remove(struct pci_dev *pdev)
4247 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4248 struct devlink *devlink = priv_to_devlink(bp);
4250 devlink_unregister(devlink);
4252 pci_disable_device(pdev);
4254 devlink_free(devlink);
4257 static struct pci_driver ptp_ocp_driver = {
4258 .name = KBUILD_MODNAME,
4259 .id_table = ptp_ocp_pcidev_id,
4260 .probe = ptp_ocp_probe,
4261 .remove = ptp_ocp_remove,
4265 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4266 unsigned long action, void *data)
4268 struct device *dev, *child = data;
4273 case BUS_NOTIFY_ADD_DEVICE:
4274 case BUS_NOTIFY_DEL_DEVICE:
4275 add = action == BUS_NOTIFY_ADD_DEVICE;
4281 if (!i2c_verify_adapter(child))
4285 while ((dev = dev->parent))
4286 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4291 bp = dev_get_drvdata(dev);
4293 ptp_ocp_symlink(bp, child, "i2c");
4295 sysfs_remove_link(&bp->dev.kobj, "i2c");
4300 static struct notifier_block ptp_ocp_i2c_notifier = {
4301 .notifier_call = ptp_ocp_i2c_notifier_call,
4310 ptp_ocp_debugfs_init();
4312 what = "timecard class";
4313 err = class_register(&timecard_class);
4317 what = "i2c notifier";
4318 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4322 what = "ptp_ocp driver";
4323 err = pci_register_driver(&ptp_ocp_driver);
4330 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4332 class_unregister(&timecard_class);
4334 ptp_ocp_debugfs_fini();
4335 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4342 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4343 pci_unregister_driver(&ptp_ocp_driver);
4344 class_unregister(&timecard_class);
4345 ptp_ocp_debugfs_fini();
4348 module_init(ptp_ocp_init);
4349 module_exit(ptp_ocp_fini);
4351 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4352 MODULE_LICENSE("GPL v2");