1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
4 #include <linux/bits.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36 static struct class timecard_class = {
65 #define OCP_CTRL_ENABLE BIT(0)
66 #define OCP_CTRL_ADJUST_TIME BIT(1)
67 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
68 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
69 #define OCP_CTRL_ADJUST_SERVO BIT(8)
70 #define OCP_CTRL_READ_TIME_REQ BIT(30)
71 #define OCP_CTRL_READ_TIME_DONE BIT(31)
73 #define OCP_STATUS_IN_SYNC BIT(0)
74 #define OCP_STATUS_IN_HOLDOVER BIT(1)
76 #define OCP_SELECT_CLK_NONE 0
77 #define OCP_SELECT_CLK_REG 0xfe
92 #define TOD_CTRL_PROTOCOL BIT(28)
93 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
94 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
95 #define TOD_CTRL_ENABLE BIT(0)
96 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
97 #define TOD_CTRL_GNSS_SHIFT 24
99 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
100 #define TOD_STATUS_UTC_VALID BIT(8)
101 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
102 #define TOD_STATUS_LEAP_VALID BIT(16)
130 #define PPS_STATUS_FILTER_ERR BIT(0)
131 #define PPS_STATUS_SUPERV_ERR BIT(1)
144 struct irig_master_reg {
153 #define IRIG_M_CTRL_ENABLE BIT(0)
155 struct irig_slave_reg {
164 #define IRIG_S_CTRL_ENABLE BIT(0)
166 struct dcf_master_reg {
174 #define DCF_M_CTRL_ENABLE BIT(0)
176 struct dcf_slave_reg {
184 #define DCF_S_CTRL_ENABLE BIT(0)
206 struct frequency_reg {
211 struct board_config_reg {
212 u32 mro50_serial_activate;
215 #define FREQ_STATUS_VALID BIT(31)
216 #define FREQ_STATUS_ERROR BIT(30)
217 #define FREQ_STATUS_OVERRUN BIT(29)
218 #define FREQ_STATUS_MASK GENMASK(23, 0)
220 struct ptp_ocp_flash_info {
227 struct ptp_ocp_firmware_header {
229 __be16 pci_vendor_id;
230 __be16 pci_device_id;
236 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
238 struct ptp_ocp_i2c_info {
240 unsigned long fixed_rate;
245 struct ptp_ocp_ext_info {
247 irqreturn_t (*irq_fcn)(int irq, void *priv);
248 int (*enable)(void *priv, u32 req, bool enable);
251 struct ptp_ocp_ext_src {
254 struct ptp_ocp_ext_info *info;
258 enum ptp_ocp_sma_mode {
263 struct ptp_ocp_sma_connector {
264 enum ptp_ocp_sma_mode mode;
271 struct ocp_attr_group {
273 const struct attribute_group *group;
276 #define OCP_CAP_BASIC BIT(0)
277 #define OCP_CAP_SIGNAL BIT(1)
278 #define OCP_CAP_FREQ BIT(2)
280 struct ptp_ocp_signal {
290 struct ptp_ocp_serial_port {
295 #define OCP_BOARD_ID_LEN 13
296 #define OCP_SERIAL_LEN 6
299 struct pci_dev *pdev;
302 struct ocp_reg __iomem *reg;
303 struct tod_reg __iomem *tod;
304 struct pps_reg __iomem *pps_to_ext;
305 struct pps_reg __iomem *pps_to_clk;
306 struct board_config_reg __iomem *board_config;
307 struct gpio_reg __iomem *pps_select;
308 struct gpio_reg __iomem *sma_map1;
309 struct gpio_reg __iomem *sma_map2;
310 struct irig_master_reg __iomem *irig_out;
311 struct irig_slave_reg __iomem *irig_in;
312 struct dcf_master_reg __iomem *dcf_out;
313 struct dcf_slave_reg __iomem *dcf_in;
314 struct tod_reg __iomem *nmea_out;
315 struct frequency_reg __iomem *freq_in[4];
316 struct ptp_ocp_ext_src *signal_out[4];
317 struct ptp_ocp_ext_src *pps;
318 struct ptp_ocp_ext_src *ts0;
319 struct ptp_ocp_ext_src *ts1;
320 struct ptp_ocp_ext_src *ts2;
321 struct ptp_ocp_ext_src *ts3;
322 struct ptp_ocp_ext_src *ts4;
323 struct ocp_art_gpio_reg __iomem *art_sma;
324 struct img_reg __iomem *image;
325 struct ptp_clock *ptp;
326 struct ptp_clock_info ptp_info;
327 struct platform_device *i2c_ctrl;
328 struct platform_device *spi_flash;
329 struct clk_hw *i2c_clk;
330 struct timer_list watchdog;
331 const struct attribute_group **attr_group;
332 const struct ptp_ocp_eeprom_map *eeprom_map;
333 struct dentry *debug_root;
337 struct ptp_ocp_serial_port gnss_port;
338 struct ptp_ocp_serial_port gnss2_port;
339 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */
340 struct ptp_ocp_serial_port nmea_port;
344 u8 board_id[OCP_BOARD_ID_LEN];
345 u8 serial[OCP_SERIAL_LEN];
346 bool has_eeprom_data;
350 u32 ts_window_adjust;
352 struct ptp_ocp_signal signal[4];
353 struct ptp_ocp_sma_connector sma[4];
354 const struct ocp_sma_op *sma_op;
357 #define OCP_REQ_TIMESTAMP BIT(0)
358 #define OCP_REQ_PPS BIT(1)
360 struct ocp_resource {
361 unsigned long offset;
364 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
366 unsigned long bp_offset;
367 const char * const name;
370 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
371 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
372 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
373 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
374 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
375 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
376 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
377 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
378 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
379 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
380 struct ptp_perout_request *req);
381 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
382 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
384 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
386 static const struct ocp_attr_group fb_timecard_groups[];
388 static const struct ocp_attr_group art_timecard_groups[];
390 struct ptp_ocp_eeprom_map {
394 const void * const tag;
397 #define EEPROM_ENTRY(addr, member) \
399 .len = sizeof_field(struct ptp_ocp, member), \
400 .bp_offset = offsetof(struct ptp_ocp, member)
402 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
403 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
406 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
407 { EEPROM_ENTRY(0x43, board_id) },
408 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
412 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
413 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
414 { EEPROM_ENTRY(0x200 + 0x63, serial) },
418 #define bp_assign_entry(bp, res, val) ({ \
419 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
420 *(typeof(val) *)addr = val; \
423 #define OCP_RES_LOCATION(member) \
424 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
426 #define OCP_MEM_RESOURCE(member) \
427 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
429 #define OCP_SERIAL_RESOURCE(member) \
430 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
432 #define OCP_I2C_RESOURCE(member) \
433 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
435 #define OCP_SPI_RESOURCE(member) \
436 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
438 #define OCP_EXT_RESOURCE(member) \
439 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
441 /* This is the MSI vector mapping used.
450 * 8: HWICAP (notused)
453 * 11: Signal Generator 1
454 * 12: Signal Generator 2
455 * 13: Signal Generator 3
456 * 14: Signal Generator 4
462 * 11: Orolia TS0 (GNSS)
468 static struct ocp_resource ocp_fb_resource[] = {
470 OCP_MEM_RESOURCE(reg),
471 .offset = 0x01000000, .size = 0x10000,
474 OCP_EXT_RESOURCE(ts0),
475 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
476 .extra = &(struct ptp_ocp_ext_info) {
478 .irq_fcn = ptp_ocp_ts_irq,
479 .enable = ptp_ocp_ts_enable,
483 OCP_EXT_RESOURCE(ts1),
484 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
485 .extra = &(struct ptp_ocp_ext_info) {
487 .irq_fcn = ptp_ocp_ts_irq,
488 .enable = ptp_ocp_ts_enable,
492 OCP_EXT_RESOURCE(ts2),
493 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
494 .extra = &(struct ptp_ocp_ext_info) {
496 .irq_fcn = ptp_ocp_ts_irq,
497 .enable = ptp_ocp_ts_enable,
501 OCP_EXT_RESOURCE(ts3),
502 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
503 .extra = &(struct ptp_ocp_ext_info) {
505 .irq_fcn = ptp_ocp_ts_irq,
506 .enable = ptp_ocp_ts_enable,
510 OCP_EXT_RESOURCE(ts4),
511 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
512 .extra = &(struct ptp_ocp_ext_info) {
514 .irq_fcn = ptp_ocp_ts_irq,
515 .enable = ptp_ocp_ts_enable,
518 /* Timestamp for PHC and/or PPS generator */
520 OCP_EXT_RESOURCE(pps),
521 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
522 .extra = &(struct ptp_ocp_ext_info) {
524 .irq_fcn = ptp_ocp_ts_irq,
525 .enable = ptp_ocp_ts_enable,
529 OCP_EXT_RESOURCE(signal_out[0]),
530 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
531 .extra = &(struct ptp_ocp_ext_info) {
533 .irq_fcn = ptp_ocp_signal_irq,
534 .enable = ptp_ocp_signal_enable,
538 OCP_EXT_RESOURCE(signal_out[1]),
539 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
540 .extra = &(struct ptp_ocp_ext_info) {
542 .irq_fcn = ptp_ocp_signal_irq,
543 .enable = ptp_ocp_signal_enable,
547 OCP_EXT_RESOURCE(signal_out[2]),
548 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
549 .extra = &(struct ptp_ocp_ext_info) {
551 .irq_fcn = ptp_ocp_signal_irq,
552 .enable = ptp_ocp_signal_enable,
556 OCP_EXT_RESOURCE(signal_out[3]),
557 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
558 .extra = &(struct ptp_ocp_ext_info) {
560 .irq_fcn = ptp_ocp_signal_irq,
561 .enable = ptp_ocp_signal_enable,
565 OCP_MEM_RESOURCE(pps_to_ext),
566 .offset = 0x01030000, .size = 0x10000,
569 OCP_MEM_RESOURCE(pps_to_clk),
570 .offset = 0x01040000, .size = 0x10000,
573 OCP_MEM_RESOURCE(tod),
574 .offset = 0x01050000, .size = 0x10000,
577 OCP_MEM_RESOURCE(irig_in),
578 .offset = 0x01070000, .size = 0x10000,
581 OCP_MEM_RESOURCE(irig_out),
582 .offset = 0x01080000, .size = 0x10000,
585 OCP_MEM_RESOURCE(dcf_in),
586 .offset = 0x01090000, .size = 0x10000,
589 OCP_MEM_RESOURCE(dcf_out),
590 .offset = 0x010A0000, .size = 0x10000,
593 OCP_MEM_RESOURCE(nmea_out),
594 .offset = 0x010B0000, .size = 0x10000,
597 OCP_MEM_RESOURCE(image),
598 .offset = 0x00020000, .size = 0x1000,
601 OCP_MEM_RESOURCE(pps_select),
602 .offset = 0x00130000, .size = 0x1000,
605 OCP_MEM_RESOURCE(sma_map1),
606 .offset = 0x00140000, .size = 0x1000,
609 OCP_MEM_RESOURCE(sma_map2),
610 .offset = 0x00220000, .size = 0x1000,
613 OCP_I2C_RESOURCE(i2c_ctrl),
614 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
615 .extra = &(struct ptp_ocp_i2c_info) {
617 .fixed_rate = 50000000,
618 .data_size = sizeof(struct xiic_i2c_platform_data),
619 .data = &(struct xiic_i2c_platform_data) {
621 .devices = (struct i2c_board_info[]) {
622 { I2C_BOARD_INFO("24c02", 0x50) },
623 { I2C_BOARD_INFO("24mac402", 0x58),
624 .platform_data = "mac" },
630 OCP_SERIAL_RESOURCE(gnss_port),
631 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
632 .extra = &(struct ptp_ocp_serial_port) {
637 OCP_SERIAL_RESOURCE(gnss2_port),
638 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
639 .extra = &(struct ptp_ocp_serial_port) {
644 OCP_SERIAL_RESOURCE(mac_port),
645 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
646 .extra = &(struct ptp_ocp_serial_port) {
651 OCP_SERIAL_RESOURCE(nmea_port),
652 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
655 OCP_SPI_RESOURCE(spi_flash),
656 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
657 .extra = &(struct ptp_ocp_flash_info) {
658 .name = "xilinx_spi", .pci_offset = 0,
659 .data_size = sizeof(struct xspi_platform_data),
660 .data = &(struct xspi_platform_data) {
664 .devices = &(struct spi_board_info) {
665 .modalias = "spi-nor",
671 OCP_MEM_RESOURCE(freq_in[0]),
672 .offset = 0x01200000, .size = 0x10000,
675 OCP_MEM_RESOURCE(freq_in[1]),
676 .offset = 0x01210000, .size = 0x10000,
679 OCP_MEM_RESOURCE(freq_in[2]),
680 .offset = 0x01220000, .size = 0x10000,
683 OCP_MEM_RESOURCE(freq_in[3]),
684 .offset = 0x01230000, .size = 0x10000,
687 .setup = ptp_ocp_fb_board_init,
692 #define OCP_ART_CONFIG_SIZE 144
693 #define OCP_ART_TEMP_TABLE_SIZE 368
695 struct ocp_art_gpio_reg {
702 static struct ocp_resource ocp_art_resource[] = {
704 OCP_MEM_RESOURCE(reg),
705 .offset = 0x01000000, .size = 0x10000,
708 OCP_SERIAL_RESOURCE(gnss_port),
709 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
710 .extra = &(struct ptp_ocp_serial_port) {
715 OCP_MEM_RESOURCE(art_sma),
716 .offset = 0x003C0000, .size = 0x1000,
718 /* Timestamp associated with GNSS1 receiver PPS */
720 OCP_EXT_RESOURCE(ts0),
721 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
722 .extra = &(struct ptp_ocp_ext_info) {
724 .irq_fcn = ptp_ocp_ts_irq,
725 .enable = ptp_ocp_ts_enable,
729 OCP_EXT_RESOURCE(ts1),
730 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
731 .extra = &(struct ptp_ocp_ext_info) {
733 .irq_fcn = ptp_ocp_ts_irq,
734 .enable = ptp_ocp_ts_enable,
738 OCP_EXT_RESOURCE(ts2),
739 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
740 .extra = &(struct ptp_ocp_ext_info) {
742 .irq_fcn = ptp_ocp_ts_irq,
743 .enable = ptp_ocp_ts_enable,
747 OCP_EXT_RESOURCE(ts3),
748 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
749 .extra = &(struct ptp_ocp_ext_info) {
751 .irq_fcn = ptp_ocp_ts_irq,
752 .enable = ptp_ocp_ts_enable,
756 OCP_EXT_RESOURCE(ts4),
757 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
758 .extra = &(struct ptp_ocp_ext_info) {
760 .irq_fcn = ptp_ocp_ts_irq,
761 .enable = ptp_ocp_ts_enable,
764 /* Timestamp associated with Internal PPS of the card */
766 OCP_EXT_RESOURCE(pps),
767 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
768 .extra = &(struct ptp_ocp_ext_info) {
770 .irq_fcn = ptp_ocp_ts_irq,
771 .enable = ptp_ocp_ts_enable,
775 OCP_SPI_RESOURCE(spi_flash),
776 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
777 .extra = &(struct ptp_ocp_flash_info) {
778 .name = "spi_altera", .pci_offset = 0,
779 .data_size = sizeof(struct altera_spi_platform_data),
780 .data = &(struct altera_spi_platform_data) {
783 .devices = &(struct spi_board_info) {
784 .modalias = "spi-nor",
790 OCP_I2C_RESOURCE(i2c_ctrl),
791 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
792 .extra = &(struct ptp_ocp_i2c_info) {
793 .name = "ocores-i2c",
794 .fixed_rate = 400000,
795 .data_size = sizeof(struct ocores_i2c_platform_data),
796 .data = &(struct ocores_i2c_platform_data) {
800 .devices = &(struct i2c_board_info) {
801 I2C_BOARD_INFO("24c08", 0x50),
807 OCP_SERIAL_RESOURCE(mac_port),
808 .offset = 0x00190000, .irq_vec = 7,
809 .extra = &(struct ptp_ocp_serial_port) {
814 OCP_MEM_RESOURCE(board_config),
815 .offset = 0x210000, .size = 0x1000,
818 .setup = ptp_ocp_art_board_init,
823 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
824 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
825 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
826 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
829 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
831 static DEFINE_MUTEX(ptp_ocp_lock);
832 static DEFINE_IDR(ptp_ocp_idr);
834 struct ocp_selector {
839 static const struct ocp_selector ptp_ocp_clock[] = {
840 { .name = "NONE", .value = 0 },
841 { .name = "TOD", .value = 1 },
842 { .name = "IRIG", .value = 2 },
843 { .name = "PPS", .value = 3 },
844 { .name = "PTP", .value = 4 },
845 { .name = "RTC", .value = 5 },
846 { .name = "DCF", .value = 6 },
847 { .name = "REGS", .value = 0xfe },
848 { .name = "EXT", .value = 0xff },
852 #define SMA_DISABLE BIT(16)
853 #define SMA_ENABLE BIT(15)
854 #define SMA_SELECT_MASK GENMASK(14, 0)
856 static const struct ocp_selector ptp_ocp_sma_in[] = {
857 { .name = "10Mhz", .value = 0x0000 },
858 { .name = "PPS1", .value = 0x0001 },
859 { .name = "PPS2", .value = 0x0002 },
860 { .name = "TS1", .value = 0x0004 },
861 { .name = "TS2", .value = 0x0008 },
862 { .name = "IRIG", .value = 0x0010 },
863 { .name = "DCF", .value = 0x0020 },
864 { .name = "TS3", .value = 0x0040 },
865 { .name = "TS4", .value = 0x0080 },
866 { .name = "FREQ1", .value = 0x0100 },
867 { .name = "FREQ2", .value = 0x0200 },
868 { .name = "FREQ3", .value = 0x0400 },
869 { .name = "FREQ4", .value = 0x0800 },
870 { .name = "None", .value = SMA_DISABLE },
874 static const struct ocp_selector ptp_ocp_sma_out[] = {
875 { .name = "10Mhz", .value = 0x0000 },
876 { .name = "PHC", .value = 0x0001 },
877 { .name = "MAC", .value = 0x0002 },
878 { .name = "GNSS1", .value = 0x0004 },
879 { .name = "GNSS2", .value = 0x0008 },
880 { .name = "IRIG", .value = 0x0010 },
881 { .name = "DCF", .value = 0x0020 },
882 { .name = "GEN1", .value = 0x0040 },
883 { .name = "GEN2", .value = 0x0080 },
884 { .name = "GEN3", .value = 0x0100 },
885 { .name = "GEN4", .value = 0x0200 },
886 { .name = "GND", .value = 0x2000 },
887 { .name = "VCC", .value = 0x4000 },
891 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
892 { .name = "PPS1", .value = 0x0001 },
893 { .name = "10Mhz", .value = 0x0008 },
897 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
898 { .name = "PHC", .value = 0x0002 },
899 { .name = "GNSS", .value = 0x0004 },
900 { .name = "10Mhz", .value = 0x0010 },
905 const struct ocp_selector *tbl[2];
906 void (*init)(struct ptp_ocp *bp);
907 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
908 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
909 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
913 ptp_ocp_sma_init(struct ptp_ocp *bp)
915 return bp->sma_op->init(bp);
919 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
921 return bp->sma_op->get(bp, sma_nr);
925 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
927 return bp->sma_op->set_inputs(bp, sma_nr, val);
931 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
933 return bp->sma_op->set_output(bp, sma_nr, val);
937 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
941 for (i = 0; tbl[i].name; i++)
942 if (tbl[i].value == val)
948 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
953 for (i = 0; tbl[i].name; i++) {
954 select = tbl[i].name;
955 if (!strncasecmp(name, select, strlen(select)))
962 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
968 for (i = 0; tbl[i].name; i++)
969 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
972 count += sysfs_emit_at(buf, count, "\n");
977 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
978 struct ptp_system_timestamp *sts)
980 u32 ctrl, time_sec, time_ns;
983 ptp_read_system_prets(sts);
985 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
986 iowrite32(ctrl, &bp->reg->ctrl);
988 for (i = 0; i < 100; i++) {
989 ctrl = ioread32(&bp->reg->ctrl);
990 if (ctrl & OCP_CTRL_READ_TIME_DONE)
993 ptp_read_system_postts(sts);
995 if (sts && bp->ts_window_adjust) {
996 s64 ns = timespec64_to_ns(&sts->post_ts);
998 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1001 time_ns = ioread32(&bp->reg->time_ns);
1002 time_sec = ioread32(&bp->reg->time_sec);
1004 ts->tv_sec = time_sec;
1005 ts->tv_nsec = time_ns;
1007 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1011 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1012 struct ptp_system_timestamp *sts)
1014 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1015 unsigned long flags;
1018 spin_lock_irqsave(&bp->lock, flags);
1019 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1020 spin_unlock_irqrestore(&bp->lock, flags);
1026 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1028 u32 ctrl, time_sec, time_ns;
1031 time_ns = ts->tv_nsec;
1032 time_sec = ts->tv_sec;
1034 select = ioread32(&bp->reg->select);
1035 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1037 iowrite32(time_ns, &bp->reg->adjust_ns);
1038 iowrite32(time_sec, &bp->reg->adjust_sec);
1040 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1041 iowrite32(ctrl, &bp->reg->ctrl);
1043 /* restore clock selection */
1044 iowrite32(select >> 16, &bp->reg->select);
1048 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1050 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1051 unsigned long flags;
1053 spin_lock_irqsave(&bp->lock, flags);
1054 __ptp_ocp_settime_locked(bp, ts);
1055 spin_unlock_irqrestore(&bp->lock, flags);
1061 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1065 select = ioread32(&bp->reg->select);
1066 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1068 iowrite32(adj_val, &bp->reg->offset_ns);
1069 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1071 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1072 iowrite32(ctrl, &bp->reg->ctrl);
1074 /* restore clock selection */
1075 iowrite32(select >> 16, &bp->reg->select);
1079 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1081 struct timespec64 ts;
1082 unsigned long flags;
1085 spin_lock_irqsave(&bp->lock, flags);
1086 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1088 set_normalized_timespec64(&ts, ts.tv_sec,
1089 ts.tv_nsec + delta_ns);
1090 __ptp_ocp_settime_locked(bp, &ts);
1092 spin_unlock_irqrestore(&bp->lock, flags);
1096 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1098 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1099 unsigned long flags;
1102 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1103 ptp_ocp_adjtime_coarse(bp, delta_ns);
1107 sign = delta_ns < 0 ? BIT(31) : 0;
1108 adj_ns = sign ? -delta_ns : delta_ns;
1110 spin_lock_irqsave(&bp->lock, flags);
1111 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1112 spin_unlock_irqrestore(&bp->lock, flags);
1118 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1120 if (scaled_ppm == 0)
1127 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1133 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1136 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1137 struct ptp_ocp_ext_src *ext = NULL;
1142 case PTP_CLK_REQ_EXTTS:
1143 req = OCP_REQ_TIMESTAMP;
1144 switch (rq->extts.index) {
1165 case PTP_CLK_REQ_PPS:
1169 case PTP_CLK_REQ_PEROUT:
1170 switch (rq->perout.index) {
1172 /* This is a request for 1PPS on an output SMA.
1173 * Allow, but assume manual configuration.
1175 if (on && (rq->perout.period.sec != 1 ||
1176 rq->perout.period.nsec != 0))
1183 req = rq->perout.index - 1;
1184 ext = bp->signal_out[req];
1185 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1197 err = ext->info->enable(ext, req, on);
1203 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1204 enum ptp_pin_function func, unsigned chan)
1206 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1211 snprintf(buf, sizeof(buf), "IN: None");
1214 /* Allow timestamps, but require sysfs configuration. */
1217 /* channel 0 is 1PPS from PHC.
1218 * channels 1..4 are the frequency generators.
1221 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1223 snprintf(buf, sizeof(buf), "OUT: PHC");
1229 return ptp_ocp_sma_store(bp, buf, pin + 1);
1232 static const struct ptp_clock_info ptp_ocp_clock_info = {
1233 .owner = THIS_MODULE,
1234 .name = KBUILD_MODNAME,
1235 .max_adj = 100000000,
1236 .gettimex64 = ptp_ocp_gettimex,
1237 .settime64 = ptp_ocp_settime,
1238 .adjtime = ptp_ocp_adjtime,
1239 .adjfine = ptp_ocp_null_adjfine,
1240 .adjphase = ptp_ocp_null_adjphase,
1241 .enable = ptp_ocp_enable,
1242 .verify = ptp_ocp_verify,
1249 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1253 select = ioread32(&bp->reg->select);
1254 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1256 iowrite32(0, &bp->reg->drift_ns);
1258 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1259 iowrite32(ctrl, &bp->reg->ctrl);
1261 /* restore clock selection */
1262 iowrite32(select >> 16, &bp->reg->select);
1266 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1268 unsigned long flags;
1270 spin_lock_irqsave(&bp->lock, flags);
1272 bp->utc_tai_offset = val;
1275 iowrite32(val, &bp->irig_out->adj_sec);
1277 iowrite32(val, &bp->dcf_out->adj_sec);
1279 iowrite32(val, &bp->nmea_out->adj_sec);
1281 spin_unlock_irqrestore(&bp->lock, flags);
1285 ptp_ocp_watchdog(struct timer_list *t)
1287 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1288 unsigned long flags;
1289 u32 status, utc_offset;
1291 status = ioread32(&bp->pps_to_clk->status);
1293 if (status & PPS_STATUS_SUPERV_ERR) {
1294 iowrite32(status, &bp->pps_to_clk->status);
1295 if (!bp->gnss_lost) {
1296 spin_lock_irqsave(&bp->lock, flags);
1297 __ptp_ocp_clear_drift_locked(bp);
1298 spin_unlock_irqrestore(&bp->lock, flags);
1299 bp->gnss_lost = ktime_get_real_seconds();
1302 } else if (bp->gnss_lost) {
1306 /* if GNSS provides correct data we can rely on
1307 * it to get leap second information
1310 status = ioread32(&bp->tod->utc_status);
1311 utc_offset = status & TOD_STATUS_UTC_MASK;
1312 if (status & TOD_STATUS_UTC_VALID &&
1313 utc_offset != bp->utc_tai_offset)
1314 ptp_ocp_utc_distribute(bp, utc_offset);
1317 mod_timer(&bp->watchdog, jiffies + HZ);
1321 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1327 ctrl = ioread32(&bp->reg->ctrl);
1328 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1330 iowrite32(ctrl, &bp->reg->ctrl);
1332 start = ktime_get_ns();
1334 ctrl = ioread32(&bp->reg->ctrl);
1336 end = ktime_get_ns();
1338 delay = end - start;
1339 bp->ts_window_adjust = (delay >> 5) * 3;
1343 ptp_ocp_init_clock(struct ptp_ocp *bp)
1345 struct timespec64 ts;
1349 ctrl = OCP_CTRL_ENABLE;
1350 iowrite32(ctrl, &bp->reg->ctrl);
1352 /* NO DRIFT Correction */
1353 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1354 iowrite32(0x2000, &bp->reg->servo_offset_p);
1355 iowrite32(0x1000, &bp->reg->servo_offset_i);
1356 iowrite32(0, &bp->reg->servo_drift_p);
1357 iowrite32(0, &bp->reg->servo_drift_i);
1359 /* latch servo values */
1360 ctrl |= OCP_CTRL_ADJUST_SERVO;
1361 iowrite32(ctrl, &bp->reg->ctrl);
1363 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1364 dev_err(&bp->pdev->dev, "clock not enabled\n");
1368 ptp_ocp_estimate_pci_timing(bp);
1370 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1372 ktime_get_clocktai_ts64(&ts);
1373 ptp_ocp_settime(&bp->ptp_info, &ts);
1376 /* If there is a clock supervisor, then enable the watchdog */
1377 if (bp->pps_to_clk) {
1378 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1379 mod_timer(&bp->watchdog, jiffies + HZ);
1386 ptp_ocp_tod_init(struct ptp_ocp *bp)
1390 ctrl = ioread32(&bp->tod->ctrl);
1391 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1392 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1393 iowrite32(ctrl, &bp->tod->ctrl);
1395 reg = ioread32(&bp->tod->utc_status);
1396 if (reg & TOD_STATUS_UTC_VALID)
1397 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1401 ptp_ocp_tod_proto_name(const int idx)
1403 static const char * const proto_name[] = {
1404 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1405 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1407 return proto_name[idx];
1411 ptp_ocp_tod_gnss_name(int idx)
1413 static const char * const gnss_name[] = {
1414 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1417 if (idx >= ARRAY_SIZE(gnss_name))
1418 idx = ARRAY_SIZE(gnss_name) - 1;
1419 return gnss_name[idx];
1422 struct ptp_ocp_nvmem_match_info {
1424 const void * const tag;
1428 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1430 const struct ptp_ocp_nvmem_match_info *info = data;
1433 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1436 while ((dev = dev->parent))
1437 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1438 return info->bp == dev_get_drvdata(dev);
1442 static inline struct nvmem_device *
1443 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1445 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1447 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1451 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1453 if (!IS_ERR_OR_NULL(*nvmemp))
1454 nvmem_device_put(*nvmemp);
1459 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1461 const struct ptp_ocp_eeprom_map *map;
1462 struct nvmem_device *nvmem;
1472 for (map = bp->eeprom_map; map->len; map++) {
1473 if (map->tag != tag) {
1475 ptp_ocp_nvmem_device_put(&nvmem);
1478 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1479 if (IS_ERR(nvmem)) {
1480 ret = PTR_ERR(nvmem);
1484 ret = nvmem_device_read(nvmem, map->off, map->len,
1485 BP_MAP_ENTRY_ADDR(bp, map));
1486 if (ret != map->len)
1490 bp->has_eeprom_data = true;
1493 ptp_ocp_nvmem_device_put(&nvmem);
1497 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1501 static struct device *
1502 ptp_ocp_find_flash(struct ptp_ocp *bp)
1504 struct device *dev, *last;
1507 dev = &bp->spi_flash->dev;
1509 while ((dev = device_find_any_child(dev))) {
1510 if (!strcmp("mtd", dev_bus_name(dev)))
1521 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1522 const u8 **data, size_t *size)
1524 struct ptp_ocp *bp = devlink_priv(devlink);
1525 const struct ptp_ocp_firmware_header *hdr;
1526 size_t offset, length;
1529 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1530 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1531 devlink_flash_update_status_notify(devlink,
1532 "No firmware header found, cancel firmware upgrade",
1537 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1538 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1539 devlink_flash_update_status_notify(devlink,
1540 "Firmware image compatibility check failed",
1545 offset = sizeof(*hdr);
1546 length = be32_to_cpu(hdr->image_size);
1547 if (length != (fw->size - offset)) {
1548 devlink_flash_update_status_notify(devlink,
1549 "Firmware image size check failed",
1554 crc = crc16(0xffff, &fw->data[offset], length);
1555 if (be16_to_cpu(hdr->crc) != crc) {
1556 devlink_flash_update_status_notify(devlink,
1557 "Firmware image CRC check failed",
1562 *data = &fw->data[offset];
1569 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1570 const struct firmware *fw)
1572 struct mtd_info *mtd = dev_get_drvdata(dev);
1573 struct ptp_ocp *bp = devlink_priv(devlink);
1574 size_t off, len, size, resid, wrote;
1575 struct erase_info erase;
1580 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1585 base = bp->flash_start;
1590 devlink_flash_update_status_notify(devlink, "Flashing",
1593 len = min_t(size_t, resid, blksz);
1594 erase.addr = base + off;
1597 err = mtd_erase(mtd, &erase);
1601 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1613 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1614 struct devlink_flash_update_params *params,
1615 struct netlink_ext_ack *extack)
1617 struct ptp_ocp *bp = devlink_priv(devlink);
1622 dev = ptp_ocp_find_flash(bp);
1624 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1628 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1631 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1633 msg = err ? "Flash error" : "Flash complete";
1634 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1641 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1642 struct netlink_ext_ack *extack)
1644 struct ptp_ocp *bp = devlink_priv(devlink);
1645 const char *fw_image;
1649 fw_image = bp->fw_loader ? "loader" : "fw";
1650 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1651 err = devlink_info_version_running_put(req, fw_image, buf);
1655 if (!bp->has_eeprom_data) {
1656 ptp_ocp_read_eeprom(bp);
1657 if (!bp->has_eeprom_data)
1661 sprintf(buf, "%pM", bp->serial);
1662 err = devlink_info_serial_number_put(req, buf);
1666 err = devlink_info_version_fixed_put(req,
1667 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1675 static const struct devlink_ops ptp_ocp_devlink_ops = {
1676 .flash_update = ptp_ocp_devlink_flash_update,
1677 .info_get = ptp_ocp_devlink_info_get,
1680 static void __iomem *
1681 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1683 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1685 return devm_ioremap_resource(&bp->pdev->dev, &res);
1688 static void __iomem *
1689 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1691 resource_size_t start;
1693 start = pci_resource_start(bp->pdev, 0) + r->offset;
1694 return __ptp_ocp_get_mem(bp, start, r->size);
1698 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1700 struct resource r = DEFINE_RES_IRQ(irq);
1705 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1707 struct resource r = DEFINE_RES_MEM(start, size);
1712 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1714 struct ptp_ocp_flash_info *info;
1715 struct pci_dev *pdev = bp->pdev;
1716 struct platform_device *p;
1717 struct resource res[2];
1718 resource_size_t start;
1721 start = pci_resource_start(pdev, 0) + r->offset;
1722 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1723 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1726 id = pci_dev_id(pdev) << 1;
1727 id += info->pci_offset;
1729 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1735 bp_assign_entry(bp, r, p);
1740 static struct platform_device *
1741 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1743 struct ptp_ocp_i2c_info *info;
1744 struct resource res[2];
1745 resource_size_t start;
1748 start = pci_resource_start(pdev, 0) + r->offset;
1749 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1750 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1752 return platform_device_register_resndata(&pdev->dev, info->name,
1754 info->data, info->data_size);
1758 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1760 struct pci_dev *pdev = bp->pdev;
1761 struct ptp_ocp_i2c_info *info;
1762 struct platform_device *p;
1768 id = pci_dev_id(bp->pdev);
1770 sprintf(buf, "AXI.%d", id);
1771 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1774 return PTR_ERR(clk);
1777 sprintf(buf, "%s.%d", info->name, id);
1778 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1779 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1783 bp_assign_entry(bp, r, p);
1788 /* The expectation is that this is triggered only on error. */
1790 ptp_ocp_signal_irq(int irq, void *priv)
1792 struct ptp_ocp_ext_src *ext = priv;
1793 struct signal_reg __iomem *reg = ext->mem;
1794 struct ptp_ocp *bp = ext->bp;
1798 gen = ext->info->index - 1;
1800 enable = ioread32(®->enable);
1801 status = ioread32(®->status);
1803 /* disable generator on error */
1804 if (status || !enable) {
1805 iowrite32(0, ®->intr_mask);
1806 iowrite32(0, ®->enable);
1807 bp->signal[gen].running = false;
1810 iowrite32(0, ®->intr); /* ack interrupt */
1816 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1818 struct ptp_system_timestamp sts;
1819 struct timespec64 ts;
1827 s->pulse = ktime_divns(s->period * s->duty, 100);
1829 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1833 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1835 /* roundup() does not work on 32-bit systems */
1836 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1837 s->start = ktime_add(s->start, s->phase);
1840 if (s->duty < 1 || s->duty > 99)
1843 if (s->pulse < 1 || s->pulse > s->period)
1846 if (s->start < start_ns)
1849 bp->signal[gen] = *s;
1855 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1856 struct ptp_perout_request *req)
1858 struct ptp_ocp_signal s = { };
1860 s.polarity = bp->signal[gen].polarity;
1861 s.period = ktime_set(req->period.sec, req->period.nsec);
1865 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1866 s.pulse = ktime_set(req->on.sec, req->on.nsec);
1867 s.duty = ktime_divns(s.pulse * 100, s.period);
1870 if (req->flags & PTP_PEROUT_PHASE)
1871 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1873 s.start = ktime_set(req->start.sec, req->start.nsec);
1875 return ptp_ocp_signal_set(bp, gen, &s);
1879 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1881 struct ptp_ocp_ext_src *ext = priv;
1882 struct signal_reg __iomem *reg = ext->mem;
1883 struct ptp_ocp *bp = ext->bp;
1884 struct timespec64 ts;
1887 gen = ext->info->index - 1;
1889 iowrite32(0, ®->intr_mask);
1890 iowrite32(0, ®->enable);
1891 bp->signal[gen].running = false;
1895 ts = ktime_to_timespec64(bp->signal[gen].start);
1896 iowrite32(ts.tv_sec, ®->start_sec);
1897 iowrite32(ts.tv_nsec, ®->start_ns);
1899 ts = ktime_to_timespec64(bp->signal[gen].period);
1900 iowrite32(ts.tv_sec, ®->period_sec);
1901 iowrite32(ts.tv_nsec, ®->period_ns);
1903 ts = ktime_to_timespec64(bp->signal[gen].pulse);
1904 iowrite32(ts.tv_sec, ®->pulse_sec);
1905 iowrite32(ts.tv_nsec, ®->pulse_ns);
1907 iowrite32(bp->signal[gen].polarity, ®->polarity);
1908 iowrite32(0, ®->repeat_count);
1910 iowrite32(0, ®->intr); /* clear interrupt state */
1911 iowrite32(1, ®->intr_mask); /* enable interrupt */
1912 iowrite32(3, ®->enable); /* valid & enable */
1914 bp->signal[gen].running = true;
1920 ptp_ocp_ts_irq(int irq, void *priv)
1922 struct ptp_ocp_ext_src *ext = priv;
1923 struct ts_reg __iomem *reg = ext->mem;
1924 struct ptp_clock_event ev;
1927 if (ext == ext->bp->pps) {
1928 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1929 ev.type = PTP_CLOCK_PPS;
1930 ptp_clock_event(ext->bp->ptp, &ev);
1933 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1937 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1938 sec = ioread32(®->time_sec);
1939 nsec = ioread32(®->time_ns);
1941 ev.type = PTP_CLOCK_EXTTS;
1942 ev.index = ext->info->index;
1943 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1945 ptp_clock_event(ext->bp->ptp, &ev);
1948 iowrite32(1, ®->intr); /* write 1 to ack */
1954 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1956 struct ptp_ocp_ext_src *ext = priv;
1957 struct ts_reg __iomem *reg = ext->mem;
1958 struct ptp_ocp *bp = ext->bp;
1960 if (ext == bp->pps) {
1961 u32 old_map = bp->pps_req_map;
1964 bp->pps_req_map |= req;
1966 bp->pps_req_map &= ~req;
1968 /* if no state change, just return */
1969 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1974 iowrite32(1, ®->enable);
1975 iowrite32(1, ®->intr_mask);
1976 iowrite32(1, ®->intr);
1978 iowrite32(0, ®->intr_mask);
1979 iowrite32(0, ®->enable);
1986 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1988 ext->info->enable(ext, ~0, false);
1989 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1994 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1996 struct pci_dev *pdev = bp->pdev;
1997 struct ptp_ocp_ext_src *ext;
2000 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2004 ext->mem = ptp_ocp_get_mem(bp, r);
2005 if (IS_ERR(ext->mem)) {
2006 err = PTR_ERR(ext->mem);
2011 ext->info = r->extra;
2012 ext->irq_vec = r->irq_vec;
2014 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2015 ext, "ocp%d.%s", bp->id, r->name);
2017 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2021 bp_assign_entry(bp, r, ext);
2031 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2033 struct pci_dev *pdev = bp->pdev;
2034 struct uart_8250_port uart;
2036 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2037 * the serial port device claim and release the pci resource.
2039 memset(&uart, 0, sizeof(uart));
2040 uart.port.dev = &pdev->dev;
2041 uart.port.iotype = UPIO_MEM;
2042 uart.port.regshift = 2;
2043 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2044 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2045 uart.port.uartclk = 50000000;
2046 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2047 uart.port.type = PORT_16550A;
2049 return serial8250_register_8250_port(&uart);
2053 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2055 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2056 struct ptp_ocp_serial_port port = {};
2058 port.line = ptp_ocp_serial_line(bp, r);
2063 port.baud = p->baud;
2065 bp_assign_entry(bp, r, port);
2071 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2075 mem = ptp_ocp_get_mem(bp, r);
2077 return PTR_ERR(mem);
2079 bp_assign_entry(bp, r, mem);
2085 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2090 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2091 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2092 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2096 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2100 iowrite32(0, ®->enable); /* disable */
2102 val = ioread32(®->polarity);
2103 s->polarity = val ? true : false;
2108 ptp_ocp_signal_init(struct ptp_ocp *bp)
2112 for (i = 0; i < 4; i++)
2113 if (bp->signal_out[i])
2114 _ptp_ocp_signal_init(&bp->signal[i],
2115 bp->signal_out[i]->mem);
2119 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2121 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2122 kfree(bp->attr_group);
2126 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2127 const struct ocp_attr_group *attr_tbl)
2133 for (i = 0; attr_tbl[i].cap; i++)
2134 if (attr_tbl[i].cap & bp->fw_cap)
2137 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2139 if (!bp->attr_group)
2143 for (i = 0; attr_tbl[i].cap; i++)
2144 if (attr_tbl[i].cap & bp->fw_cap)
2145 bp->attr_group[count++] = attr_tbl[i].group;
2147 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2149 bp->attr_group[0] = NULL;
2155 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2160 ctrl = ioread32(reg);
2164 ctrl |= enable ? bit : 0;
2165 iowrite32(ctrl, reg);
2170 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2172 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2173 IRIG_M_CTRL_ENABLE, enable);
2177 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2179 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2180 IRIG_S_CTRL_ENABLE, enable);
2184 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2186 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2187 DCF_M_CTRL_ENABLE, enable);
2191 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2193 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2194 DCF_S_CTRL_ENABLE, enable);
2198 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2200 ptp_ocp_irig_out(bp, val & 0x00100010);
2201 ptp_ocp_dcf_out(bp, val & 0x00200020);
2205 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2207 ptp_ocp_irig_in(bp, val & 0x00100010);
2208 ptp_ocp_dcf_in(bp, val & 0x00200020);
2212 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2217 if (bp->sma[sma_nr - 1].fixed_fcn)
2218 return (sma_nr - 1) & 1;
2220 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2221 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2223 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2224 shift = sma_nr & 1 ? 0 : 16;
2226 return (ioread32(gpio) >> shift) & 0xffff;
2230 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2232 u32 reg, mask, shift;
2233 unsigned long flags;
2236 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2237 shift = sma_nr & 1 ? 0 : 16;
2239 mask = 0xffff << (16 - shift);
2241 spin_lock_irqsave(&bp->lock, flags);
2243 reg = ioread32(gpio);
2244 reg = (reg & mask) | (val << shift);
2246 __handle_signal_outputs(bp, reg);
2248 iowrite32(reg, gpio);
2250 spin_unlock_irqrestore(&bp->lock, flags);
2256 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2258 u32 reg, mask, shift;
2259 unsigned long flags;
2262 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2263 shift = sma_nr & 1 ? 0 : 16;
2265 mask = 0xffff << (16 - shift);
2267 spin_lock_irqsave(&bp->lock, flags);
2269 reg = ioread32(gpio);
2270 reg = (reg & mask) | (val << shift);
2272 __handle_signal_inputs(bp, reg);
2274 iowrite32(reg, gpio);
2276 spin_unlock_irqrestore(&bp->lock, flags);
2282 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2288 bp->sma[0].mode = SMA_MODE_IN;
2289 bp->sma[1].mode = SMA_MODE_IN;
2290 bp->sma[2].mode = SMA_MODE_OUT;
2291 bp->sma[3].mode = SMA_MODE_OUT;
2292 for (i = 0; i < 4; i++)
2293 bp->sma[i].default_fcn = i & 1;
2295 /* If no SMA1 map, the pin functions and directions are fixed. */
2296 if (!bp->sma_map1) {
2297 for (i = 0; i < 4; i++) {
2298 bp->sma[i].fixed_fcn = true;
2299 bp->sma[i].fixed_dir = true;
2304 /* If SMA2 GPIO output map is all 1, it is not present.
2305 * This indicates the firmware has fixed direction SMA pins.
2307 reg = ioread32(&bp->sma_map2->gpio2);
2308 if (reg == 0xffffffff) {
2309 for (i = 0; i < 4; i++)
2310 bp->sma[i].fixed_dir = true;
2312 reg = ioread32(&bp->sma_map1->gpio1);
2313 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2314 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2316 reg = ioread32(&bp->sma_map1->gpio2);
2317 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2318 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2322 static const struct ocp_sma_op ocp_fb_sma_op = {
2323 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2324 .init = ptp_ocp_sma_fb_init,
2325 .get = ptp_ocp_sma_fb_get,
2326 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2327 .set_output = ptp_ocp_sma_fb_set_output,
2331 ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2333 struct ptp_pin_desc *config;
2336 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2340 for (i = 0; i < 4; i++) {
2341 sprintf(config[i].name, "sma%d", i + 1);
2342 config[i].index = i;
2345 bp->ptp_info.n_pins = 4;
2346 bp->ptp_info.pin_config = config;
2352 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2354 u64 cap = OCP_CAP_BASIC;
2357 version = ioread32(&bp->image->version);
2359 /* if lower 16 bits are empty, this is the fw loader. */
2360 if ((version & 0xffff) == 0) {
2361 version = version >> 16;
2362 bp->fw_loader = true;
2365 bp->fw_tag = version >> 15;
2366 bp->fw_version = version & 0x7fff;
2371 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2375 cap |= OCP_CAP_SIGNAL;
2377 cap |= OCP_CAP_FREQ;
2383 /* FB specific board initializers; last "resource" registered. */
2385 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2389 bp->flash_start = 1024 * 4096;
2390 bp->eeprom_map = fb_eeprom_map;
2391 bp->fw_version = ioread32(&bp->image->version);
2392 bp->sma_op = &ocp_fb_sma_op;
2394 ptp_ocp_fb_set_version(bp);
2396 ptp_ocp_tod_init(bp);
2397 ptp_ocp_nmea_out_init(bp);
2398 ptp_ocp_sma_init(bp);
2399 ptp_ocp_signal_init(bp);
2401 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2405 err = ptp_ocp_fb_set_pins(bp);
2409 return ptp_ocp_init_clock(bp);
2413 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2415 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2418 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2419 r->irq_vec, r->name);
2424 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2426 struct ocp_resource *r, *table;
2429 table = (struct ocp_resource *)driver_data;
2430 for (r = table; r->setup; r++) {
2431 if (!ptp_ocp_allow_irq(bp, r))
2433 err = r->setup(bp, r);
2435 dev_err(&bp->pdev->dev,
2436 "Could not register %s: err %d\n",
2445 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2451 bp->sma[0].mode = SMA_MODE_IN;
2452 bp->sma[1].mode = SMA_MODE_IN;
2453 bp->sma[2].mode = SMA_MODE_OUT;
2454 bp->sma[3].mode = SMA_MODE_OUT;
2456 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2457 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2458 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2459 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2461 /* If no SMA map, the pin functions and directions are fixed. */
2463 for (i = 0; i < 4; i++) {
2464 bp->sma[i].fixed_fcn = true;
2465 bp->sma[i].fixed_dir = true;
2470 for (i = 0; i < 4; i++) {
2471 reg = ioread32(&bp->art_sma->map[i].gpio);
2473 switch (reg & 0xff) {
2475 bp->sma[i].fixed_fcn = true;
2476 bp->sma[i].fixed_dir = true;
2480 bp->sma[i].mode = SMA_MODE_IN;
2483 bp->sma[i].mode = SMA_MODE_OUT;
2490 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2492 if (bp->sma[sma_nr - 1].fixed_fcn)
2493 return bp->sma[sma_nr - 1].default_fcn;
2495 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2498 /* note: store 0 is considered invalid. */
2500 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2502 unsigned long flags;
2507 val &= SMA_SELECT_MASK;
2508 if (hweight32(val) > 1)
2511 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2513 spin_lock_irqsave(&bp->lock, flags);
2514 reg = ioread32(gpio);
2515 if (((reg >> 16) & val) == 0) {
2518 reg = (reg & 0xff00) | (val & 0xff);
2519 iowrite32(reg, gpio);
2521 spin_unlock_irqrestore(&bp->lock, flags);
2526 static const struct ocp_sma_op ocp_art_sma_op = {
2527 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2528 .init = ptp_ocp_art_sma_init,
2529 .get = ptp_ocp_art_sma_get,
2530 .set_inputs = ptp_ocp_art_sma_set,
2531 .set_output = ptp_ocp_art_sma_set,
2534 /* ART specific board initializers; last "resource" registered. */
2536 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2540 bp->flash_start = 0x1000000;
2541 bp->eeprom_map = art_eeprom_map;
2542 bp->fw_cap = OCP_CAP_BASIC;
2543 bp->fw_version = ioread32(&bp->reg->version);
2545 bp->sma_op = &ocp_art_sma_op;
2547 /* Enable MAC serial port during initialisation */
2548 iowrite32(1, &bp->board_config->mro50_serial_activate);
2550 ptp_ocp_sma_init(bp);
2552 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2556 return ptp_ocp_init_clock(bp);
2560 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2566 count = sysfs_emit(buf, "OUT: ");
2567 name = ptp_ocp_select_name_from_val(tbl, val);
2569 name = ptp_ocp_select_name_from_val(tbl, def_val);
2570 count += sysfs_emit_at(buf, count, "%s\n", name);
2575 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2582 count = sysfs_emit(buf, "IN: ");
2583 for (i = 0; tbl[i].name; i++) {
2584 if (val & tbl[i].value) {
2586 count += sysfs_emit_at(buf, count, "%s ", name);
2589 if (!val && def_val >= 0) {
2590 name = ptp_ocp_select_name_from_val(tbl, def_val);
2591 count += sysfs_emit_at(buf, count, "%s ", name);
2595 count += sysfs_emit_at(buf, count, "\n");
2600 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2601 enum ptp_ocp_sma_mode *mode)
2603 int idx, count, dir;
2607 argv = argv_split(GFP_KERNEL, buf, &count);
2616 dir = *mode == SMA_MODE_IN ? 0 : 1;
2617 if (!strcasecmp("IN:", argv[0])) {
2621 if (!strcasecmp("OUT:", argv[0])) {
2625 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2628 for (; idx < count; idx++)
2629 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2639 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2640 int default_in_val, int default_out_val)
2642 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2643 const struct ocp_selector * const *tbl;
2646 tbl = bp->sma_op->tbl;
2647 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2649 if (sma->mode == SMA_MODE_IN) {
2652 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2655 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2659 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2661 struct ptp_ocp *bp = dev_get_drvdata(dev);
2663 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2667 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2669 struct ptp_ocp *bp = dev_get_drvdata(dev);
2671 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2675 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2677 struct ptp_ocp *bp = dev_get_drvdata(dev);
2679 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2683 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2685 struct ptp_ocp *bp = dev_get_drvdata(dev);
2687 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2691 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2693 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2694 enum ptp_ocp_sma_mode mode;
2698 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2702 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2705 if (sma->fixed_fcn) {
2706 if (val != sma->default_fcn)
2711 sma->disabled = !!(val & SMA_DISABLE);
2713 if (mode != sma->mode) {
2714 if (mode == SMA_MODE_IN)
2715 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2717 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2721 if (!sma->fixed_dir)
2722 val |= SMA_ENABLE; /* add enable bit */
2727 if (mode == SMA_MODE_IN)
2728 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2730 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2736 sma1_store(struct device *dev, struct device_attribute *attr,
2737 const char *buf, size_t count)
2739 struct ptp_ocp *bp = dev_get_drvdata(dev);
2742 err = ptp_ocp_sma_store(bp, buf, 1);
2743 return err ? err : count;
2747 sma2_store(struct device *dev, struct device_attribute *attr,
2748 const char *buf, size_t count)
2750 struct ptp_ocp *bp = dev_get_drvdata(dev);
2753 err = ptp_ocp_sma_store(bp, buf, 2);
2754 return err ? err : count;
2758 sma3_store(struct device *dev, struct device_attribute *attr,
2759 const char *buf, size_t count)
2761 struct ptp_ocp *bp = dev_get_drvdata(dev);
2764 err = ptp_ocp_sma_store(bp, buf, 3);
2765 return err ? err : count;
2769 sma4_store(struct device *dev, struct device_attribute *attr,
2770 const char *buf, size_t count)
2772 struct ptp_ocp *bp = dev_get_drvdata(dev);
2775 err = ptp_ocp_sma_store(bp, buf, 4);
2776 return err ? err : count;
2778 static DEVICE_ATTR_RW(sma1);
2779 static DEVICE_ATTR_RW(sma2);
2780 static DEVICE_ATTR_RW(sma3);
2781 static DEVICE_ATTR_RW(sma4);
2784 available_sma_inputs_show(struct device *dev,
2785 struct device_attribute *attr, char *buf)
2787 struct ptp_ocp *bp = dev_get_drvdata(dev);
2789 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2791 static DEVICE_ATTR_RO(available_sma_inputs);
2794 available_sma_outputs_show(struct device *dev,
2795 struct device_attribute *attr, char *buf)
2797 struct ptp_ocp *bp = dev_get_drvdata(dev);
2799 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2801 static DEVICE_ATTR_RO(available_sma_outputs);
2803 #define EXT_ATTR_RO(_group, _name, _val) \
2804 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2805 { __ATTR_RO(_name), (void *)_val }
2806 #define EXT_ATTR_RW(_group, _name, _val) \
2807 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2808 { __ATTR_RW(_name), (void *)_val }
2809 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2811 /* period [duty [phase [polarity]]] */
2813 signal_store(struct device *dev, struct device_attribute *attr,
2814 const char *buf, size_t count)
2816 struct dev_ext_attribute *ea = to_ext_attr(attr);
2817 struct ptp_ocp *bp = dev_get_drvdata(dev);
2818 struct ptp_ocp_signal s = { };
2819 int gen = (uintptr_t)ea->var;
2823 argv = argv_split(GFP_KERNEL, buf, &argc);
2828 s.duty = bp->signal[gen].duty;
2829 s.phase = bp->signal[gen].phase;
2830 s.period = bp->signal[gen].period;
2831 s.polarity = bp->signal[gen].polarity;
2836 err = kstrtobool(argv[argc], &s.polarity);
2842 err = kstrtou64(argv[argc], 0, &s.phase);
2848 err = kstrtoint(argv[argc], 0, &s.duty);
2854 err = kstrtou64(argv[argc], 0, &s.period);
2862 err = ptp_ocp_signal_set(bp, gen, &s);
2866 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2870 return err ? err : count;
2874 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2876 struct dev_ext_attribute *ea = to_ext_attr(attr);
2877 struct ptp_ocp *bp = dev_get_drvdata(dev);
2878 struct ptp_ocp_signal *signal;
2879 struct timespec64 ts;
2883 i = (uintptr_t)ea->var;
2884 signal = &bp->signal[i];
2886 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2887 signal->duty, signal->phase, signal->polarity);
2889 ts = ktime_to_timespec64(signal->start);
2890 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2894 static EXT_ATTR_RW(signal, signal, 0);
2895 static EXT_ATTR_RW(signal, signal, 1);
2896 static EXT_ATTR_RW(signal, signal, 2);
2897 static EXT_ATTR_RW(signal, signal, 3);
2900 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2902 struct dev_ext_attribute *ea = to_ext_attr(attr);
2903 struct ptp_ocp *bp = dev_get_drvdata(dev);
2904 int i = (uintptr_t)ea->var;
2906 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2908 static EXT_ATTR_RO(signal, duty, 0);
2909 static EXT_ATTR_RO(signal, duty, 1);
2910 static EXT_ATTR_RO(signal, duty, 2);
2911 static EXT_ATTR_RO(signal, duty, 3);
2914 period_show(struct device *dev, struct device_attribute *attr, char *buf)
2916 struct dev_ext_attribute *ea = to_ext_attr(attr);
2917 struct ptp_ocp *bp = dev_get_drvdata(dev);
2918 int i = (uintptr_t)ea->var;
2920 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2922 static EXT_ATTR_RO(signal, period, 0);
2923 static EXT_ATTR_RO(signal, period, 1);
2924 static EXT_ATTR_RO(signal, period, 2);
2925 static EXT_ATTR_RO(signal, period, 3);
2928 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2930 struct dev_ext_attribute *ea = to_ext_attr(attr);
2931 struct ptp_ocp *bp = dev_get_drvdata(dev);
2932 int i = (uintptr_t)ea->var;
2934 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2936 static EXT_ATTR_RO(signal, phase, 0);
2937 static EXT_ATTR_RO(signal, phase, 1);
2938 static EXT_ATTR_RO(signal, phase, 2);
2939 static EXT_ATTR_RO(signal, phase, 3);
2942 polarity_show(struct device *dev, struct device_attribute *attr,
2945 struct dev_ext_attribute *ea = to_ext_attr(attr);
2946 struct ptp_ocp *bp = dev_get_drvdata(dev);
2947 int i = (uintptr_t)ea->var;
2949 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2951 static EXT_ATTR_RO(signal, polarity, 0);
2952 static EXT_ATTR_RO(signal, polarity, 1);
2953 static EXT_ATTR_RO(signal, polarity, 2);
2954 static EXT_ATTR_RO(signal, polarity, 3);
2957 running_show(struct device *dev, struct device_attribute *attr, char *buf)
2959 struct dev_ext_attribute *ea = to_ext_attr(attr);
2960 struct ptp_ocp *bp = dev_get_drvdata(dev);
2961 int i = (uintptr_t)ea->var;
2963 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2965 static EXT_ATTR_RO(signal, running, 0);
2966 static EXT_ATTR_RO(signal, running, 1);
2967 static EXT_ATTR_RO(signal, running, 2);
2968 static EXT_ATTR_RO(signal, running, 3);
2971 start_show(struct device *dev, struct device_attribute *attr, char *buf)
2973 struct dev_ext_attribute *ea = to_ext_attr(attr);
2974 struct ptp_ocp *bp = dev_get_drvdata(dev);
2975 int i = (uintptr_t)ea->var;
2976 struct timespec64 ts;
2978 ts = ktime_to_timespec64(bp->signal[i].start);
2979 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2981 static EXT_ATTR_RO(signal, start, 0);
2982 static EXT_ATTR_RO(signal, start, 1);
2983 static EXT_ATTR_RO(signal, start, 2);
2984 static EXT_ATTR_RO(signal, start, 3);
2987 seconds_store(struct device *dev, struct device_attribute *attr,
2988 const char *buf, size_t count)
2990 struct dev_ext_attribute *ea = to_ext_attr(attr);
2991 struct ptp_ocp *bp = dev_get_drvdata(dev);
2992 int idx = (uintptr_t)ea->var;
2996 err = kstrtou32(buf, 0, &val);
3003 val = (val << 8) | 0x1;
3005 iowrite32(val, &bp->freq_in[idx]->ctrl);
3011 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3013 struct dev_ext_attribute *ea = to_ext_attr(attr);
3014 struct ptp_ocp *bp = dev_get_drvdata(dev);
3015 int idx = (uintptr_t)ea->var;
3018 val = ioread32(&bp->freq_in[idx]->ctrl);
3020 val = (val >> 8) & 0xff;
3024 return sysfs_emit(buf, "%u\n", val);
3026 static EXT_ATTR_RW(freq, seconds, 0);
3027 static EXT_ATTR_RW(freq, seconds, 1);
3028 static EXT_ATTR_RW(freq, seconds, 2);
3029 static EXT_ATTR_RW(freq, seconds, 3);
3032 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3034 struct dev_ext_attribute *ea = to_ext_attr(attr);
3035 struct ptp_ocp *bp = dev_get_drvdata(dev);
3036 int idx = (uintptr_t)ea->var;
3039 val = ioread32(&bp->freq_in[idx]->status);
3040 if (val & FREQ_STATUS_ERROR)
3041 return sysfs_emit(buf, "error\n");
3042 if (val & FREQ_STATUS_OVERRUN)
3043 return sysfs_emit(buf, "overrun\n");
3044 if (val & FREQ_STATUS_VALID)
3045 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3048 static EXT_ATTR_RO(freq, frequency, 0);
3049 static EXT_ATTR_RO(freq, frequency, 1);
3050 static EXT_ATTR_RO(freq, frequency, 2);
3051 static EXT_ATTR_RO(freq, frequency, 3);
3054 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3056 struct ptp_ocp *bp = dev_get_drvdata(dev);
3058 if (!bp->has_eeprom_data)
3059 ptp_ocp_read_eeprom(bp);
3061 return sysfs_emit(buf, "%pM\n", bp->serial);
3063 static DEVICE_ATTR_RO(serialnum);
3066 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3068 struct ptp_ocp *bp = dev_get_drvdata(dev);
3072 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3074 ret = sysfs_emit(buf, "SYNC\n");
3078 static DEVICE_ATTR_RO(gnss_sync);
3081 utc_tai_offset_show(struct device *dev,
3082 struct device_attribute *attr, char *buf)
3084 struct ptp_ocp *bp = dev_get_drvdata(dev);
3086 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3090 utc_tai_offset_store(struct device *dev,
3091 struct device_attribute *attr,
3092 const char *buf, size_t count)
3094 struct ptp_ocp *bp = dev_get_drvdata(dev);
3098 err = kstrtou32(buf, 0, &val);
3102 ptp_ocp_utc_distribute(bp, val);
3106 static DEVICE_ATTR_RW(utc_tai_offset);
3109 ts_window_adjust_show(struct device *dev,
3110 struct device_attribute *attr, char *buf)
3112 struct ptp_ocp *bp = dev_get_drvdata(dev);
3114 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3118 ts_window_adjust_store(struct device *dev,
3119 struct device_attribute *attr,
3120 const char *buf, size_t count)
3122 struct ptp_ocp *bp = dev_get_drvdata(dev);
3126 err = kstrtou32(buf, 0, &val);
3130 bp->ts_window_adjust = val;
3134 static DEVICE_ATTR_RW(ts_window_adjust);
3137 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3139 struct ptp_ocp *bp = dev_get_drvdata(dev);
3142 val = ioread32(&bp->irig_out->ctrl);
3143 val = (val >> 16) & 0x07;
3144 return sysfs_emit(buf, "%d\n", val);
3148 irig_b_mode_store(struct device *dev,
3149 struct device_attribute *attr,
3150 const char *buf, size_t count)
3152 struct ptp_ocp *bp = dev_get_drvdata(dev);
3153 unsigned long flags;
3158 err = kstrtou8(buf, 0, &val);
3164 reg = ((val & 0x7) << 16);
3166 spin_lock_irqsave(&bp->lock, flags);
3167 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3168 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3169 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3170 spin_unlock_irqrestore(&bp->lock, flags);
3174 static DEVICE_ATTR_RW(irig_b_mode);
3177 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3179 struct ptp_ocp *bp = dev_get_drvdata(dev);
3183 select = ioread32(&bp->reg->select);
3184 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3186 return sysfs_emit(buf, "%s\n", p);
3190 clock_source_store(struct device *dev, struct device_attribute *attr,
3191 const char *buf, size_t count)
3193 struct ptp_ocp *bp = dev_get_drvdata(dev);
3194 unsigned long flags;
3197 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3201 spin_lock_irqsave(&bp->lock, flags);
3202 iowrite32(val, &bp->reg->select);
3203 spin_unlock_irqrestore(&bp->lock, flags);
3207 static DEVICE_ATTR_RW(clock_source);
3210 available_clock_sources_show(struct device *dev,
3211 struct device_attribute *attr, char *buf)
3213 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3215 static DEVICE_ATTR_RO(available_clock_sources);
3218 clock_status_drift_show(struct device *dev,
3219 struct device_attribute *attr, char *buf)
3221 struct ptp_ocp *bp = dev_get_drvdata(dev);
3225 val = ioread32(&bp->reg->status_drift);
3226 res = (val & ~INT_MAX) ? -1 : 1;
3227 res *= (val & INT_MAX);
3228 return sysfs_emit(buf, "%d\n", res);
3230 static DEVICE_ATTR_RO(clock_status_drift);
3233 clock_status_offset_show(struct device *dev,
3234 struct device_attribute *attr, char *buf)
3236 struct ptp_ocp *bp = dev_get_drvdata(dev);
3240 val = ioread32(&bp->reg->status_offset);
3241 res = (val & ~INT_MAX) ? -1 : 1;
3242 res *= (val & INT_MAX);
3243 return sysfs_emit(buf, "%d\n", res);
3245 static DEVICE_ATTR_RO(clock_status_offset);
3248 tod_correction_show(struct device *dev,
3249 struct device_attribute *attr, char *buf)
3251 struct ptp_ocp *bp = dev_get_drvdata(dev);
3255 val = ioread32(&bp->tod->adj_sec);
3256 res = (val & ~INT_MAX) ? -1 : 1;
3257 res *= (val & INT_MAX);
3258 return sysfs_emit(buf, "%d\n", res);
3262 tod_correction_store(struct device *dev, struct device_attribute *attr,
3263 const char *buf, size_t count)
3265 struct ptp_ocp *bp = dev_get_drvdata(dev);
3266 unsigned long flags;
3270 err = kstrtos32(buf, 0, &res);
3279 spin_lock_irqsave(&bp->lock, flags);
3280 iowrite32(val, &bp->tod->adj_sec);
3281 spin_unlock_irqrestore(&bp->lock, flags);
3285 static DEVICE_ATTR_RW(tod_correction);
3287 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3288 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3289 &dev_attr_signal##_nr##_signal.attr.attr, \
3290 &dev_attr_signal##_nr##_duty.attr.attr, \
3291 &dev_attr_signal##_nr##_phase.attr.attr, \
3292 &dev_attr_signal##_nr##_period.attr.attr, \
3293 &dev_attr_signal##_nr##_polarity.attr.attr, \
3294 &dev_attr_signal##_nr##_running.attr.attr, \
3295 &dev_attr_signal##_nr##_start.attr.attr, \
3299 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3300 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3301 static const struct attribute_group \
3302 fb_timecard_signal##_nr##_group = { \
3304 .attrs = fb_timecard_signal##_nr##_attrs, \
3307 DEVICE_SIGNAL_GROUP(gen1, 0);
3308 DEVICE_SIGNAL_GROUP(gen2, 1);
3309 DEVICE_SIGNAL_GROUP(gen3, 2);
3310 DEVICE_SIGNAL_GROUP(gen4, 3);
3312 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3313 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3314 &dev_attr_freq##_nr##_seconds.attr.attr, \
3315 &dev_attr_freq##_nr##_frequency.attr.attr, \
3319 #define DEVICE_FREQ_GROUP(_name, _nr) \
3320 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3321 static const struct attribute_group \
3322 fb_timecard_freq##_nr##_group = { \
3324 .attrs = fb_timecard_freq##_nr##_attrs, \
3327 DEVICE_FREQ_GROUP(freq1, 0);
3328 DEVICE_FREQ_GROUP(freq2, 1);
3329 DEVICE_FREQ_GROUP(freq3, 2);
3330 DEVICE_FREQ_GROUP(freq4, 3);
3333 disciplining_config_read(struct file *filp, struct kobject *kobj,
3334 struct bin_attribute *bin_attr, char *buf,
3335 loff_t off, size_t count)
3337 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3338 size_t size = OCP_ART_CONFIG_SIZE;
3339 struct nvmem_device *nvmem;
3342 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3344 return PTR_ERR(nvmem);
3351 if (off + count > size)
3354 // the configuration is in the very beginning of the EEPROM
3355 err = nvmem_device_read(nvmem, off, count, buf);
3362 ptp_ocp_nvmem_device_put(&nvmem);
3368 disciplining_config_write(struct file *filp, struct kobject *kobj,
3369 struct bin_attribute *bin_attr, char *buf,
3370 loff_t off, size_t count)
3372 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3373 struct nvmem_device *nvmem;
3376 /* Allow write of the whole area only */
3377 if (off || count != OCP_ART_CONFIG_SIZE)
3380 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3382 return PTR_ERR(nvmem);
3384 err = nvmem_device_write(nvmem, 0x00, count, buf);
3388 ptp_ocp_nvmem_device_put(&nvmem);
3392 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3395 temperature_table_read(struct file *filp, struct kobject *kobj,
3396 struct bin_attribute *bin_attr, char *buf,
3397 loff_t off, size_t count)
3399 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3400 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3401 struct nvmem_device *nvmem;
3404 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3406 return PTR_ERR(nvmem);
3413 if (off + count > size)
3416 // the configuration is in the very beginning of the EEPROM
3417 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3424 ptp_ocp_nvmem_device_put(&nvmem);
3430 temperature_table_write(struct file *filp, struct kobject *kobj,
3431 struct bin_attribute *bin_attr, char *buf,
3432 loff_t off, size_t count)
3434 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3435 struct nvmem_device *nvmem;
3438 /* Allow write of the whole area only */
3439 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3442 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3444 return PTR_ERR(nvmem);
3446 err = nvmem_device_write(nvmem, 0x90, count, buf);
3450 ptp_ocp_nvmem_device_put(&nvmem);
3454 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3456 static struct attribute *fb_timecard_attrs[] = {
3457 &dev_attr_serialnum.attr,
3458 &dev_attr_gnss_sync.attr,
3459 &dev_attr_clock_source.attr,
3460 &dev_attr_available_clock_sources.attr,
3461 &dev_attr_sma1.attr,
3462 &dev_attr_sma2.attr,
3463 &dev_attr_sma3.attr,
3464 &dev_attr_sma4.attr,
3465 &dev_attr_available_sma_inputs.attr,
3466 &dev_attr_available_sma_outputs.attr,
3467 &dev_attr_clock_status_drift.attr,
3468 &dev_attr_clock_status_offset.attr,
3469 &dev_attr_irig_b_mode.attr,
3470 &dev_attr_utc_tai_offset.attr,
3471 &dev_attr_ts_window_adjust.attr,
3472 &dev_attr_tod_correction.attr,
3476 static const struct attribute_group fb_timecard_group = {
3477 .attrs = fb_timecard_attrs,
3480 static const struct ocp_attr_group fb_timecard_groups[] = {
3481 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3482 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3483 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3484 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3485 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3486 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3487 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3488 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3489 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3493 static struct attribute *art_timecard_attrs[] = {
3494 &dev_attr_serialnum.attr,
3495 &dev_attr_clock_source.attr,
3496 &dev_attr_available_clock_sources.attr,
3497 &dev_attr_utc_tai_offset.attr,
3498 &dev_attr_ts_window_adjust.attr,
3499 &dev_attr_sma1.attr,
3500 &dev_attr_sma2.attr,
3501 &dev_attr_sma3.attr,
3502 &dev_attr_sma4.attr,
3503 &dev_attr_available_sma_inputs.attr,
3504 &dev_attr_available_sma_outputs.attr,
3508 static struct bin_attribute *bin_art_timecard_attrs[] = {
3509 &bin_attr_disciplining_config,
3510 &bin_attr_temperature_table,
3514 static const struct attribute_group art_timecard_group = {
3515 .attrs = art_timecard_attrs,
3516 .bin_attrs = bin_art_timecard_attrs,
3519 static const struct ocp_attr_group art_timecard_groups[] = {
3520 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3525 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3530 for (i = 0; i < 4; i++) {
3531 if (bp->sma[i].mode != SMA_MODE_IN)
3533 if (map[i][0] & (1 << bit)) {
3534 sprintf(buf, "sma%d", i + 1);
3544 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3549 strcpy(ans, "----");
3550 for (i = 0; i < 4; i++) {
3551 if (bp->sma[i].mode != SMA_MODE_OUT)
3553 if (map[i][1] & (1 << bit))
3554 ans += sprintf(ans, "sma%d ", i + 1);
3559 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3561 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3562 struct ptp_ocp_signal *signal = &bp->signal[nr];
3570 on = signal->running;
3571 sprintf(label, "GEN%d", nr + 1);
3572 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3573 label, on ? " ON" : "OFF",
3574 signal->period, signal->duty, signal->phase,
3577 val = ioread32(®->enable);
3578 seq_printf(s, " [%x", val);
3579 val = ioread32(®->status);
3580 seq_printf(s, " %x]", val);
3582 seq_printf(s, " start:%llu\n", signal->start);
3586 _frequency_summary_show(struct seq_file *s, int nr,
3587 struct frequency_reg __iomem *reg)
3596 sprintf(label, "FREQ%d", nr + 1);
3597 val = ioread32(®->ctrl);
3599 val = (val >> 8) & 0xff;
3600 seq_printf(s, "%7s: %s, sec:%u",
3605 val = ioread32(®->status);
3606 if (val & FREQ_STATUS_ERROR)
3607 seq_printf(s, ", error");
3608 if (val & FREQ_STATUS_OVERRUN)
3609 seq_printf(s, ", overrun");
3610 if (val & FREQ_STATUS_VALID)
3611 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3612 seq_printf(s, " reg:%x\n", val);
3616 ptp_ocp_summary_show(struct seq_file *s, void *data)
3618 struct device *dev = s->private;
3619 struct ptp_system_timestamp sts;
3620 struct ts_reg __iomem *ts_reg;
3621 char *buf, *src, *mac_src;
3622 struct timespec64 ts;
3629 buf = (char *)__get_free_page(GFP_KERNEL);
3633 bp = dev_get_drvdata(dev);
3635 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3636 if (bp->gnss_port.line != -1)
3637 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3638 bp->gnss_port.line);
3639 if (bp->gnss2_port.line != -1)
3640 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3641 bp->gnss2_port.line);
3642 if (bp->mac_port.line != -1)
3643 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3644 if (bp->nmea_port.line != -1)
3645 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3647 memset(sma_val, 0xff, sizeof(sma_val));
3651 reg = ioread32(&bp->sma_map1->gpio1);
3652 sma_val[0][0] = reg & 0xffff;
3653 sma_val[1][0] = reg >> 16;
3655 reg = ioread32(&bp->sma_map1->gpio2);
3656 sma_val[2][1] = reg & 0xffff;
3657 sma_val[3][1] = reg >> 16;
3659 reg = ioread32(&bp->sma_map2->gpio1);
3660 sma_val[2][0] = reg & 0xffff;
3661 sma_val[3][0] = reg >> 16;
3663 reg = ioread32(&bp->sma_map2->gpio2);
3664 sma_val[0][1] = reg & 0xffff;
3665 sma_val[1][1] = reg >> 16;
3668 sma1_show(dev, NULL, buf);
3669 seq_printf(s, " sma1: %04x,%04x %s",
3670 sma_val[0][0], sma_val[0][1], buf);
3672 sma2_show(dev, NULL, buf);
3673 seq_printf(s, " sma2: %04x,%04x %s",
3674 sma_val[1][0], sma_val[1][1], buf);
3676 sma3_show(dev, NULL, buf);
3677 seq_printf(s, " sma3: %04x,%04x %s",
3678 sma_val[2][0], sma_val[2][1], buf);
3680 sma4_show(dev, NULL, buf);
3681 seq_printf(s, " sma4: %04x,%04x %s",
3682 sma_val[3][0], sma_val[3][1], buf);
3685 ts_reg = bp->ts0->mem;
3686 on = ioread32(&ts_reg->enable);
3688 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3689 on ? " ON" : "OFF", src);
3693 ts_reg = bp->ts1->mem;
3694 on = ioread32(&ts_reg->enable);
3695 gpio_input_map(buf, bp, sma_val, 2, NULL);
3696 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3697 on ? " ON" : "OFF", buf);
3701 ts_reg = bp->ts2->mem;
3702 on = ioread32(&ts_reg->enable);
3703 gpio_input_map(buf, bp, sma_val, 3, NULL);
3704 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3705 on ? " ON" : "OFF", buf);
3709 ts_reg = bp->ts3->mem;
3710 on = ioread32(&ts_reg->enable);
3711 gpio_input_map(buf, bp, sma_val, 6, NULL);
3712 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3713 on ? " ON" : "OFF", buf);
3717 ts_reg = bp->ts4->mem;
3718 on = ioread32(&ts_reg->enable);
3719 gpio_input_map(buf, bp, sma_val, 7, NULL);
3720 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3721 on ? " ON" : "OFF", buf);
3725 ts_reg = bp->pps->mem;
3727 on = ioread32(&ts_reg->enable);
3728 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3729 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3730 on && map ? " ON" : "OFF", src);
3732 map = !!(bp->pps_req_map & OCP_REQ_PPS);
3733 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3734 on && map ? " ON" : "OFF", src);
3737 if (bp->fw_cap & OCP_CAP_SIGNAL)
3738 for (i = 0; i < 4; i++)
3739 _signal_summary_show(s, bp, i);
3741 if (bp->fw_cap & OCP_CAP_FREQ)
3742 for (i = 0; i < 4; i++)
3743 _frequency_summary_show(s, i, bp->freq_in[i]);
3746 ctrl = ioread32(&bp->irig_out->ctrl);
3747 on = ctrl & IRIG_M_CTRL_ENABLE;
3748 val = ioread32(&bp->irig_out->status);
3749 gpio_output_map(buf, bp, sma_val, 4);
3750 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3751 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3755 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3756 val = ioread32(&bp->irig_in->status);
3757 gpio_input_map(buf, bp, sma_val, 4, NULL);
3758 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3759 on ? " ON" : "OFF", val, buf);
3763 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3764 val = ioread32(&bp->dcf_out->status);
3765 gpio_output_map(buf, bp, sma_val, 5);
3766 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3767 on ? " ON" : "OFF", val, buf);
3771 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3772 val = ioread32(&bp->dcf_in->status);
3773 gpio_input_map(buf, bp, sma_val, 5, NULL);
3774 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3775 on ? " ON" : "OFF", val, buf);
3779 on = ioread32(&bp->nmea_out->ctrl) & 1;
3780 val = ioread32(&bp->nmea_out->status);
3781 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3782 on ? " ON" : "OFF", val);
3785 /* compute src for PPS1, used below. */
3786 if (bp->pps_select) {
3787 val = ioread32(&bp->pps_select->gpio1);
3791 gpio_input_map(src, bp, sma_val, 0, NULL);
3793 } else if (val & 0x02) {
3795 } else if (val & 0x04) {
3805 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3807 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3808 seq_printf(s, "MAC PPS2 src: %s\n", buf);
3810 /* assumes automatic switchover/selection */
3811 val = ioread32(&bp->reg->select);
3812 switch (val >> 16) {
3814 sprintf(buf, "----");
3817 sprintf(buf, "IRIG");
3820 sprintf(buf, "%s via PPS1", src);
3823 sprintf(buf, "DCF");
3826 strcpy(buf, "unknown");
3829 val = ioread32(&bp->reg->status);
3830 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3831 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3833 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3834 struct timespec64 sys_ts;
3835 s64 pre_ns, post_ns, ns;
3837 pre_ns = timespec64_to_ns(&sts.pre_ts);
3838 post_ns = timespec64_to_ns(&sts.post_ts);
3839 ns = (pre_ns + post_ns) / 2;
3840 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3841 sys_ts = ns_to_timespec64(ns);
3843 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3844 ts.tv_sec, ts.tv_nsec, &ts);
3845 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3846 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3847 bp->utc_tai_offset);
3848 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
3849 timespec64_to_ns(&ts) - ns,
3853 free_page((unsigned long)buf);
3856 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3859 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3861 struct device *dev = s->private;
3866 bp = dev_get_drvdata(dev);
3868 val = ioread32(&bp->tod->ctrl);
3869 if (!(val & TOD_CTRL_ENABLE)) {
3870 seq_printf(s, "TOD Slave disabled\n");
3873 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3875 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3876 idx += (val >> 16) & 3;
3877 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3879 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3880 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3882 val = ioread32(&bp->tod->version);
3883 seq_printf(s, "TOD Version %d.%d.%d\n",
3884 val >> 24, (val >> 16) & 0xff, val & 0xffff);
3886 val = ioread32(&bp->tod->status);
3887 seq_printf(s, "Status register: 0x%08X\n", val);
3889 val = ioread32(&bp->tod->adj_sec);
3890 idx = (val & ~INT_MAX) ? -1 : 1;
3891 idx *= (val & INT_MAX);
3892 seq_printf(s, "Correction seconds: %d\n", idx);
3894 val = ioread32(&bp->tod->utc_status);
3895 seq_printf(s, "UTC status register: 0x%08X\n", val);
3896 seq_printf(s, "UTC offset: %ld valid:%d\n",
3897 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3898 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3899 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3900 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3902 val = ioread32(&bp->tod->leap);
3903 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3907 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3909 static struct dentry *ptp_ocp_debugfs_root;
3912 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3916 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3918 debugfs_create_file("summary", 0444, bp->debug_root,
3919 &bp->dev, &ptp_ocp_summary_fops);
3921 debugfs_create_file("tod_status", 0444, bp->debug_root,
3922 &bp->dev, &ptp_ocp_tod_status_fops);
3926 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3928 debugfs_remove_recursive(bp->debug_root);
3932 ptp_ocp_debugfs_init(void)
3934 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3938 ptp_ocp_debugfs_fini(void)
3940 debugfs_remove_recursive(ptp_ocp_debugfs_root);
3944 ptp_ocp_dev_release(struct device *dev)
3946 struct ptp_ocp *bp = dev_get_drvdata(dev);
3948 mutex_lock(&ptp_ocp_lock);
3949 idr_remove(&ptp_ocp_idr, bp->id);
3950 mutex_unlock(&ptp_ocp_lock);
3954 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3958 mutex_lock(&ptp_ocp_lock);
3959 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3960 mutex_unlock(&ptp_ocp_lock);
3962 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3967 bp->ptp_info = ptp_ocp_clock_info;
3968 spin_lock_init(&bp->lock);
3969 bp->gnss_port.line = -1;
3970 bp->gnss2_port.line = -1;
3971 bp->mac_port.line = -1;
3972 bp->nmea_port.line = -1;
3975 device_initialize(&bp->dev);
3976 dev_set_name(&bp->dev, "ocp%d", bp->id);
3977 bp->dev.class = &timecard_class;
3978 bp->dev.parent = &pdev->dev;
3979 bp->dev.release = ptp_ocp_dev_release;
3980 dev_set_drvdata(&bp->dev, bp);
3982 err = device_add(&bp->dev);
3984 dev_err(&bp->dev, "device add failed: %d\n", err);
3988 pci_set_drvdata(pdev, bp);
3993 ptp_ocp_dev_release(&bp->dev);
3994 put_device(&bp->dev);
3999 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4001 struct device *dev = &bp->dev;
4003 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4004 dev_err(dev, "%s symlink failed\n", link);
4008 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4010 struct device *dev, *child;
4012 dev = &bp->pdev->dev;
4014 child = device_find_child_by_name(dev, name);
4016 dev_err(dev, "Could not find device %s\n", name);
4020 ptp_ocp_symlink(bp, child, link);
4025 ptp_ocp_complete(struct ptp_ocp *bp)
4027 struct pps_device *pps;
4030 if (bp->gnss_port.line != -1) {
4031 sprintf(buf, "ttyS%d", bp->gnss_port.line);
4032 ptp_ocp_link_child(bp, buf, "ttyGNSS");
4034 if (bp->gnss2_port.line != -1) {
4035 sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4036 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4038 if (bp->mac_port.line != -1) {
4039 sprintf(buf, "ttyS%d", bp->mac_port.line);
4040 ptp_ocp_link_child(bp, buf, "ttyMAC");
4042 if (bp->nmea_port.line != -1) {
4043 sprintf(buf, "ttyS%d", bp->nmea_port.line);
4044 ptp_ocp_link_child(bp, buf, "ttyNMEA");
4046 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4047 ptp_ocp_link_child(bp, buf, "ptp");
4049 pps = pps_lookup_dev(bp->ptp);
4051 ptp_ocp_symlink(bp, pps->dev, "pps");
4053 ptp_ocp_debugfs_add_device(bp);
4059 ptp_ocp_phc_info(struct ptp_ocp *bp)
4061 struct timespec64 ts;
4062 u32 version, select;
4065 version = ioread32(&bp->reg->version);
4066 select = ioread32(&bp->reg->select);
4067 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4068 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4069 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4070 ptp_clock_index(bp->ptp));
4072 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
4073 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4074 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4075 ts.tv_sec, ts.tv_nsec,
4076 sync ? "in-sync" : "UNSYNCED");
4080 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4083 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4087 ptp_ocp_info(struct ptp_ocp *bp)
4089 static int nmea_baud[] = {
4090 1200, 2400, 4800, 9600, 19200, 38400,
4091 57600, 115200, 230400, 460800, 921600,
4094 struct device *dev = &bp->pdev->dev;
4097 ptp_ocp_phc_info(bp);
4099 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4100 bp->gnss_port.baud);
4101 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4102 bp->gnss2_port.baud);
4103 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4104 if (bp->nmea_out && bp->nmea_port.line != -1) {
4105 bp->nmea_port.baud = -1;
4107 reg = ioread32(&bp->nmea_out->uart_baud);
4108 if (reg < ARRAY_SIZE(nmea_baud))
4109 bp->nmea_port.baud = nmea_baud[reg];
4111 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4112 bp->nmea_port.baud);
4117 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4119 struct device *dev = &bp->dev;
4121 sysfs_remove_link(&dev->kobj, "ttyGNSS");
4122 sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4123 sysfs_remove_link(&dev->kobj, "ttyMAC");
4124 sysfs_remove_link(&dev->kobj, "ptp");
4125 sysfs_remove_link(&dev->kobj, "pps");
4129 ptp_ocp_detach(struct ptp_ocp *bp)
4133 ptp_ocp_debugfs_remove_device(bp);
4134 ptp_ocp_detach_sysfs(bp);
4135 ptp_ocp_attr_group_del(bp);
4136 if (timer_pending(&bp->watchdog))
4137 del_timer_sync(&bp->watchdog);
4139 ptp_ocp_unregister_ext(bp->ts0);
4141 ptp_ocp_unregister_ext(bp->ts1);
4143 ptp_ocp_unregister_ext(bp->ts2);
4145 ptp_ocp_unregister_ext(bp->ts3);
4147 ptp_ocp_unregister_ext(bp->ts4);
4149 ptp_ocp_unregister_ext(bp->pps);
4150 for (i = 0; i < 4; i++)
4151 if (bp->signal_out[i])
4152 ptp_ocp_unregister_ext(bp->signal_out[i]);
4153 if (bp->gnss_port.line != -1)
4154 serial8250_unregister_port(bp->gnss_port.line);
4155 if (bp->gnss2_port.line != -1)
4156 serial8250_unregister_port(bp->gnss2_port.line);
4157 if (bp->mac_port.line != -1)
4158 serial8250_unregister_port(bp->mac_port.line);
4159 if (bp->nmea_port.line != -1)
4160 serial8250_unregister_port(bp->nmea_port.line);
4161 platform_device_unregister(bp->spi_flash);
4162 platform_device_unregister(bp->i2c_ctrl);
4164 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4166 pci_free_irq_vectors(bp->pdev);
4168 ptp_clock_unregister(bp->ptp);
4169 kfree(bp->ptp_info.pin_config);
4170 device_unregister(&bp->dev);
4174 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4176 struct devlink *devlink;
4180 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4182 dev_err(&pdev->dev, "devlink_alloc failed\n");
4186 err = pci_enable_device(pdev);
4188 dev_err(&pdev->dev, "pci_enable_device\n");
4192 bp = devlink_priv(devlink);
4193 err = ptp_ocp_device_init(bp, pdev);
4198 * Older FPGA firmware only returns 2 irq's.
4199 * allow this - if not all of the IRQ's are returned, skip the
4200 * extra devices and just register the clock.
4202 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4204 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4208 pci_set_master(pdev);
4210 err = ptp_ocp_register_resources(bp, id->driver_data);
4214 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4215 if (IS_ERR(bp->ptp)) {
4216 err = PTR_ERR(bp->ptp);
4217 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4222 err = ptp_ocp_complete(bp);
4227 devlink_register(devlink);
4233 pci_disable_device(pdev);
4235 devlink_free(devlink);
4240 ptp_ocp_remove(struct pci_dev *pdev)
4242 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4243 struct devlink *devlink = priv_to_devlink(bp);
4245 devlink_unregister(devlink);
4247 pci_disable_device(pdev);
4249 devlink_free(devlink);
4252 static struct pci_driver ptp_ocp_driver = {
4253 .name = KBUILD_MODNAME,
4254 .id_table = ptp_ocp_pcidev_id,
4255 .probe = ptp_ocp_probe,
4256 .remove = ptp_ocp_remove,
4260 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4261 unsigned long action, void *data)
4263 struct device *dev, *child = data;
4268 case BUS_NOTIFY_ADD_DEVICE:
4269 case BUS_NOTIFY_DEL_DEVICE:
4270 add = action == BUS_NOTIFY_ADD_DEVICE;
4276 if (!i2c_verify_adapter(child))
4280 while ((dev = dev->parent))
4281 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4286 bp = dev_get_drvdata(dev);
4288 ptp_ocp_symlink(bp, child, "i2c");
4290 sysfs_remove_link(&bp->dev.kobj, "i2c");
4295 static struct notifier_block ptp_ocp_i2c_notifier = {
4296 .notifier_call = ptp_ocp_i2c_notifier_call,
4305 ptp_ocp_debugfs_init();
4307 what = "timecard class";
4308 err = class_register(&timecard_class);
4312 what = "i2c notifier";
4313 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4317 what = "ptp_ocp driver";
4318 err = pci_register_driver(&ptp_ocp_driver);
4325 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4327 class_unregister(&timecard_class);
4329 ptp_ocp_debugfs_fini();
4330 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4337 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4338 pci_unregister_driver(&ptp_ocp_driver);
4339 class_unregister(&timecard_class);
4340 ptp_ocp_debugfs_fini();
4343 module_init(ptp_ocp_init);
4344 module_exit(ptp_ocp_fini);
4346 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4347 MODULE_LICENSE("GPL v2");