1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/debugfs.h>
8 #include <linux/init.h>
10 #include <linux/serial_8250.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/platform_device.h>
14 #include <linux/ptp_clock_kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/xilinx_spi.h>
17 #include <net/devlink.h>
18 #include <linux/i2c.h>
19 #include <linux/mtd/mtd.h>
21 #ifndef PCI_VENDOR_ID_FACEBOOK
22 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
25 #ifndef PCI_DEVICE_ID_FACEBOOK_TIMECARD
26 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
29 static struct class timecard_class = {
57 #define OCP_CTRL_ENABLE BIT(0)
58 #define OCP_CTRL_ADJUST_TIME BIT(1)
59 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
60 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
61 #define OCP_CTRL_ADJUST_SERVO BIT(8)
62 #define OCP_CTRL_READ_TIME_REQ BIT(30)
63 #define OCP_CTRL_READ_TIME_DONE BIT(31)
65 #define OCP_STATUS_IN_SYNC BIT(0)
66 #define OCP_STATUS_IN_HOLDOVER BIT(1)
68 #define OCP_SELECT_CLK_NONE 0
69 #define OCP_SELECT_CLK_REG 0xfe
84 #define TOD_CTRL_PROTOCOL BIT(28)
85 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
86 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
87 #define TOD_CTRL_ENABLE BIT(0)
88 #define TOD_CTRL_GNSS_MASK ((1U << 4) - 1)
89 #define TOD_CTRL_GNSS_SHIFT 24
91 #define TOD_STATUS_UTC_MASK 0xff
92 #define TOD_STATUS_UTC_VALID BIT(8)
93 #define TOD_STATUS_LEAP_VALID BIT(16)
121 #define PPS_STATUS_FILTER_ERR BIT(0)
122 #define PPS_STATUS_SUPERV_ERR BIT(1)
135 struct irig_master_reg {
144 #define IRIG_M_CTRL_ENABLE BIT(0)
146 struct irig_slave_reg {
155 #define IRIG_S_CTRL_ENABLE BIT(0)
157 struct dcf_master_reg {
165 #define DCF_M_CTRL_ENABLE BIT(0)
167 struct dcf_slave_reg {
175 #define DCF_S_CTRL_ENABLE BIT(0)
177 struct ptp_ocp_flash_info {
184 struct ptp_ocp_i2c_info {
186 unsigned long fixed_rate;
191 struct ptp_ocp_ext_info {
193 irqreturn_t (*irq_fcn)(int irq, void *priv);
194 int (*enable)(void *priv, u32 req, bool enable);
197 struct ptp_ocp_ext_src {
200 struct ptp_ocp_ext_info *info;
205 struct pci_dev *pdev;
208 struct ocp_reg __iomem *reg;
209 struct tod_reg __iomem *tod;
210 struct pps_reg __iomem *pps_to_ext;
211 struct pps_reg __iomem *pps_to_clk;
212 struct gpio_reg __iomem *pps_select;
213 struct gpio_reg __iomem *sma;
214 struct irig_master_reg __iomem *irig_out;
215 struct irig_slave_reg __iomem *irig_in;
216 struct dcf_master_reg __iomem *dcf_out;
217 struct dcf_slave_reg __iomem *dcf_in;
218 struct tod_reg __iomem *nmea_out;
219 struct ptp_ocp_ext_src *pps;
220 struct ptp_ocp_ext_src *ts0;
221 struct ptp_ocp_ext_src *ts1;
222 struct ptp_ocp_ext_src *ts2;
223 struct img_reg __iomem *image;
224 struct ptp_clock *ptp;
225 struct ptp_clock_info ptp_info;
226 struct platform_device *i2c_ctrl;
227 struct platform_device *spi_flash;
228 struct clk_hw *i2c_clk;
229 struct timer_list watchdog;
230 struct dentry *debug_root;
236 int mac_port; /* miniature atomic clock */
243 u32 ts_window_adjust;
246 #define OCP_REQ_TIMESTAMP BIT(0)
247 #define OCP_REQ_PPS BIT(1)
249 struct ocp_resource {
250 unsigned long offset;
253 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
255 unsigned long bp_offset;
256 const char * const name;
259 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
260 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
261 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
262 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
263 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
264 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
265 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
266 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
268 #define bp_assign_entry(bp, res, val) ({ \
269 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
270 *(typeof(val) *)addr = val; \
273 #define OCP_RES_LOCATION(member) \
274 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
276 #define OCP_MEM_RESOURCE(member) \
277 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
279 #define OCP_SERIAL_RESOURCE(member) \
280 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
282 #define OCP_I2C_RESOURCE(member) \
283 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
285 #define OCP_SPI_RESOURCE(member) \
286 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
288 #define OCP_EXT_RESOURCE(member) \
289 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
291 /* This is the MSI vector mapping used.
300 * 8: HWICAP (notused)
305 static struct ocp_resource ocp_fb_resource[] = {
307 OCP_MEM_RESOURCE(reg),
308 .offset = 0x01000000, .size = 0x10000,
311 OCP_EXT_RESOURCE(ts0),
312 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
313 .extra = &(struct ptp_ocp_ext_info) {
315 .irq_fcn = ptp_ocp_ts_irq,
316 .enable = ptp_ocp_ts_enable,
320 OCP_EXT_RESOURCE(ts1),
321 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
322 .extra = &(struct ptp_ocp_ext_info) {
324 .irq_fcn = ptp_ocp_ts_irq,
325 .enable = ptp_ocp_ts_enable,
329 OCP_EXT_RESOURCE(ts2),
330 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
331 .extra = &(struct ptp_ocp_ext_info) {
333 .irq_fcn = ptp_ocp_ts_irq,
334 .enable = ptp_ocp_ts_enable,
338 OCP_EXT_RESOURCE(pps),
339 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
340 .extra = &(struct ptp_ocp_ext_info) {
342 .irq_fcn = ptp_ocp_ts_irq,
343 .enable = ptp_ocp_ts_enable,
347 OCP_MEM_RESOURCE(pps_to_ext),
348 .offset = 0x01030000, .size = 0x10000,
351 OCP_MEM_RESOURCE(pps_to_clk),
352 .offset = 0x01040000, .size = 0x10000,
355 OCP_MEM_RESOURCE(tod),
356 .offset = 0x01050000, .size = 0x10000,
359 OCP_MEM_RESOURCE(irig_in),
360 .offset = 0x01070000, .size = 0x10000,
363 OCP_MEM_RESOURCE(irig_out),
364 .offset = 0x01080000, .size = 0x10000,
367 OCP_MEM_RESOURCE(dcf_in),
368 .offset = 0x01090000, .size = 0x10000,
371 OCP_MEM_RESOURCE(dcf_out),
372 .offset = 0x010A0000, .size = 0x10000,
375 OCP_MEM_RESOURCE(nmea_out),
376 .offset = 0x010B0000, .size = 0x10000,
379 OCP_MEM_RESOURCE(image),
380 .offset = 0x00020000, .size = 0x1000,
383 OCP_MEM_RESOURCE(pps_select),
384 .offset = 0x00130000, .size = 0x1000,
387 OCP_MEM_RESOURCE(sma),
388 .offset = 0x00140000, .size = 0x1000,
391 OCP_I2C_RESOURCE(i2c_ctrl),
392 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
393 .extra = &(struct ptp_ocp_i2c_info) {
395 .fixed_rate = 50000000,
399 OCP_SERIAL_RESOURCE(gnss_port),
400 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
403 OCP_SERIAL_RESOURCE(gnss2_port),
404 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
407 OCP_SERIAL_RESOURCE(mac_port),
408 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
411 OCP_SERIAL_RESOURCE(nmea_port),
412 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
415 OCP_SPI_RESOURCE(spi_flash),
416 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
417 .extra = &(struct ptp_ocp_flash_info) {
418 .name = "xilinx_spi", .pci_offset = 0,
419 .data_size = sizeof(struct xspi_platform_data),
420 .data = &(struct xspi_platform_data) {
424 .devices = &(struct spi_board_info) {
425 .modalias = "spi-nor",
431 .setup = ptp_ocp_fb_board_init,
436 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
437 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
440 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
442 static DEFINE_MUTEX(ptp_ocp_lock);
443 static DEFINE_IDR(ptp_ocp_idr);
445 struct ocp_selector {
450 static struct ocp_selector ptp_ocp_clock[] = {
451 { .name = "NONE", .value = 0 },
452 { .name = "TOD", .value = 1 },
453 { .name = "IRIG", .value = 2 },
454 { .name = "PPS", .value = 3 },
455 { .name = "PTP", .value = 4 },
456 { .name = "RTC", .value = 5 },
457 { .name = "DCF", .value = 6 },
458 { .name = "REGS", .value = 0xfe },
459 { .name = "EXT", .value = 0xff },
463 static struct ocp_selector ptp_ocp_sma_in[] = {
464 { .name = "10Mhz", .value = 0x00 },
465 { .name = "PPS1", .value = 0x01 },
466 { .name = "PPS2", .value = 0x02 },
467 { .name = "TS1", .value = 0x04 },
468 { .name = "TS2", .value = 0x08 },
469 { .name = "IRIG", .value = 0x10 },
470 { .name = "DCF", .value = 0x20 },
474 static struct ocp_selector ptp_ocp_sma_out[] = {
475 { .name = "10Mhz", .value = 0x00 },
476 { .name = "PHC", .value = 0x01 },
477 { .name = "MAC", .value = 0x02 },
478 { .name = "GNSS", .value = 0x04 },
479 { .name = "GNSS2", .value = 0x08 },
480 { .name = "IRIG", .value = 0x10 },
481 { .name = "DCF", .value = 0x20 },
486 ptp_ocp_select_name_from_val(struct ocp_selector *tbl, int val)
490 for (i = 0; tbl[i].name; i++)
491 if (tbl[i].value == val)
497 ptp_ocp_select_val_from_name(struct ocp_selector *tbl, const char *name)
502 for (i = 0; tbl[i].name; i++) {
503 select = tbl[i].name;
504 if (!strncasecmp(name, select, strlen(select)))
511 ptp_ocp_select_table_show(struct ocp_selector *tbl, char *buf)
517 for (i = 0; tbl[i].name; i++)
518 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
521 count += sysfs_emit_at(buf, count, "\n");
526 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
527 struct ptp_system_timestamp *sts)
529 u32 ctrl, time_sec, time_ns;
532 ptp_read_system_prets(sts);
534 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
535 iowrite32(ctrl, &bp->reg->ctrl);
537 for (i = 0; i < 100; i++) {
538 ctrl = ioread32(&bp->reg->ctrl);
539 if (ctrl & OCP_CTRL_READ_TIME_DONE)
542 ptp_read_system_postts(sts);
544 if (sts && bp->ts_window_adjust) {
545 s64 ns = timespec64_to_ns(&sts->post_ts);
547 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
550 time_ns = ioread32(&bp->reg->time_ns);
551 time_sec = ioread32(&bp->reg->time_sec);
553 ts->tv_sec = time_sec;
554 ts->tv_nsec = time_ns;
556 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
560 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
561 struct ptp_system_timestamp *sts)
563 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
567 spin_lock_irqsave(&bp->lock, flags);
568 err = __ptp_ocp_gettime_locked(bp, ts, sts);
569 spin_unlock_irqrestore(&bp->lock, flags);
575 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
577 u32 ctrl, time_sec, time_ns;
580 time_ns = ts->tv_nsec;
581 time_sec = ts->tv_sec;
583 select = ioread32(&bp->reg->select);
584 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
586 iowrite32(time_ns, &bp->reg->adjust_ns);
587 iowrite32(time_sec, &bp->reg->adjust_sec);
589 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
590 iowrite32(ctrl, &bp->reg->ctrl);
592 /* restore clock selection */
593 iowrite32(select >> 16, &bp->reg->select);
597 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
599 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
602 spin_lock_irqsave(&bp->lock, flags);
603 __ptp_ocp_settime_locked(bp, ts);
604 spin_unlock_irqrestore(&bp->lock, flags);
610 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
614 select = ioread32(&bp->reg->select);
615 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
617 iowrite32(adj_val, &bp->reg->offset_ns);
618 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
620 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
621 iowrite32(ctrl, &bp->reg->ctrl);
623 /* restore clock selection */
624 iowrite32(select >> 16, &bp->reg->select);
628 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, u64 delta_ns)
630 struct timespec64 ts;
634 spin_lock_irqsave(&bp->lock, flags);
635 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
637 timespec64_add_ns(&ts, delta_ns);
638 __ptp_ocp_settime_locked(bp, &ts);
640 spin_unlock_irqrestore(&bp->lock, flags);
644 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
646 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
650 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
651 ptp_ocp_adjtime_coarse(bp, delta_ns);
655 sign = delta_ns < 0 ? BIT(31) : 0;
656 adj_ns = sign ? -delta_ns : delta_ns;
658 spin_lock_irqsave(&bp->lock, flags);
659 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
660 spin_unlock_irqrestore(&bp->lock, flags);
666 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
675 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
681 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
684 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
685 struct ptp_ocp_ext_src *ext = NULL;
690 case PTP_CLK_REQ_EXTTS:
691 req = OCP_REQ_TIMESTAMP;
692 switch (rq->extts.index) {
707 case PTP_CLK_REQ_PPS:
711 case PTP_CLK_REQ_PEROUT:
713 (rq->perout.period.sec != 1 || rq->perout.period.nsec != 0))
715 /* This is a request for 1PPS on an output SMA.
716 * Allow, but assume manual configuration.
725 err = ext->info->enable(ext, req, on);
730 static const struct ptp_clock_info ptp_ocp_clock_info = {
731 .owner = THIS_MODULE,
732 .name = KBUILD_MODNAME,
733 .max_adj = 100000000,
734 .gettimex64 = ptp_ocp_gettimex,
735 .settime64 = ptp_ocp_settime,
736 .adjtime = ptp_ocp_adjtime,
737 .adjfine = ptp_ocp_null_adjfine,
738 .adjphase = ptp_ocp_null_adjphase,
739 .enable = ptp_ocp_enable,
746 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
750 select = ioread32(&bp->reg->select);
751 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
753 iowrite32(0, &bp->reg->drift_ns);
755 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
756 iowrite32(ctrl, &bp->reg->ctrl);
758 /* restore clock selection */
759 iowrite32(select >> 16, &bp->reg->select);
763 ptp_ocp_watchdog(struct timer_list *t)
765 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
769 status = ioread32(&bp->pps_to_clk->status);
771 if (status & PPS_STATUS_SUPERV_ERR) {
772 iowrite32(status, &bp->pps_to_clk->status);
773 if (!bp->gnss_lost) {
774 spin_lock_irqsave(&bp->lock, flags);
775 __ptp_ocp_clear_drift_locked(bp);
776 spin_unlock_irqrestore(&bp->lock, flags);
777 bp->gnss_lost = ktime_get_real_seconds();
780 } else if (bp->gnss_lost) {
784 mod_timer(&bp->watchdog, jiffies + HZ);
788 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
794 ctrl = ioread32(&bp->reg->ctrl);
795 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
797 iowrite32(ctrl, &bp->reg->ctrl);
799 start = ktime_get_ns();
801 ctrl = ioread32(&bp->reg->ctrl);
803 end = ktime_get_ns();
806 bp->ts_window_adjust = (delay >> 5) * 3;
810 ptp_ocp_init_clock(struct ptp_ocp *bp)
812 struct timespec64 ts;
816 ctrl = OCP_CTRL_ENABLE;
817 iowrite32(ctrl, &bp->reg->ctrl);
819 /* NO DRIFT Correction */
820 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
821 iowrite32(0x2000, &bp->reg->servo_offset_p);
822 iowrite32(0x1000, &bp->reg->servo_offset_i);
823 iowrite32(0, &bp->reg->servo_drift_p);
824 iowrite32(0, &bp->reg->servo_drift_i);
826 /* latch servo values */
827 ctrl |= OCP_CTRL_ADJUST_SERVO;
828 iowrite32(ctrl, &bp->reg->ctrl);
830 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
831 dev_err(&bp->pdev->dev, "clock not enabled\n");
835 ptp_ocp_estimate_pci_timing(bp);
837 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
839 ktime_get_clocktai_ts64(&ts);
840 ptp_ocp_settime(&bp->ptp_info, &ts);
843 /* If there is a clock supervisor, then enable the watchdog */
844 if (bp->pps_to_clk) {
845 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
846 mod_timer(&bp->watchdog, jiffies + HZ);
853 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
857 spin_lock_irqsave(&bp->lock, flags);
859 bp->utc_tai_offset = val;
862 iowrite32(val, &bp->irig_out->adj_sec);
864 iowrite32(val, &bp->dcf_out->adj_sec);
866 iowrite32(val, &bp->nmea_out->adj_sec);
868 spin_unlock_irqrestore(&bp->lock, flags);
872 ptp_ocp_tod_init(struct ptp_ocp *bp)
876 ctrl = ioread32(&bp->tod->ctrl);
877 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
878 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
879 iowrite32(ctrl, &bp->tod->ctrl);
881 reg = ioread32(&bp->tod->utc_status);
882 if (reg & TOD_STATUS_UTC_VALID)
883 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
887 ptp_ocp_tod_info(struct ptp_ocp *bp)
889 static const char * const proto_name[] = {
890 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
891 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
893 static const char * const gnss_name[] = {
894 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
896 u32 version, ctrl, reg;
899 version = ioread32(&bp->tod->version);
900 dev_info(&bp->pdev->dev, "TOD Version %d.%d.%d\n",
901 version >> 24, (version >> 16) & 0xff, version & 0xffff);
903 ctrl = ioread32(&bp->tod->ctrl);
904 idx = ctrl & TOD_CTRL_PROTOCOL ? 4 : 0;
905 idx += (ctrl >> 16) & 3;
906 dev_info(&bp->pdev->dev, "control: %x\n", ctrl);
907 dev_info(&bp->pdev->dev, "TOD Protocol %s %s\n", proto_name[idx],
908 ctrl & TOD_CTRL_ENABLE ? "enabled" : "");
910 idx = (ctrl >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
911 if (idx < ARRAY_SIZE(gnss_name))
912 dev_info(&bp->pdev->dev, "GNSS %s\n", gnss_name[idx]);
914 reg = ioread32(&bp->tod->status);
915 dev_info(&bp->pdev->dev, "status: %x\n", reg);
917 reg = ioread32(&bp->tod->adj_sec);
918 dev_info(&bp->pdev->dev, "correction: %d\n", reg);
920 reg = ioread32(&bp->tod->utc_status);
921 dev_info(&bp->pdev->dev, "utc_status: %x\n", reg);
922 dev_info(&bp->pdev->dev, "utc_offset: %d valid:%d leap_valid:%d\n",
923 reg & TOD_STATUS_UTC_MASK, reg & TOD_STATUS_UTC_VALID ? 1 : 0,
924 reg & TOD_STATUS_LEAP_VALID ? 1 : 0);
928 ptp_ocp_firstchild(struct device *dev, void *data)
934 ptp_ocp_read_i2c(struct i2c_adapter *adap, u8 addr, u8 reg, u8 sz, u8 *data)
936 struct i2c_msg msgs[2] = {
952 /* xiic-i2c for some stupid reason only does 2 byte reads. */
954 len = min_t(u8, sz, 2);
956 err = i2c_transfer(adap, msgs, 2);
957 if (err != msgs[1].len)
967 ptp_ocp_get_serial_number(struct ptp_ocp *bp)
969 struct i2c_adapter *adap;
976 dev = device_find_child(&bp->i2c_ctrl->dev, NULL, ptp_ocp_firstchild);
978 dev_err(&bp->pdev->dev, "Can't find I2C adapter\n");
982 adap = i2c_verify_adapter(dev);
984 dev_err(&bp->pdev->dev, "device '%s' isn't an I2C adapter\n",
989 err = ptp_ocp_read_i2c(adap, 0x58, 0x9A, 6, bp->serial);
991 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", err);
995 bp->has_serial = true;
1001 static struct device *
1002 ptp_ocp_find_flash(struct ptp_ocp *bp)
1004 struct device *dev, *last;
1007 dev = &bp->spi_flash->dev;
1009 while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) {
1010 if (!strcmp("mtd", dev_bus_name(dev)))
1021 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1022 const struct firmware *fw)
1024 struct mtd_info *mtd = dev_get_drvdata(dev);
1025 struct ptp_ocp *bp = devlink_priv(devlink);
1026 size_t off, len, resid, wrote;
1027 struct erase_info erase;
1032 base = bp->flash_start;
1037 devlink_flash_update_status_notify(devlink, "Flashing",
1038 NULL, off, fw->size);
1040 len = min_t(size_t, resid, blksz);
1041 erase.addr = base + off;
1044 err = mtd_erase(mtd, &erase);
1048 err = mtd_write(mtd, base + off, len, &wrote, &fw->data[off]);
1060 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1061 struct devlink_flash_update_params *params,
1062 struct netlink_ext_ack *extack)
1064 struct ptp_ocp *bp = devlink_priv(devlink);
1069 dev = ptp_ocp_find_flash(bp);
1071 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1075 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1078 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1080 msg = err ? "Flash error" : "Flash complete";
1081 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1088 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1089 struct netlink_ext_ack *extack)
1091 struct ptp_ocp *bp = devlink_priv(devlink);
1095 err = devlink_info_driver_name_put(req, KBUILD_MODNAME);
1100 u32 ver = ioread32(&bp->image->version);
1103 sprintf(buf, "%d", ver);
1104 err = devlink_info_version_running_put(req,
1108 sprintf(buf, "%d", ver >> 16);
1109 err = devlink_info_version_running_put(req,
1117 if (!bp->has_serial)
1118 ptp_ocp_get_serial_number(bp);
1120 if (bp->has_serial) {
1121 sprintf(buf, "%pM", bp->serial);
1122 err = devlink_info_serial_number_put(req, buf);
1130 static const struct devlink_ops ptp_ocp_devlink_ops = {
1131 .flash_update = ptp_ocp_devlink_flash_update,
1132 .info_get = ptp_ocp_devlink_info_get,
1135 static void __iomem *
1136 __ptp_ocp_get_mem(struct ptp_ocp *bp, unsigned long start, int size)
1138 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1140 return devm_ioremap_resource(&bp->pdev->dev, &res);
1143 static void __iomem *
1144 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1146 unsigned long start;
1148 start = pci_resource_start(bp->pdev, 0) + r->offset;
1149 return __ptp_ocp_get_mem(bp, start, r->size);
1153 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1155 struct resource r = DEFINE_RES_IRQ(irq);
1160 ptp_ocp_set_mem_resource(struct resource *res, unsigned long start, int size)
1162 struct resource r = DEFINE_RES_MEM(start, size);
1167 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1169 struct ptp_ocp_flash_info *info;
1170 struct pci_dev *pdev = bp->pdev;
1171 struct platform_device *p;
1172 struct resource res[2];
1173 unsigned long start;
1176 start = pci_resource_start(pdev, 0) + r->offset;
1177 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1178 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1181 id = pci_dev_id(pdev) << 1;
1182 id += info->pci_offset;
1184 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1190 bp_assign_entry(bp, r, p);
1195 static struct platform_device *
1196 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1198 struct ptp_ocp_i2c_info *info;
1199 struct resource res[2];
1200 unsigned long start;
1203 start = pci_resource_start(pdev, 0) + r->offset;
1204 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1205 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1207 return platform_device_register_resndata(&pdev->dev, info->name,
1209 info->data, info->data_size);
1213 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1215 struct pci_dev *pdev = bp->pdev;
1216 struct ptp_ocp_i2c_info *info;
1217 struct platform_device *p;
1223 id = pci_dev_id(bp->pdev);
1225 sprintf(buf, "AXI.%d", id);
1226 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1229 return PTR_ERR(clk);
1232 sprintf(buf, "%s.%d", info->name, id);
1233 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1234 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1238 bp_assign_entry(bp, r, p);
1244 ptp_ocp_ts_irq(int irq, void *priv)
1246 struct ptp_ocp_ext_src *ext = priv;
1247 struct ts_reg __iomem *reg = ext->mem;
1248 struct ptp_clock_event ev;
1251 if (ext == ext->bp->pps) {
1252 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1253 ev.type = PTP_CLOCK_PPS;
1254 ptp_clock_event(ext->bp->ptp, &ev);
1257 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1261 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1262 sec = ioread32(®->time_sec);
1263 nsec = ioread32(®->time_ns);
1265 ev.type = PTP_CLOCK_EXTTS;
1266 ev.index = ext->info->index;
1267 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1269 ptp_clock_event(ext->bp->ptp, &ev);
1272 iowrite32(1, ®->intr); /* write 1 to ack */
1278 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1280 struct ptp_ocp_ext_src *ext = priv;
1281 struct ts_reg __iomem *reg = ext->mem;
1282 struct ptp_ocp *bp = ext->bp;
1284 if (ext == bp->pps) {
1285 u32 old_map = bp->pps_req_map;
1288 bp->pps_req_map |= req;
1290 bp->pps_req_map &= ~req;
1292 /* if no state change, just return */
1293 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1298 iowrite32(1, ®->enable);
1299 iowrite32(1, ®->intr_mask);
1300 iowrite32(1, ®->intr);
1302 iowrite32(0, ®->intr_mask);
1303 iowrite32(0, ®->enable);
1310 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1312 ext->info->enable(ext, ~0, false);
1313 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1318 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1320 struct pci_dev *pdev = bp->pdev;
1321 struct ptp_ocp_ext_src *ext;
1324 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
1328 ext->mem = ptp_ocp_get_mem(bp, r);
1329 if (IS_ERR(ext->mem)) {
1330 err = PTR_ERR(ext->mem);
1335 ext->info = r->extra;
1336 ext->irq_vec = r->irq_vec;
1338 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
1339 ext, "ocp%d.%s", bp->id, r->name);
1341 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
1345 bp_assign_entry(bp, r, ext);
1355 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
1357 struct pci_dev *pdev = bp->pdev;
1358 struct uart_8250_port uart;
1360 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
1361 * the serial port device claim and release the pci resource.
1363 memset(&uart, 0, sizeof(uart));
1364 uart.port.dev = &pdev->dev;
1365 uart.port.iotype = UPIO_MEM;
1366 uart.port.regshift = 2;
1367 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
1368 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
1369 uart.port.uartclk = 50000000;
1370 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP;
1371 uart.port.type = PORT_16550A;
1373 return serial8250_register_8250_port(&uart);
1377 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
1381 port = ptp_ocp_serial_line(bp, r);
1385 bp_assign_entry(bp, r, port);
1391 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1395 mem = ptp_ocp_get_mem(bp, r);
1397 return PTR_ERR(mem);
1399 bp_assign_entry(bp, r, mem);
1405 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
1410 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
1411 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
1412 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
1415 /* FB specific board initializers; last "resource" registered. */
1417 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
1419 bp->flash_start = 1024 * 4096;
1421 ptp_ocp_tod_init(bp);
1422 ptp_ocp_nmea_out_init(bp);
1424 return ptp_ocp_init_clock(bp);
1428 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
1430 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
1433 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
1434 r->irq_vec, r->name);
1439 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
1441 struct ocp_resource *r, *table;
1444 table = (struct ocp_resource *)driver_data;
1445 for (r = table; r->setup; r++) {
1446 if (!ptp_ocp_allow_irq(bp, r))
1448 err = r->setup(bp, r);
1450 dev_err(&bp->pdev->dev,
1451 "Could not register %s: err %d\n",
1460 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
1465 ctrl = ioread32(reg);
1469 ctrl |= enable ? bit : 0;
1470 iowrite32(ctrl, reg);
1475 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
1477 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
1478 IRIG_M_CTRL_ENABLE, enable);
1482 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
1484 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
1485 IRIG_S_CTRL_ENABLE, enable);
1489 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
1491 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
1492 DCF_M_CTRL_ENABLE, enable);
1496 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
1498 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
1499 DCF_S_CTRL_ENABLE, enable);
1503 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
1505 ptp_ocp_irig_out(bp, val & 0x00100010);
1506 ptp_ocp_dcf_out(bp, val & 0x00200020);
1510 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
1512 ptp_ocp_irig_in(bp, val & 0x00100010);
1513 ptp_ocp_dcf_in(bp, val & 0x00200020);
1520 * ANT3 == sma3 (out)
1521 * ANT4 == sma4 (out)
1524 enum ptp_ocp_sma_mode {
1529 static struct ptp_ocp_sma_connector {
1530 enum ptp_ocp_sma_mode mode;
1532 u16 default_out_idx;
1533 } ptp_ocp_sma_map[4] = {
1535 .mode = SMA_MODE_IN,
1539 .mode = SMA_MODE_IN,
1543 .mode = SMA_MODE_OUT,
1545 .default_out_idx = 0, /* 10Mhz */
1548 .mode = SMA_MODE_OUT,
1550 .default_out_idx = 1, /* PHC */
1555 ptp_ocp_show_output(u32 val, char *buf, int default_idx)
1560 count = sysfs_emit(buf, "OUT: ");
1561 name = ptp_ocp_select_name_from_val(ptp_ocp_sma_out, val);
1563 name = ptp_ocp_sma_out[default_idx].name;
1564 count += sysfs_emit_at(buf, count, "%s\n", name);
1569 ptp_ocp_show_inputs(u32 val, char *buf, const char *zero_in)
1575 count = sysfs_emit(buf, "IN: ");
1576 for (i = 0; i < ARRAY_SIZE(ptp_ocp_sma_in); i++) {
1577 if (val & ptp_ocp_sma_in[i].value) {
1578 name = ptp_ocp_sma_in[i].name;
1579 count += sysfs_emit_at(buf, count, "%s ", name);
1582 if (!val && zero_in)
1583 count += sysfs_emit_at(buf, count, "%s ", zero_in);
1586 count += sysfs_emit_at(buf, count, "\n");
1591 sma_parse_inputs(const char *buf, enum ptp_ocp_sma_mode *mode)
1593 struct ocp_selector *tbl[] = { ptp_ocp_sma_in, ptp_ocp_sma_out };
1594 int idx, count, dir;
1598 argv = argv_split(GFP_KERNEL, buf, &count);
1607 dir = *mode == SMA_MODE_IN ? 0 : 1;
1608 if (!strcasecmp("IN:", argv[idx])) {
1612 if (!strcasecmp("OUT:", argv[0])) {
1616 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
1619 for (; idx < count; idx++)
1620 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
1630 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, u32 val, char *buf,
1631 const char *zero_in)
1633 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1];
1635 if (sma->mode == SMA_MODE_IN)
1636 return ptp_ocp_show_inputs(val, buf, zero_in);
1638 return ptp_ocp_show_output(val, buf, sma->default_out_idx);
1642 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
1644 struct ptp_ocp *bp = dev_get_drvdata(dev);
1647 val = ioread32(&bp->sma->gpio1) & 0x3f;
1648 return ptp_ocp_sma_show(bp, 1, val, buf, ptp_ocp_sma_in[0].name);
1652 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
1654 struct ptp_ocp *bp = dev_get_drvdata(dev);
1657 val = (ioread32(&bp->sma->gpio1) >> 16) & 0x3f;
1658 return ptp_ocp_sma_show(bp, 2, val, buf, NULL);
1662 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
1664 struct ptp_ocp *bp = dev_get_drvdata(dev);
1667 val = ioread32(&bp->sma->gpio2) & 0x3f;
1668 return ptp_ocp_sma_show(bp, 3, val, buf, NULL);
1672 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
1674 struct ptp_ocp *bp = dev_get_drvdata(dev);
1677 val = (ioread32(&bp->sma->gpio2) >> 16) & 0x3f;
1678 return ptp_ocp_sma_show(bp, 4, val, buf, NULL);
1682 ptp_ocp_sma_store_output(struct ptp_ocp *bp, u32 val, u32 shift)
1684 unsigned long flags;
1687 mask = 0xffff << (16 - shift);
1689 spin_lock_irqsave(&bp->lock, flags);
1691 gpio = ioread32(&bp->sma->gpio2);
1692 gpio = (gpio & mask) | (val << shift);
1694 __handle_signal_outputs(bp, gpio);
1696 iowrite32(gpio, &bp->sma->gpio2);
1698 spin_unlock_irqrestore(&bp->lock, flags);
1702 ptp_ocp_sma_store_inputs(struct ptp_ocp *bp, u32 val, u32 shift)
1704 unsigned long flags;
1707 mask = 0xffff << (16 - shift);
1709 spin_lock_irqsave(&bp->lock, flags);
1711 gpio = ioread32(&bp->sma->gpio1);
1712 gpio = (gpio & mask) | (val << shift);
1714 __handle_signal_inputs(bp, gpio);
1716 iowrite32(gpio, &bp->sma->gpio1);
1718 spin_unlock_irqrestore(&bp->lock, flags);
1722 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr, u32 shift)
1724 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1];
1725 enum ptp_ocp_sma_mode mode;
1729 val = sma_parse_inputs(buf, &mode);
1733 if (mode != sma->mode && sma->fixed_mode)
1736 if (mode != sma->mode) {
1737 pr_err("Mode changes not supported yet.\n");
1741 if (sma->mode == SMA_MODE_IN)
1742 ptp_ocp_sma_store_inputs(bp, val, shift);
1744 ptp_ocp_sma_store_output(bp, val, shift);
1750 sma1_store(struct device *dev, struct device_attribute *attr,
1751 const char *buf, size_t count)
1753 struct ptp_ocp *bp = dev_get_drvdata(dev);
1756 err = ptp_ocp_sma_store(bp, buf, 1, 0);
1757 return err ? err : count;
1761 sma2_store(struct device *dev, struct device_attribute *attr,
1762 const char *buf, size_t count)
1764 struct ptp_ocp *bp = dev_get_drvdata(dev);
1767 err = ptp_ocp_sma_store(bp, buf, 2, 16);
1768 return err ? err : count;
1772 sma3_store(struct device *dev, struct device_attribute *attr,
1773 const char *buf, size_t count)
1775 struct ptp_ocp *bp = dev_get_drvdata(dev);
1778 err = ptp_ocp_sma_store(bp, buf, 3, 0);
1779 return err ? err : count;
1783 sma4_store(struct device *dev, struct device_attribute *attr,
1784 const char *buf, size_t count)
1786 struct ptp_ocp *bp = dev_get_drvdata(dev);
1789 err = ptp_ocp_sma_store(bp, buf, 4, 16);
1790 return err ? err : count;
1792 static DEVICE_ATTR_RW(sma1);
1793 static DEVICE_ATTR_RW(sma2);
1794 static DEVICE_ATTR_RW(sma3);
1795 static DEVICE_ATTR_RW(sma4);
1798 available_sma_inputs_show(struct device *dev,
1799 struct device_attribute *attr, char *buf)
1801 return ptp_ocp_select_table_show(ptp_ocp_sma_in, buf);
1803 static DEVICE_ATTR_RO(available_sma_inputs);
1806 available_sma_outputs_show(struct device *dev,
1807 struct device_attribute *attr, char *buf)
1809 return ptp_ocp_select_table_show(ptp_ocp_sma_out, buf);
1811 static DEVICE_ATTR_RO(available_sma_outputs);
1814 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
1816 struct ptp_ocp *bp = dev_get_drvdata(dev);
1818 if (!bp->has_serial)
1819 ptp_ocp_get_serial_number(bp);
1821 return sysfs_emit(buf, "%pM\n", bp->serial);
1823 static DEVICE_ATTR_RO(serialnum);
1826 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
1828 struct ptp_ocp *bp = dev_get_drvdata(dev);
1832 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
1834 ret = sysfs_emit(buf, "SYNC\n");
1838 static DEVICE_ATTR_RO(gnss_sync);
1841 utc_tai_offset_show(struct device *dev,
1842 struct device_attribute *attr, char *buf)
1844 struct ptp_ocp *bp = dev_get_drvdata(dev);
1846 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
1850 utc_tai_offset_store(struct device *dev,
1851 struct device_attribute *attr,
1852 const char *buf, size_t count)
1854 struct ptp_ocp *bp = dev_get_drvdata(dev);
1858 err = kstrtou32(buf, 0, &val);
1862 ptp_ocp_utc_distribute(bp, val);
1866 static DEVICE_ATTR_RW(utc_tai_offset);
1869 ts_window_adjust_show(struct device *dev,
1870 struct device_attribute *attr, char *buf)
1872 struct ptp_ocp *bp = dev_get_drvdata(dev);
1874 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
1878 ts_window_adjust_store(struct device *dev,
1879 struct device_attribute *attr,
1880 const char *buf, size_t count)
1882 struct ptp_ocp *bp = dev_get_drvdata(dev);
1886 err = kstrtou32(buf, 0, &val);
1890 bp->ts_window_adjust = val;
1894 static DEVICE_ATTR_RW(ts_window_adjust);
1897 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1899 struct ptp_ocp *bp = dev_get_drvdata(dev);
1902 val = ioread32(&bp->irig_out->ctrl);
1903 val = (val >> 16) & 0x07;
1904 return sysfs_emit(buf, "%d\n", val);
1908 irig_b_mode_store(struct device *dev,
1909 struct device_attribute *attr,
1910 const char *buf, size_t count)
1912 struct ptp_ocp *bp = dev_get_drvdata(dev);
1913 unsigned long flags;
1918 err = kstrtou8(buf, 0, &val);
1924 reg = ((val & 0x7) << 16);
1926 spin_lock_irqsave(&bp->lock, flags);
1927 iowrite32(0, &bp->irig_out->ctrl); /* disable */
1928 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
1929 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
1930 spin_unlock_irqrestore(&bp->lock, flags);
1934 static DEVICE_ATTR_RW(irig_b_mode);
1937 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
1939 struct ptp_ocp *bp = dev_get_drvdata(dev);
1943 select = ioread32(&bp->reg->select);
1944 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
1946 return sysfs_emit(buf, "%s\n", p);
1950 clock_source_store(struct device *dev, struct device_attribute *attr,
1951 const char *buf, size_t count)
1953 struct ptp_ocp *bp = dev_get_drvdata(dev);
1954 unsigned long flags;
1957 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
1961 spin_lock_irqsave(&bp->lock, flags);
1962 iowrite32(val, &bp->reg->select);
1963 spin_unlock_irqrestore(&bp->lock, flags);
1967 static DEVICE_ATTR_RW(clock_source);
1970 available_clock_sources_show(struct device *dev,
1971 struct device_attribute *attr, char *buf)
1973 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
1975 static DEVICE_ATTR_RO(available_clock_sources);
1977 static struct attribute *timecard_attrs[] = {
1978 &dev_attr_serialnum.attr,
1979 &dev_attr_gnss_sync.attr,
1980 &dev_attr_clock_source.attr,
1981 &dev_attr_available_clock_sources.attr,
1982 &dev_attr_sma1.attr,
1983 &dev_attr_sma2.attr,
1984 &dev_attr_sma3.attr,
1985 &dev_attr_sma4.attr,
1986 &dev_attr_available_sma_inputs.attr,
1987 &dev_attr_available_sma_outputs.attr,
1988 &dev_attr_irig_b_mode.attr,
1989 &dev_attr_utc_tai_offset.attr,
1990 &dev_attr_ts_window_adjust.attr,
1993 ATTRIBUTE_GROUPS(timecard);
1996 gpio_map(u32 gpio, u32 bit, const char *pri, const char *sec, const char *def)
2000 if (gpio & (1 << bit))
2002 else if (gpio & (1 << (bit + 16)))
2010 gpio_multi_map(char *buf, u32 gpio, u32 bit,
2011 const char *pri, const char *sec, const char *def)
2016 if (gpio & (1 << bit))
2017 ans += sprintf(ans, "%s ", pri);
2018 if (gpio & (1 << (bit + 16)))
2019 ans += sprintf(ans, "%s ", sec);
2023 ptp_ocp_summary_show(struct seq_file *s, void *data)
2025 struct device *dev = s->private;
2026 struct ptp_system_timestamp sts;
2027 u32 sma_in, sma_out, ctrl, val;
2028 struct ts_reg __iomem *ts_reg;
2029 struct timespec64 ts;
2035 buf = (char *)__get_free_page(GFP_KERNEL);
2039 bp = dev_get_drvdata(dev);
2040 sma_in = ioread32(&bp->sma->gpio1);
2041 sma_out = ioread32(&bp->sma->gpio2);
2043 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
2045 sma1_show(dev, NULL, buf);
2046 seq_printf(s, " sma1: %s", buf);
2048 sma2_show(dev, NULL, buf);
2049 seq_printf(s, " sma2: %s", buf);
2051 sma3_show(dev, NULL, buf);
2052 seq_printf(s, " sma3: %s", buf);
2054 sma4_show(dev, NULL, buf);
2055 seq_printf(s, " sma4: %s", buf);
2058 ts_reg = bp->ts0->mem;
2059 on = ioread32(&ts_reg->enable);
2061 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
2062 on ? " ON" : "OFF", src);
2066 ts_reg = bp->ts1->mem;
2067 on = ioread32(&ts_reg->enable);
2068 src = gpio_map(sma_in, 2, "sma1", "sma2", "----");
2069 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
2070 on ? " ON" : "OFF", src);
2074 ts_reg = bp->ts2->mem;
2075 on = ioread32(&ts_reg->enable);
2076 src = gpio_map(sma_in, 3, "sma1", "sma2", "----");
2077 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
2078 on ? " ON" : "OFF", src);
2082 ts_reg = bp->pps->mem;
2084 on = ioread32(&ts_reg->enable);
2085 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
2086 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
2087 on && map ? " ON" : "OFF", src);
2089 map = !!(bp->pps_req_map & OCP_REQ_PPS);
2090 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
2091 on && map ? " ON" : "OFF", src);
2095 ctrl = ioread32(&bp->irig_out->ctrl);
2096 on = ctrl & IRIG_M_CTRL_ENABLE;
2097 val = ioread32(&bp->irig_out->status);
2098 gpio_multi_map(buf, sma_out, 4, "sma3", "sma4", "----");
2099 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
2100 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
2104 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
2105 val = ioread32(&bp->irig_in->status);
2106 src = gpio_map(sma_in, 4, "sma1", "sma2", "----");
2107 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
2108 on ? " ON" : "OFF", val, src);
2112 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
2113 val = ioread32(&bp->dcf_out->status);
2114 gpio_multi_map(buf, sma_out, 5, "sma3", "sma4", "----");
2115 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
2116 on ? " ON" : "OFF", val, buf);
2120 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
2121 val = ioread32(&bp->dcf_in->status);
2122 src = gpio_map(sma_in, 5, "sma1", "sma2", "----");
2123 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
2124 on ? " ON" : "OFF", val, src);
2128 on = ioread32(&bp->nmea_out->ctrl) & 1;
2129 val = ioread32(&bp->nmea_out->status);
2130 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
2131 on ? " ON" : "OFF", val);
2134 /* compute src for PPS1, used below. */
2135 if (bp->pps_select) {
2136 val = ioread32(&bp->pps_select->gpio1);
2138 src = gpio_map(sma_in, 0, "sma1", "sma2", "----");
2139 else if (val & 0x02)
2141 else if (val & 0x04)
2149 /* assumes automatic switchover/selection */
2150 val = ioread32(&bp->reg->select);
2151 switch (val >> 16) {
2153 sprintf(buf, "----");
2156 sprintf(buf, "IRIG");
2159 sprintf(buf, "%s via PPS1", src);
2162 sprintf(buf, "DCF");
2165 strcpy(buf, "unknown");
2168 val = ioread32(&bp->reg->status);
2169 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
2170 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
2172 /* reuses PPS1 src from earlier */
2173 seq_printf(s, "MAC PPS1 src: %s\n", src);
2175 src = gpio_map(sma_in, 1, "sma1", "sma2", "GNSS2");
2176 seq_printf(s, "MAC PPS2 src: %s\n", src);
2178 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
2179 struct timespec64 sys_ts;
2180 s64 pre_ns, post_ns, ns;
2182 pre_ns = timespec64_to_ns(&sts.pre_ts);
2183 post_ns = timespec64_to_ns(&sts.post_ts);
2184 ns = (pre_ns + post_ns) / 2;
2185 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
2186 sys_ts = ns_to_timespec64(ns);
2188 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
2189 ts.tv_sec, ts.tv_nsec, &ts);
2190 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
2191 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
2192 bp->utc_tai_offset);
2193 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
2194 timespec64_to_ns(&ts) - ns,
2198 free_page((unsigned long)buf);
2201 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
2203 static struct dentry *ptp_ocp_debugfs_root;
2206 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
2210 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
2212 debugfs_create_file("summary", 0444, bp->debug_root,
2213 &bp->dev, &ptp_ocp_summary_fops);
2217 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
2219 debugfs_remove_recursive(bp->debug_root);
2223 ptp_ocp_debugfs_init(void)
2225 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
2229 ptp_ocp_debugfs_fini(void)
2231 debugfs_remove_recursive(ptp_ocp_debugfs_root);
2235 ptp_ocp_dev_release(struct device *dev)
2237 struct ptp_ocp *bp = dev_get_drvdata(dev);
2239 mutex_lock(&ptp_ocp_lock);
2240 idr_remove(&ptp_ocp_idr, bp->id);
2241 mutex_unlock(&ptp_ocp_lock);
2245 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
2249 mutex_lock(&ptp_ocp_lock);
2250 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
2251 mutex_unlock(&ptp_ocp_lock);
2253 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
2258 bp->ptp_info = ptp_ocp_clock_info;
2259 spin_lock_init(&bp->lock);
2261 bp->gnss2_port = -1;
2266 device_initialize(&bp->dev);
2267 dev_set_name(&bp->dev, "ocp%d", bp->id);
2268 bp->dev.class = &timecard_class;
2269 bp->dev.parent = &pdev->dev;
2270 bp->dev.release = ptp_ocp_dev_release;
2271 dev_set_drvdata(&bp->dev, bp);
2273 err = device_add(&bp->dev);
2275 dev_err(&bp->dev, "device add failed: %d\n", err);
2279 pci_set_drvdata(pdev, bp);
2284 ptp_ocp_dev_release(&bp->dev);
2285 put_device(&bp->dev);
2290 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
2292 struct device *dev = &bp->dev;
2294 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
2295 dev_err(dev, "%s symlink failed\n", link);
2299 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
2301 struct device *dev, *child;
2303 dev = &bp->pdev->dev;
2305 child = device_find_child_by_name(dev, name);
2307 dev_err(dev, "Could not find device %s\n", name);
2311 ptp_ocp_symlink(bp, child, link);
2316 ptp_ocp_complete(struct ptp_ocp *bp)
2318 struct pps_device *pps;
2321 if (bp->gnss_port != -1) {
2322 sprintf(buf, "ttyS%d", bp->gnss_port);
2323 ptp_ocp_link_child(bp, buf, "ttyGNSS");
2325 if (bp->gnss2_port != -1) {
2326 sprintf(buf, "ttyS%d", bp->gnss2_port);
2327 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
2329 if (bp->mac_port != -1) {
2330 sprintf(buf, "ttyS%d", bp->mac_port);
2331 ptp_ocp_link_child(bp, buf, "ttyMAC");
2333 if (bp->nmea_port != -1) {
2334 sprintf(buf, "ttyS%d", bp->nmea_port);
2335 ptp_ocp_link_child(bp, buf, "ttyNMEA");
2337 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
2338 ptp_ocp_link_child(bp, buf, "ptp");
2340 pps = pps_lookup_dev(bp->ptp);
2342 ptp_ocp_symlink(bp, pps->dev, "pps");
2344 if (device_add_groups(&bp->dev, timecard_groups))
2345 pr_err("device add groups failed\n");
2347 ptp_ocp_debugfs_add_device(bp);
2353 ptp_ocp_phc_info(struct ptp_ocp *bp)
2355 struct timespec64 ts;
2356 u32 version, select;
2359 version = ioread32(&bp->reg->version);
2360 select = ioread32(&bp->reg->select);
2361 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
2362 version >> 24, (version >> 16) & 0xff, version & 0xffff,
2363 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
2364 ptp_clock_index(bp->ptp));
2366 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
2367 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
2368 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
2369 ts.tv_sec, ts.tv_nsec,
2370 sync ? "in-sync" : "UNSYNCED");
2374 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
2377 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
2381 ptp_ocp_info(struct ptp_ocp *bp)
2383 static int nmea_baud[] = {
2384 1200, 2400, 4800, 9600, 19200, 38400,
2385 57600, 115200, 230400, 460800, 921600,
2388 struct device *dev = &bp->pdev->dev;
2391 ptp_ocp_phc_info(bp);
2393 ptp_ocp_tod_info(bp);
2396 u32 ver = ioread32(&bp->image->version);
2398 dev_info(dev, "version %x\n", ver);
2400 dev_info(dev, "regular image, version %d\n",
2403 dev_info(dev, "golden image, version %d\n",
2406 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port, 115200);
2407 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port, 115200);
2408 ptp_ocp_serial_info(dev, "MAC", bp->mac_port, 57600);
2409 if (bp->nmea_out && bp->nmea_port != -1) {
2412 reg = ioread32(&bp->nmea_out->uart_baud);
2413 if (reg < ARRAY_SIZE(nmea_baud))
2414 baud = nmea_baud[reg];
2415 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port, baud);
2420 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
2422 struct device *dev = &bp->dev;
2424 sysfs_remove_link(&dev->kobj, "ttyGNSS");
2425 sysfs_remove_link(&dev->kobj, "ttyMAC");
2426 sysfs_remove_link(&dev->kobj, "ptp");
2427 sysfs_remove_link(&dev->kobj, "pps");
2428 device_remove_groups(dev, timecard_groups);
2432 ptp_ocp_detach(struct ptp_ocp *bp)
2434 ptp_ocp_debugfs_remove_device(bp);
2435 ptp_ocp_detach_sysfs(bp);
2436 if (timer_pending(&bp->watchdog))
2437 del_timer_sync(&bp->watchdog);
2439 ptp_ocp_unregister_ext(bp->ts0);
2441 ptp_ocp_unregister_ext(bp->ts1);
2443 ptp_ocp_unregister_ext(bp->ts2);
2445 ptp_ocp_unregister_ext(bp->pps);
2446 if (bp->gnss_port != -1)
2447 serial8250_unregister_port(bp->gnss_port);
2448 if (bp->gnss2_port != -1)
2449 serial8250_unregister_port(bp->gnss2_port);
2450 if (bp->mac_port != -1)
2451 serial8250_unregister_port(bp->mac_port);
2452 if (bp->nmea_port != -1)
2453 serial8250_unregister_port(bp->nmea_port);
2455 platform_device_unregister(bp->spi_flash);
2457 platform_device_unregister(bp->i2c_ctrl);
2459 clk_hw_unregister_fixed_rate(bp->i2c_clk);
2461 pci_free_irq_vectors(bp->pdev);
2463 ptp_clock_unregister(bp->ptp);
2464 device_unregister(&bp->dev);
2468 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2470 struct devlink *devlink;
2474 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
2476 dev_err(&pdev->dev, "devlink_alloc failed\n");
2480 err = pci_enable_device(pdev);
2482 dev_err(&pdev->dev, "pci_enable_device\n");
2483 goto out_unregister;
2486 bp = devlink_priv(devlink);
2487 err = ptp_ocp_device_init(bp, pdev);
2492 * Older FPGA firmware only returns 2 irq's.
2493 * allow this - if not all of the IRQ's are returned, skip the
2494 * extra devices and just register the clock.
2496 err = pci_alloc_irq_vectors(pdev, 1, 11, PCI_IRQ_MSI | PCI_IRQ_MSIX);
2498 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
2502 pci_set_master(pdev);
2504 err = ptp_ocp_register_resources(bp, id->driver_data);
2508 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
2509 if (IS_ERR(bp->ptp)) {
2510 err = PTR_ERR(bp->ptp);
2511 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
2516 err = ptp_ocp_complete(bp);
2521 devlink_register(devlink);
2526 pci_set_drvdata(pdev, NULL);
2528 pci_disable_device(pdev);
2530 devlink_free(devlink);
2535 ptp_ocp_remove(struct pci_dev *pdev)
2537 struct ptp_ocp *bp = pci_get_drvdata(pdev);
2538 struct devlink *devlink = priv_to_devlink(bp);
2540 devlink_unregister(devlink);
2542 pci_set_drvdata(pdev, NULL);
2543 pci_disable_device(pdev);
2545 devlink_free(devlink);
2548 static struct pci_driver ptp_ocp_driver = {
2549 .name = KBUILD_MODNAME,
2550 .id_table = ptp_ocp_pcidev_id,
2551 .probe = ptp_ocp_probe,
2552 .remove = ptp_ocp_remove,
2556 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
2557 unsigned long action, void *data)
2559 struct device *dev, *child = data;
2564 case BUS_NOTIFY_ADD_DEVICE:
2565 case BUS_NOTIFY_DEL_DEVICE:
2566 add = action == BUS_NOTIFY_ADD_DEVICE;
2572 if (!i2c_verify_adapter(child))
2576 while ((dev = dev->parent))
2577 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
2582 bp = dev_get_drvdata(dev);
2584 ptp_ocp_symlink(bp, child, "i2c");
2586 sysfs_remove_link(&bp->dev.kobj, "i2c");
2591 static struct notifier_block ptp_ocp_i2c_notifier = {
2592 .notifier_call = ptp_ocp_i2c_notifier_call,
2601 ptp_ocp_debugfs_init();
2603 what = "timecard class";
2604 err = class_register(&timecard_class);
2608 what = "i2c notifier";
2609 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
2613 what = "ptp_ocp driver";
2614 err = pci_register_driver(&ptp_ocp_driver);
2621 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
2623 class_unregister(&timecard_class);
2625 ptp_ocp_debugfs_fini();
2626 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
2633 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
2634 pci_unregister_driver(&ptp_ocp_driver);
2635 class_unregister(&timecard_class);
2636 ptp_ocp_debugfs_fini();
2639 module_init(ptp_ocp_init);
2640 module_exit(ptp_ocp_fini);
2642 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
2643 MODULE_LICENSE("GPL v2");