drivers/ptp/ptp_idt82p33.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2018 Integrated Device Technology, Inc
   4 //
   5
   6 #define pr_fmt(fmt) "IDT_82p33xxx: " fmt
   7
   8 #include <linux/firmware.h>
   9 #include <linux/i2c.h>
  10 #include <linux/module.h>
  11 #include <linux/ptp_clock_kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timekeeping.h>
  15 #include <linux/bitops.h>
  16
  17 #include "ptp_private.h"
  18 #include "ptp_idt82p33.h"
  19
  20 MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
  21 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  22 MODULE_VERSION("1.0");
  23 MODULE_LICENSE("GPL");
  24 MODULE_FIRMWARE(FW_FILENAME);
  25
  26 /* Module Parameters */
  27 static u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC;
  28 module_param(sync_tod_timeout, uint, 0);
  29 MODULE_PARM_DESC(sync_tod_timeout,
  30 "duration in second to keep SYNC_TOD on (set to 0 to keep it always on)");
  31
  32 static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
  33 module_param(phase_snap_threshold, uint, 0);
  34 MODULE_PARM_DESC(phase_snap_threshold,
  35 "threshold (150000ns by default) below which adjtime would ignore");
  36
  37 static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
  38                                             u8 buf[TOD_BYTE_COUNT])
  39 {
  40         time64_t sec;
  41         s32 nsec;
  42         u8 i;
  43
  44         nsec = buf[3];
  45         for (i = 0; i < 3; i++) {
  46                 nsec <<= 8;
  47                 nsec |= buf[2 - i];
  48         }
  49
  50         sec = buf[9];
  51         for (i = 0; i < 5; i++) {
  52                 sec <<= 8;
  53                 sec |= buf[8 - i];
  54         }
  55
  56         ts->tv_sec = sec;
  57         ts->tv_nsec = nsec;
  58 }
  59
  60 static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
  61                                             u8 buf[TOD_BYTE_COUNT])
  62 {
  63         time64_t sec;
  64         s32 nsec;
  65         u8 i;
  66
  67         nsec = ts->tv_nsec;
  68         sec = ts->tv_sec;
  69
  70         for (i = 0; i < 4; i++) {
  71                 buf[i] = nsec & 0xff;
  72                 nsec >>= 8;
  73         }
  74
  75         for (i = 4; i < TOD_BYTE_COUNT; i++) {
  76                 buf[i] = sec & 0xff;
  77                 sec >>= 8;
  78         }
  79 }
  80
  81 static int idt82p33_xfer_read(struct idt82p33 *idt82p33,
  82                               unsigned char regaddr,
  83                               unsigned char *buf,
  84                               unsigned int count)
  85 {
  86         struct i2c_client *client = idt82p33->client;
  87         struct i2c_msg msg[2];
  88         int cnt;
  89
  90         msg[0].addr = client->addr;
  91         msg[0].flags = 0;
  92         msg[0].len = 1;
  93         msg[0].buf = &regaddr;
  94
  95         msg[1].addr = client->addr;
  96         msg[1].flags = I2C_M_RD;
  97         msg[1].len = count;
  98         msg[1].buf = buf;
  99
 100         cnt = i2c_transfer(client->adapter, msg, 2);
 101         if (cnt < 0) {
 102                 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
 103                 return cnt;
 104         } else if (cnt != 2) {
 105                 dev_err(&client->dev,
 106                         "i2c_transfer sent only %d of %d messages\n", cnt, 2);
 107                 return -EIO;
 108         }
 109         return 0;
 110 }
 111
 112 static int idt82p33_xfer_write(struct idt82p33 *idt82p33,
 113                                u8 regaddr,
 114                                u8 *buf,
 115                                u16 count)
 116 {
 117         struct i2c_client *client = idt82p33->client;
 118         /* we add 1 byte for device register */
 119         u8 msg[IDT82P33_MAX_WRITE_COUNT + 1];
 120         int err;
 121
 122         if (count > IDT82P33_MAX_WRITE_COUNT)
 123                 return -EINVAL;
 124
 125         msg[0] = regaddr;
 126         memcpy(&msg[1], buf, count);
 127
 128         err = i2c_master_send(client, msg, count + 1);
 129         if (err < 0) {
 130                 dev_err(&client->dev, "i2c_master_send returned %d\n", err);
 131                 return err;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val)
 138 {
 139         int err;
 140
 141         if (idt82p33->page_offset == val)
 142                 return 0;
 143
 144         err = idt82p33_xfer_write(idt82p33, PAGE_ADDR, &val, sizeof(val));
 145         if (err)
 146                 dev_err(&idt82p33->client->dev,
 147                         "failed to set page offset %d\n", val);
 148         else
 149                 idt82p33->page_offset = val;
 150
 151         return err;
 152 }
 153
 154 static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr,
 155                          unsigned char *buf, unsigned int count, bool write)
 156 {
 157         u8 offset, page;
 158         int err;
 159
 160         page = _PAGE(regaddr);
 161         offset = _OFFSET(regaddr);
 162
 163         err = idt82p33_page_offset(idt82p33, page);
 164         if (err)
 165                 return err;
 166
 167         if (write)
 168                 return idt82p33_xfer_write(idt82p33, offset, buf, count);
 169
 170         return idt82p33_xfer_read(idt82p33, offset, buf, count);
 171 }
 172
 173 static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr,
 174                         unsigned char *buf, unsigned int count)
 175 {
 176         return idt82p33_rdwr(idt82p33, regaddr, buf, count, false);
 177 }
 178
 179 static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr,
 180                         unsigned char *buf, unsigned int count)
 181 {
 182         return idt82p33_rdwr(idt82p33, regaddr, buf, count, true);
 183 }
 184
 185 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
 186                                   enum pll_mode mode)
 187 {
 188         struct idt82p33 *idt82p33 = channel->idt82p33;
 189         u8 dpll_mode;
 190         int err;
 191
 192         if (channel->pll_mode == mode)
 193                 return 0;
 194
 195         err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
 196                             &dpll_mode, sizeof(dpll_mode));
 197         if (err)
 198                 return err;
 199
 200         dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
 201
 202         dpll_mode |= (mode << PLL_MODE_SHIFT);
 203
 204         err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
 205                              &dpll_mode, sizeof(dpll_mode));
 206         if (err)
 207                 return err;
 208
 209         channel->pll_mode = dpll_mode;
 210
 211         return 0;
 212 }
 213
 214 static int _idt82p33_gettime(struct idt82p33_channel *channel,
 215                              struct timespec64 *ts)
 216 {
 217         struct idt82p33 *idt82p33 = channel->idt82p33;
 218         u8 buf[TOD_BYTE_COUNT];
 219         u8 trigger;
 220         int err;
 221
 222         trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 223                               HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
 224
 225
 226         err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 227                              &trigger, sizeof(trigger));
 228
 229         if (err)
 230                 return err;
 231
 232         if (idt82p33->calculate_overhead_flag)
 233                 idt82p33->start_time = ktime_get_raw();
 234
 235         err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
 236
 237         if (err)
 238                 return err;
 239
 240         idt82p33_byte_array_to_timespec(ts, buf);
 241
 242         return 0;
 243 }
 244
 245 /*
 246  *   TOD Trigger:
 247  *   Bits[7:4] Write 0x9, MSB write
 248  *   Bits[3:0] Read 0x9, LSB read
 249  */
 250
 251 static int _idt82p33_settime(struct idt82p33_channel *channel,
 252                              struct timespec64 const *ts)
 253 {
 254         struct idt82p33 *idt82p33 = channel->idt82p33;
 255         struct timespec64 local_ts = *ts;
 256         char buf[TOD_BYTE_COUNT];
 257         s64 dynamic_overhead_ns;
 258         unsigned char trigger;
 259         int err;
 260         u8 i;
 261
 262         trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 263                               HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
 264
 265         err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 266                         &trigger, sizeof(trigger));
 267
 268         if (err)
 269                 return err;
 270
 271         if (idt82p33->calculate_overhead_flag) {
 272                 dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
 273                                         - ktime_to_ns(idt82p33->start_time);
 274
 275                 timespec64_add_ns(&local_ts, dynamic_overhead_ns);
 276
 277                 idt82p33->calculate_overhead_flag = 0;
 278         }
 279
 280         idt82p33_timespec_to_byte_array(&local_ts, buf);
 281
 282         /*
 283          * Store the new time value.
 284          */
 285         for (i = 0; i < TOD_BYTE_COUNT; i++) {
 286                 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
 287                                      &buf[i], sizeof(buf[i]));
 288                 if (err)
 289                         return err;
 290         }
 291
 292         return err;
 293 }
 294
 295 static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
 296 {
 297         struct idt82p33 *idt82p33 = channel->idt82p33;
 298         struct timespec64 ts;
 299         s64 now_ns;
 300         int err;
 301
 302         idt82p33->calculate_overhead_flag = 1;
 303
 304         err = _idt82p33_gettime(channel, &ts);
 305
 306         if (err)
 307                 return err;
 308
 309         now_ns = timespec64_to_ns(&ts);
 310         now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
 311
 312         ts = ns_to_timespec64(now_ns);
 313
 314         err = _idt82p33_settime(channel, &ts);
 315
 316         return err;
 317 }
 318
 319 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
 320 {
 321         struct idt82p33 *idt82p33 = channel->idt82p33;
 322         unsigned char buf[5] = {0};
 323         int neg_adj = 0;
 324         int err, i;
 325         s64 fcw;
 326
 327         if (scaled_ppm == channel->current_freq_ppb)
 328                 return 0;
 329
 330         /*
 331          * Frequency Control Word unit is: 1.68 * 10^-10 ppm
 332          *
 333          * adjfreq:
 334          *       ppb * 10^9
 335          * FCW = ----------
 336          *          168
 337          *
 338          * adjfine:
 339          *       scaled_ppm * 5^12
 340          * FCW = -------------
 341          *         168 * 2^4
 342          */
 343         if (scaled_ppm < 0) {
 344                 neg_adj = 1;
 345                 scaled_ppm = -scaled_ppm;
 346         }
 347
 348         fcw = scaled_ppm * 244140625ULL;
 349         fcw = div_u64(fcw, 2688);
 350
 351         if (neg_adj)
 352                 fcw = -fcw;
 353
 354         for (i = 0; i < 5; i++) {
 355                 buf[i] = fcw & 0xff;
 356                 fcw >>= 8;
 357         }
 358
 359         err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
 360
 361         if (err)
 362                 return err;
 363
 364         err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
 365                              buf, sizeof(buf));
 366
 367         if (err == 0)
 368                 channel->current_freq_ppb = scaled_ppm;
 369
 370         return err;
 371 }
 372
 373 static int idt82p33_measure_one_byte_write_overhead(
 374                 struct idt82p33_channel *channel, s64 *overhead_ns)
 375 {
 376         struct idt82p33 *idt82p33 = channel->idt82p33;
 377         ktime_t start, stop;
 378         s64 total_ns;
 379         u8 trigger;
 380         int err;
 381         u8 i;
 382
 383         total_ns = 0;
 384         *overhead_ns = 0;
 385         trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 386                               HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
 387
 388         for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 389
 390                 start = ktime_get_raw();
 391
 392                 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 393                                      &trigger, sizeof(trigger));
 394
 395                 stop = ktime_get_raw();
 396
 397                 if (err)
 398                         return err;
 399
 400                 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 401         }
 402
 403         *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
 404
 405         return err;
 406 }
 407
 408 static int idt82p33_measure_tod_write_9_byte_overhead(
 409                         struct idt82p33_channel *channel)
 410 {
 411         struct idt82p33 *idt82p33 = channel->idt82p33;
 412         u8 buf[TOD_BYTE_COUNT];
 413         ktime_t start, stop;
 414         s64 total_ns;
 415         int err = 0;
 416         u8 i, j;
 417
 418         total_ns = 0;
 419         idt82p33->tod_write_overhead_ns = 0;
 420
 421         for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 422
 423                 start = ktime_get_raw();
 424
 425                 /* Need one less byte for applicable overhead */
 426                 for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
 427                         err = idt82p33_write(idt82p33,
 428                                              channel->dpll_tod_cnfg + i,
 429                                              &buf[i], sizeof(buf[i]));
 430                         if (err)
 431                                 return err;
 432                 }
 433
 434                 stop = ktime_get_raw();
 435
 436                 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 437         }
 438
 439         idt82p33->tod_write_overhead_ns = div_s64(total_ns,
 440                                                   MAX_MEASURMENT_COUNT);
 441
 442         return err;
 443 }
 444
 445 static int idt82p33_measure_settime_gettime_gap_overhead(
 446                 struct idt82p33_channel *channel, s64 *overhead_ns)
 447 {
 448         struct timespec64 ts1 = {0, 0};
 449         struct timespec64 ts2;
 450         int err;
 451
 452         *overhead_ns = 0;
 453
 454         err = _idt82p33_settime(channel, &ts1);
 455
 456         if (err)
 457                 return err;
 458
 459         err = _idt82p33_gettime(channel, &ts2);
 460
 461         if (!err)
 462                 *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
 463
 464         return err;
 465 }
 466
 467 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
 468 {
 469         s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
 470         struct idt82p33 *idt82p33 = channel->idt82p33;
 471         int err;
 472
 473         idt82p33->tod_write_overhead_ns = 0;
 474
 475         err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
 476
 477         if (err) {
 478                 dev_err(&idt82p33->client->dev,
 479                         "Failed in %s with err %d!\n", __func__, err);
 480                 return err;
 481         }
 482
 483         err = idt82p33_measure_one_byte_write_overhead(channel,
 484                                                        &one_byte_write_ns);
 485
 486         if (err)
 487                 return err;
 488
 489         err = idt82p33_measure_tod_write_9_byte_overhead(channel);
 490
 491         if (err)
 492                 return err;
 493
 494         trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
 495
 496         idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
 497
 498         return err;
 499 }
 500
 501 static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
 502                                         u8 page,
 503                                         u8 offset,
 504                                         u8 val)
 505 {
 506         int err = 0;
 507
 508         if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
 509                 if ((val & 0xfc) || !(val & 0x3)) {
 510                         dev_err(&idt82p33->client->dev,
 511                                 "Invalid PLL mask 0x%hhx\n", val);
 512                         err = -EINVAL;
 513                 } else {
 514                         idt82p33->pll_mask = val;
 515                 }
 516         } else if (page == PLL0_OUTMASK_ADDR_HI &&
 517                 offset == PLL0_OUTMASK_ADDR_LO) {
 518                 idt82p33->channel[0].output_mask = val;
 519         } else if (page == PLL1_OUTMASK_ADDR_HI &&
 520                 offset == PLL1_OUTMASK_ADDR_LO) {
 521                 idt82p33->channel[1].output_mask = val;
 522         }
 523
 524         return err;
 525 }
 526
 527 static void idt82p33_display_masks(struct idt82p33 *idt82p33)
 528 {
 529         u8 mask, i;
 530
 531         dev_info(&idt82p33->client->dev,
 532                  "pllmask = 0x%02x\n", idt82p33->pll_mask);
 533
 534         for (i = 0; i < MAX_PHC_PLL; i++) {
 535                 mask = 1 << i;
 536
 537                 if (mask & idt82p33->pll_mask)
 538                         dev_info(&idt82p33->client->dev,
 539                                  "PLL%d output_mask = 0x%04x\n",
 540                                  i, idt82p33->channel[i].output_mask);
 541         }
 542 }
 543
 544 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
 545 {
 546         struct idt82p33 *idt82p33 = channel->idt82p33;
 547         u8 sync_cnfg;
 548         int err;
 549
 550         /* Turn it off after sync_tod_timeout seconds */
 551         if (enable && sync_tod_timeout)
 552                 ptp_schedule_worker(channel->ptp_clock,
 553                                     sync_tod_timeout * HZ);
 554
 555         err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
 556                             &sync_cnfg, sizeof(sync_cnfg));
 557         if (err)
 558                 return err;
 559
 560         sync_cnfg &= ~SYNC_TOD;
 561         if (enable)
 562                 sync_cnfg |= SYNC_TOD;
 563
 564         return idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
 565                               &sync_cnfg, sizeof(sync_cnfg));
 566 }
 567
 568 static long idt82p33_sync_tod_work_handler(struct ptp_clock_info *ptp)
 569 {
 570         struct idt82p33_channel *channel =
 571                         container_of(ptp, struct idt82p33_channel, caps);
 572         struct idt82p33 *idt82p33 = channel->idt82p33;
 573
 574         mutex_lock(&idt82p33->reg_lock);
 575
 576         (void)idt82p33_sync_tod(channel, false);
 577
 578         mutex_unlock(&idt82p33->reg_lock);
 579
 580         /* Return a negative value here to not reschedule */
 581         return -1;
 582 }
 583
 584 static int idt82p33_output_enable(struct idt82p33_channel *channel,
 585                                   bool enable, unsigned int outn)
 586 {
 587         struct idt82p33 *idt82p33 = channel->idt82p33;
 588         int err;
 589         u8 val;
 590
 591         err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
 592         if (err)
 593                 return err;
 594         if (enable)
 595                 val &= ~SQUELCH_ENABLE;
 596         else
 597                 val |= SQUELCH_ENABLE;
 598
 599         return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
 600 }
 601
 602 static int idt82p33_output_mask_enable(struct idt82p33_channel *channel,
 603                                        bool enable)
 604 {
 605         u16 mask;
 606         int err;
 607         u8 outn;
 608
 609         mask = channel->output_mask;
 610         outn = 0;
 611
 612         while (mask) {
 613                 if (mask & 0x1) {
 614                         err = idt82p33_output_enable(channel, enable, outn);
 615                         if (err)
 616                                 return err;
 617                 }
 618
 619                 mask >>= 0x1;
 620                 outn++;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int idt82p33_perout_enable(struct idt82p33_channel *channel,
 627                                   bool enable,
 628                                   struct ptp_perout_request *perout)
 629 {
 630         unsigned int flags = perout->flags;
 631
 632         /* Enable/disable output based on output_mask */
 633         if (flags == PEROUT_ENABLE_OUTPUT_MASK)
 634                 return idt82p33_output_mask_enable(channel, enable);
 635
 636         /* Enable/disable individual output instead */
 637         return idt82p33_output_enable(channel, enable, perout->index);
 638 }
 639
 640 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
 641 {
 642         struct idt82p33 *idt82p33 = channel->idt82p33;
 643         struct timespec64 ts = {0, 0};
 644         int err;
 645         u8 val;
 646
 647         val = 0;
 648         err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
 649                              &val, sizeof(val));
 650         if (err)
 651                 return err;
 652
 653         err = idt82p33_measure_tod_write_overhead(channel);
 654
 655         if (err) {
 656                 dev_err(&idt82p33->client->dev,
 657                         "Failed in %s with err %d!\n", __func__, err);
 658                 return err;
 659         }
 660
 661         err = _idt82p33_settime(channel, &ts);
 662
 663         if (err)
 664                 return err;
 665
 666         return idt82p33_sync_tod(channel, true);
 667 }
 668
 669 static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
 670 {
 671         struct idt82p33_channel *channel;
 672         u8 i;
 673
 674         for (i = 0; i < MAX_PHC_PLL; i++) {
 675
 676                 channel = &idt82p33->channel[i];
 677
 678                 if (channel->ptp_clock)
 679                         ptp_clock_unregister(channel->ptp_clock);
 680         }
 681 }
 682
 683 static int idt82p33_enable(struct ptp_clock_info *ptp,
 684                          struct ptp_clock_request *rq, int on)
 685 {
 686         struct idt82p33_channel *channel =
 687                         container_of(ptp, struct idt82p33_channel, caps);
 688         struct idt82p33 *idt82p33 = channel->idt82p33;
 689         int err;
 690
 691         err = -EOPNOTSUPP;
 692
 693         mutex_lock(&idt82p33->reg_lock);
 694
 695         if (rq->type == PTP_CLK_REQ_PEROUT) {
 696                 if (!on)
 697                         err = idt82p33_perout_enable(channel, false,
 698                                                      &rq->perout);
 699                 /* Only accept a 1-PPS aligned to the second. */
 700                 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
 701                     rq->perout.period.nsec) {
 702                         err = -ERANGE;
 703                 } else
 704                         err = idt82p33_perout_enable(channel, true,
 705                                                      &rq->perout);
 706         }
 707
 708         mutex_unlock(&idt82p33->reg_lock);
 709
 710         return err;
 711 }
 712
 713 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
 714 {
 715         struct idt82p33_channel *channel =
 716                 container_of(ptp, struct idt82p33_channel, caps);
 717         struct idt82p33 *idt82p33 = channel->idt82p33;
 718         s64 offset_regval, offset_fs;
 719         u8 val[4] = {0};
 720         int err;
 721
 722         offset_fs = (s64)(-offset_ns) * 1000000;
 723
 724         if (offset_fs > WRITE_PHASE_OFFSET_LIMIT)
 725                 offset_fs = WRITE_PHASE_OFFSET_LIMIT;
 726         else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT)
 727                 offset_fs = -WRITE_PHASE_OFFSET_LIMIT;
 728
 729         /* Convert from phaseoffset_fs to register value */
 730         offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL);
 731
 732         val[0] = offset_regval & 0xFF;
 733         val[1] = (offset_regval >> 8) & 0xFF;
 734         val[2] = (offset_regval >> 16) & 0xFF;
 735         val[3] = (offset_regval >> 24) & 0x1F;
 736         val[3] |= PH_OFFSET_EN;
 737
 738         mutex_lock(&idt82p33->reg_lock);
 739
 740         err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH);
 741         if (err) {
 742                 dev_err(&idt82p33->client->dev,
 743                         "Failed in %s with err %d!\n", __func__, err);
 744                 goto out;
 745         }
 746
 747         err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
 748                              sizeof(val));
 749
 750 out:
 751         mutex_unlock(&idt82p33->reg_lock);
 752         return err;
 753 }
 754
 755 static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
 756 {
 757         struct idt82p33_channel *channel =
 758                         container_of(ptp, struct idt82p33_channel, caps);
 759         struct idt82p33 *idt82p33 = channel->idt82p33;
 760         int err;
 761
 762         mutex_lock(&idt82p33->reg_lock);
 763         err = _idt82p33_adjfine(channel, scaled_ppm);
 764         if (err)
 765                 dev_err(&idt82p33->client->dev,
 766                         "Failed in %s with err %d!\n", __func__, err);
 767         mutex_unlock(&idt82p33->reg_lock);
 768
 769         return err;
 770 }
 771
 772 static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
 773 {
 774         struct idt82p33_channel *channel =
 775                         container_of(ptp, struct idt82p33_channel, caps);
 776         struct idt82p33 *idt82p33 = channel->idt82p33;
 777         int err;
 778
 779         mutex_lock(&idt82p33->reg_lock);
 780
 781         if (abs(delta_ns) < phase_snap_threshold) {
 782                 mutex_unlock(&idt82p33->reg_lock);
 783                 return 0;
 784         }
 785
 786         err = _idt82p33_adjtime(channel, delta_ns);
 787
 788         if (err) {
 789                 mutex_unlock(&idt82p33->reg_lock);
 790                 dev_err(&idt82p33->client->dev,
 791                         "Adjtime failed in %s with err %d!\n", __func__, err);
 792                 return err;
 793         }
 794
 795         err = idt82p33_sync_tod(channel, true);
 796         if (err)
 797                 dev_err(&idt82p33->client->dev,
 798                         "Sync_tod failed in %s with err %d!\n", __func__, err);
 799
 800         mutex_unlock(&idt82p33->reg_lock);
 801
 802         return err;
 803 }
 804
 805 static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 806 {
 807         struct idt82p33_channel *channel =
 808                         container_of(ptp, struct idt82p33_channel, caps);
 809         struct idt82p33 *idt82p33 = channel->idt82p33;
 810         int err;
 811
 812         mutex_lock(&idt82p33->reg_lock);
 813         err = _idt82p33_gettime(channel, ts);
 814         if (err)
 815                 dev_err(&idt82p33->client->dev,
 816                         "Failed in %s with err %d!\n", __func__, err);
 817         mutex_unlock(&idt82p33->reg_lock);
 818
 819         return err;
 820 }
 821
 822 static int idt82p33_settime(struct ptp_clock_info *ptp,
 823                         const struct timespec64 *ts)
 824 {
 825         struct idt82p33_channel *channel =
 826                         container_of(ptp, struct idt82p33_channel, caps);
 827         struct idt82p33 *idt82p33 = channel->idt82p33;
 828         int err;
 829
 830         mutex_lock(&idt82p33->reg_lock);
 831         err = _idt82p33_settime(channel, ts);
 832         if (err)
 833                 dev_err(&idt82p33->client->dev,
 834                         "Failed in %s with err %d!\n", __func__, err);
 835         mutex_unlock(&idt82p33->reg_lock);
 836
 837         return err;
 838 }
 839
 840 static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
 841 {
 842         switch (index) {
 843         case 0:
 844                 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
 845                 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
 846                 channel->dpll_tod_sts = DPLL1_TOD_STS;
 847                 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
 848                 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
 849                 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
 850                 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
 851                 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
 852                 break;
 853         case 1:
 854                 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
 855                 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
 856                 channel->dpll_tod_sts = DPLL2_TOD_STS;
 857                 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
 858                 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
 859                 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
 860                 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
 861                 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
 862                 break;
 863         default:
 864                 return -EINVAL;
 865         }
 866
 867         channel->current_freq_ppb = 0;
 868
 869         return 0;
 870 }
 871
 872 static void idt82p33_caps_init(struct ptp_clock_info *caps)
 873 {
 874         caps->owner = THIS_MODULE;
 875         caps->max_adj = 92000;
 876         caps->n_per_out = 11;
 877         caps->adjphase = idt82p33_adjwritephase;
 878         caps->adjfine = idt82p33_adjfine;
 879         caps->adjtime = idt82p33_adjtime;
 880         caps->gettime64 = idt82p33_gettime;
 881         caps->settime64 = idt82p33_settime;
 882         caps->enable = idt82p33_enable;
 883         caps->do_aux_work = idt82p33_sync_tod_work_handler;
 884 }
 885
 886 static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
 887 {
 888         struct idt82p33_channel *channel;
 889         int err;
 890
 891         if (!(index < MAX_PHC_PLL))
 892                 return -EINVAL;
 893
 894         channel = &idt82p33->channel[index];
 895
 896         err = idt82p33_channel_init(channel, index);
 897         if (err) {
 898                 dev_err(&idt82p33->client->dev,
 899                         "Channel_init failed in %s with err %d!\n",
 900                         __func__, err);
 901                 return err;
 902         }
 903
 904         channel->idt82p33 = idt82p33;
 905
 906         idt82p33_caps_init(&channel->caps);
 907         snprintf(channel->caps.name, sizeof(channel->caps.name),
 908                  "IDT 82P33 PLL%u", index);
 909
 910         channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
 911
 912         if (IS_ERR(channel->ptp_clock)) {
 913                 err = PTR_ERR(channel->ptp_clock);
 914                 channel->ptp_clock = NULL;
 915                 return err;
 916         }
 917
 918         if (!channel->ptp_clock)
 919                 return -ENOTSUPP;
 920
 921         err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
 922         if (err) {
 923                 dev_err(&idt82p33->client->dev,
 924                         "Dpll_set_mode failed in %s with err %d!\n",
 925                         __func__, err);
 926                 return err;
 927         }
 928
 929         err = idt82p33_enable_tod(channel);
 930         if (err) {
 931                 dev_err(&idt82p33->client->dev,
 932                         "Enable_tod failed in %s with err %d!\n",
 933                         __func__, err);
 934                 return err;
 935         }
 936
 937         dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n",
 938                  index, channel->ptp_clock->index);
 939
 940         return 0;
 941 }
 942
 943 static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
 944 {
 945         const struct firmware *fw;
 946         struct idt82p33_fwrc *rec;
 947         u8 loaddr, page, val;
 948         int err;
 949         s32 len;
 950
 951         dev_dbg(&idt82p33->client->dev,
 952                 "requesting firmware '%s'\n", FW_FILENAME);
 953
 954         err = request_firmware(&fw, FW_FILENAME, &idt82p33->client->dev);
 955
 956         if (err) {
 957                 dev_err(&idt82p33->client->dev,
 958                         "Failed in %s with err %d!\n", __func__, err);
 959                 return err;
 960         }
 961
 962         dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size);
 963
 964         rec = (struct idt82p33_fwrc *) fw->data;
 965
 966         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
 967
 968                 if (rec->reserved) {
 969                         dev_err(&idt82p33->client->dev,
 970                                 "bad firmware, reserved field non-zero\n");
 971                         err = -EINVAL;
 972                 } else {
 973                         val = rec->value;
 974                         loaddr = rec->loaddr;
 975                         page = rec->hiaddr;
 976
 977                         rec++;
 978
 979                         err = idt82p33_check_and_set_masks(idt82p33, page,
 980                                                            loaddr, val);
 981                 }
 982
 983                 if (err == 0) {
 984                         /* maximum 8 pages  */
 985                         if (page >= PAGE_NUM)
 986                                 continue;
 987
 988                         /* Page size 128, last 4 bytes of page skipped */
 989                         if (((loaddr > 0x7b) && (loaddr <= 0x7f))
 990                              || loaddr > 0xfb)
 991                                 continue;
 992
 993                         err = idt82p33_write(idt82p33, _ADDR(page, loaddr),
 994                                              &val, sizeof(val));
 995                 }
 996
 997                 if (err)
 998                         goto out;
 999         }
1000
1001         idt82p33_display_masks(idt82p33);
1002 out:
1003         release_firmware(fw);
1004         return err;
1005 }
1006
1007
1008 static int idt82p33_probe(struct i2c_client *client,
1009                           const struct i2c_device_id *id)
1010 {
1011         struct idt82p33 *idt82p33;
1012         int err;
1013         u8 i;
1014
1015         (void)id;
1016
1017         idt82p33 = devm_kzalloc(&client->dev,
1018                                 sizeof(struct idt82p33), GFP_KERNEL);
1019         if (!idt82p33)
1020                 return -ENOMEM;
1021
1022         mutex_init(&idt82p33->reg_lock);
1023
1024         idt82p33->client = client;
1025         idt82p33->page_offset = 0xff;
1026         idt82p33->tod_write_overhead_ns = 0;
1027         idt82p33->calculate_overhead_flag = 0;
1028         idt82p33->pll_mask = DEFAULT_PLL_MASK;
1029         idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
1030         idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
1031
1032         mutex_lock(&idt82p33->reg_lock);
1033
1034         err = idt82p33_load_firmware(idt82p33);
1035
1036         if (err)
1037                 dev_warn(&idt82p33->client->dev,
1038                          "loading firmware failed with %d\n", err);
1039
1040         if (idt82p33->pll_mask) {
1041                 for (i = 0; i < MAX_PHC_PLL; i++) {
1042                         if (idt82p33->pll_mask & (1 << i)) {
1043                                 err = idt82p33_enable_channel(idt82p33, i);
1044                                 if (err) {
1045                                         dev_err(&idt82p33->client->dev,
1046                                                 "Failed in %s with err %d!\n",
1047                                                 __func__, err);
1048                                         break;
1049                                 }
1050                         }
1051                 }
1052         } else {
1053                 dev_err(&idt82p33->client->dev,
1054                         "no PLLs flagged as PHCs, nothing to do\n");
1055                 err = -ENODEV;
1056         }
1057
1058         mutex_unlock(&idt82p33->reg_lock);
1059
1060         if (err) {
1061                 idt82p33_ptp_clock_unregister_all(idt82p33);
1062                 return err;
1063         }
1064
1065         i2c_set_clientdata(client, idt82p33);
1066
1067         return 0;
1068 }
1069
1070 static int idt82p33_remove(struct i2c_client *client)
1071 {
1072         struct idt82p33 *idt82p33 = i2c_get_clientdata(client);
1073
1074         idt82p33_ptp_clock_unregister_all(idt82p33);
1075         mutex_destroy(&idt82p33->reg_lock);
1076
1077         return 0;
1078 }
1079
1080 #ifdef CONFIG_OF
1081 static const struct of_device_id idt82p33_dt_id[] = {
1082         { .compatible = "idt,82p33810" },
1083         { .compatible = "idt,82p33813" },
1084         { .compatible = "idt,82p33814" },
1085         { .compatible = "idt,82p33831" },
1086         { .compatible = "idt,82p33910" },
1087         { .compatible = "idt,82p33913" },
1088         { .compatible = "idt,82p33914" },
1089         { .compatible = "idt,82p33931" },
1090         {},
1091 };
1092 MODULE_DEVICE_TABLE(of, idt82p33_dt_id);
1093 #endif
1094
1095 static const struct i2c_device_id idt82p33_i2c_id[] = {
1096         { "idt82p33810", },
1097         { "idt82p33813", },
1098         { "idt82p33814", },
1099         { "idt82p33831", },
1100         { "idt82p33910", },
1101         { "idt82p33913", },
1102         { "idt82p33914", },
1103         { "idt82p33931", },
1104         {},
1105 };
1106 MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id);
1107
1108 static struct i2c_driver idt82p33_driver = {
1109         .driver = {
1110                 .of_match_table = of_match_ptr(idt82p33_dt_id),
1111                 .name           = "idt82p33",
1112         },
1113         .probe          = idt82p33_probe,
1114         .remove         = idt82p33_remove,
1115         .id_table       = idt82p33_i2c_id,
1116 };
1117
1118 module_i2c_driver(idt82p33_driver);