1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
8 #ifndef PTP_IDTCLOCKMATRIX_H
9 #define PTP_IDTCLOCKMATRIX_H
11 #include <linux/ktime.h>
12 #include <linux/mfd/idt8a340_reg.h>
13 #include <linux/regmap.h>
15 #define FW_FILENAME "idtcm.bin"
19 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
21 #define TOD_MASK_ADDR (0xFFA5)
22 #define DEFAULT_TOD_MASK (0x04)
24 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
25 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
27 #define TOD0_PTP_PLL_ADDR (0xFFA8)
28 #define TOD1_PTP_PLL_ADDR (0xFFA9)
29 #define TOD2_PTP_PLL_ADDR (0xFFAA)
30 #define TOD3_PTP_PLL_ADDR (0xFFAB)
32 #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0)
33 #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2)
34 #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4)
35 #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6)
37 #define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
38 #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
39 #define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
40 #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
42 #define DEFAULT_TOD0_PTP_PLL (0)
43 #define DEFAULT_TOD1_PTP_PLL (1)
44 #define DEFAULT_TOD2_PTP_PLL (2)
45 #define DEFAULT_TOD3_PTP_PLL (3)
47 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000)
48 #define PHASE_PULL_IN_THRESHOLD_NS (15000)
49 #define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
50 #define TOD_BYTE_COUNT (11)
52 #define LOCK_TIMEOUT_MS (2000)
53 #define LOCK_POLL_INTERVAL_MS (10)
55 #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
57 #define IDTCM_MAX_WRITE_COUNT (512)
59 #define PHASE_PULL_IN_MAX_PPB (144000)
60 #define PHASE_PULL_IN_MIN_THRESHOLD_NS (2)
63 * Return register address based on passed in firmware version
65 #define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
75 PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN,
76 PTP_PLL_MODE_WRITE_PHASE,
77 PTP_PLL_MODE_UNSUPPORTED,
78 PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED,
83 struct idtcm_channel {
84 struct ptp_clock_info caps;
85 struct ptp_clock *ptp_clock;
91 u16 dpll_phase_pull_in;
97 enum ptp_pll_mode mode;
98 int (*configure_write_frequency)(struct idtcm_channel *channel);
99 int (*configure_write_phase)(struct idtcm_channel *channel);
100 int (*do_phase_pull_in)(struct idtcm_channel *channel,
101 s32 offset_ns, u32 max_ffo_ppb);
102 s32 current_freq_scaled_ppm;
105 /* last input trigger for extts */
112 struct idtcm_channel channel[MAX_TOD];
116 enum fw_version fw_ver;
117 /* Polls for external time stamps */
119 struct delayed_work extts_work;
120 /* Remember the ptp channel to report extts */
121 struct idtcm_channel *event_channel[MAX_TOD];
122 /* Mutex to protect operations from being interrupted */
125 struct regmap *regmap;
126 /* Overhead calculation for adjtime */
127 u8 calculate_overhead_flag;
128 s64 tod_write_overhead_ns;
139 #endif /* PTP_IDTCLOCKMATRIX_H */