1 // SPDX-License-Identifier: GPL-2.0+
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
8 #include <linux/firmware.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/timekeeping.h>
16 #include <linux/string.h>
18 #include "ptp_private.h"
19 #include "ptp_clockmatrix.h"
21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24 MODULE_VERSION("1.0");
25 MODULE_LICENSE("GPL");
28 * The name of the firmware file to be loaded
29 * over-rides any automatic selection
31 static char *firmware;
32 module_param(firmware, charp, 0);
34 #define SETTIME_CORRECTION (0)
36 static long set_write_phase_ready(struct ptp_clock_info *ptp)
38 struct idtcm_channel *channel =
39 container_of(ptp, struct idtcm_channel, caps);
41 channel->write_phase_ready = 1;
46 static int char_array_to_timespec(u8 *buf,
48 struct timespec64 *ts)
54 if (count < TOD_BYTE_COUNT)
57 /* Sub-nanoseconds are in buf[0]. */
59 for (i = 0; i < 3; i++) {
65 for (i = 0; i < 5; i++) {
76 static int timespec_to_char_array(struct timespec64 const *ts,
84 if (count < TOD_BYTE_COUNT)
90 /* Sub-nanoseconds are in buf[0]. */
92 for (i = 1; i < 5; i++) {
97 for (i = 5; i < TOD_BYTE_COUNT; i++) {
106 static int idtcm_strverscmp(const char *version1, const char *version2)
111 if (sscanf(version1, "%hhu.%hhu.%hhu",
112 &ver1[0], &ver1[1], &ver1[2]) != 3)
114 if (sscanf(version2, "%hhu.%hhu.%hhu",
115 &ver2[0], &ver2[1], &ver2[2]) != 3)
118 for (i = 0; i < 3; i++) {
119 if (ver1[i] > ver2[i])
121 if (ver1[i] < ver2[i])
128 static int idtcm_xfer_read(struct idtcm *idtcm,
133 struct i2c_client *client = idtcm->client;
134 struct i2c_msg msg[2];
136 char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
138 msg[0].addr = client->addr;
141 msg[0].buf = ®addr;
143 msg[1].addr = client->addr;
144 msg[1].flags = I2C_M_RD;
148 cnt = i2c_transfer(client->adapter, msg, 2);
151 dev_err(&client->dev,
157 } else if (cnt != 2) {
158 dev_err(&client->dev,
159 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
166 static int idtcm_xfer_write(struct idtcm *idtcm,
171 struct i2c_client *client = idtcm->client;
172 /* we add 1 byte for device register */
173 u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
175 char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
177 if (count > IDTCM_MAX_WRITE_COUNT)
181 memcpy(&msg[1], buf, count);
183 cnt = i2c_master_send(client, msg, count + 1);
186 dev_err(&client->dev,
197 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
202 if (idtcm->page_offset == val)
210 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
213 idtcm->page_offset = 0xff;
214 dev_err(&idtcm->client->dev, "failed to set page offset\n");
216 idtcm->page_offset = val;
222 static int _idtcm_rdwr(struct idtcm *idtcm,
232 hi = (regaddr >> 8) & 0xff;
235 err = idtcm_page_offset(idtcm, hi);
241 return idtcm_xfer_write(idtcm, lo, buf, count);
243 return idtcm_xfer_read(idtcm, lo, buf, count);
246 static int idtcm_read(struct idtcm *idtcm,
252 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
255 static int idtcm_write(struct idtcm *idtcm,
261 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
264 static int _idtcm_gettime(struct idtcm_channel *channel,
265 struct timespec64 *ts)
267 struct idtcm *idtcm = channel->idtcm;
268 u8 buf[TOD_BYTE_COUNT];
273 err = idtcm_read(idtcm, channel->tod_read_primary,
274 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
278 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
279 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
280 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
282 err = idtcm_write(idtcm, channel->tod_read_primary,
283 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
287 /* wait trigger to be 0 */
288 while (trigger & TOD_READ_TRIGGER_MASK) {
290 if (idtcm->calculate_overhead_flag)
291 idtcm->start_time = ktime_get_raw();
293 err = idtcm_read(idtcm, channel->tod_read_primary,
294 TOD_READ_PRIMARY_CMD, &trigger,
304 err = idtcm_read(idtcm, channel->tod_read_primary,
305 TOD_READ_PRIMARY, buf, sizeof(buf));
310 err = char_array_to_timespec(buf, sizeof(buf), ts);
315 static int _sync_pll_output(struct idtcm *idtcm,
327 if ((qn == 0) && (qn_plus_1 == 0))
332 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
333 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
336 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
337 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
340 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
341 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
344 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
345 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
348 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
349 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
352 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
353 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
356 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
357 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
360 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
361 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
367 val = SYNCTRL1_MASTER_SYNC_RST;
369 /* Place master sync in reset */
370 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
374 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
378 /* Set sync trigger mask */
379 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
382 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
385 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
387 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
391 /* PLL5 can have OUT8 as second additional output. */
392 if ((pll == 5) && (qn_plus_1 != 0)) {
393 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
394 &temp, sizeof(temp));
398 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
400 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
401 &temp, sizeof(temp));
405 temp |= Q9_TO_Q8_SYNC_TRIG;
407 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
408 &temp, sizeof(temp));
413 /* PLL6 can have OUT11 as second additional output. */
414 if ((pll == 6) && (qn_plus_1 != 0)) {
415 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
416 &temp, sizeof(temp));
420 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
422 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
423 &temp, sizeof(temp));
427 temp |= Q10_TO_Q11_SYNC_TRIG;
429 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
430 &temp, sizeof(temp));
435 /* Place master sync out of reset */
436 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
437 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
442 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
448 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
451 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
454 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
457 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
466 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
468 struct idtcm *idtcm = channel->idtcm;
479 u16 output_mask = channel->output_mask;
481 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
485 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
486 &temp, sizeof(temp));
490 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
491 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
494 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
495 &temp, sizeof(temp));
499 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
500 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
503 for (pll = 0; pll < 8; pll++) {
508 /* First 4 pll has 2 outputs */
509 qn = output_mask & 0x1;
510 output_mask = output_mask >> 1;
511 qn_plus_1 = output_mask & 0x1;
512 output_mask = output_mask >> 1;
513 } else if (pll == 4) {
515 qn = output_mask & 0x1;
516 output_mask = output_mask >> 1;
518 } else if (pll == 5) {
520 qn_plus_1 = output_mask & 0x1;
521 output_mask = output_mask >> 1;
523 qn = output_mask & 0x1;
524 output_mask = output_mask >> 1;
525 } else if (pll == 6) {
526 qn = output_mask & 0x1;
527 output_mask = output_mask >> 1;
529 qn_plus_1 = output_mask & 0x1;
530 output_mask = output_mask >> 1;
532 } else if (pll == 7) {
533 if (out11_mux == 0) {
534 qn = output_mask & 0x1;
535 output_mask = output_mask >> 1;
539 if ((qn != 0) || (qn_plus_1 != 0))
540 err = _sync_pll_output(idtcm, pll, sync_src, qn,
550 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
551 struct timespec64 const *ts,
552 enum hw_tod_write_trig_sel wr_trig)
554 struct idtcm *idtcm = channel->idtcm;
556 u8 buf[TOD_BYTE_COUNT];
559 struct timespec64 local_ts = *ts;
560 s64 total_overhead_ns;
562 /* Configure HW TOD write trigger. */
563 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
570 cmd |= wr_trig | 0x08;
572 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
578 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
580 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
585 err = idtcm_write(idtcm, channel->hw_dpll_n,
586 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
592 /* ARM HW TOD write trigger. */
595 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
598 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
600 if (idtcm->calculate_overhead_flag) {
601 /* Assumption: I2C @ 400KHz */
602 total_overhead_ns = ktime_to_ns(ktime_get_raw()
604 + idtcm->tod_write_overhead_ns
605 + SETTIME_CORRECTION;
607 timespec64_add_ns(&local_ts, total_overhead_ns);
609 idtcm->calculate_overhead_flag = 0;
612 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
617 err = idtcm_write(idtcm, channel->hw_dpll_n,
618 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
624 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
625 struct timespec64 const *ts,
626 enum scsr_tod_write_trig_sel wr_trig,
627 enum scsr_tod_write_type_sel wr_type)
629 struct idtcm *idtcm = channel->idtcm;
630 unsigned char buf[TOD_BYTE_COUNT], cmd;
631 struct timespec64 local_ts = *ts;
634 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
636 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
641 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
646 /* Trigger the write operation. */
647 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
652 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
653 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
654 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
655 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
657 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
662 /* Wait for the operation to complete. */
664 /* pps trigger takes up to 1 sec to complete */
665 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
668 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
677 dev_err(&idtcm->client->dev,
678 "Timed out waiting for the write counter\n");
686 static int _idtcm_settime(struct idtcm_channel *channel,
687 struct timespec64 const *ts,
688 enum hw_tod_write_trig_sel wr_trig)
690 struct idtcm *idtcm = channel->idtcm;
695 err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
700 /* Wait for the operation to complete. */
701 for (i = 0; i < 10000; i++) {
702 err = idtcm_read(idtcm, channel->hw_dpll_n,
703 HW_DPLL_TOD_CTRL_1, &trig_sel,
709 if (trig_sel == 0x4a)
716 dev_err(&idtcm->client->dev,
717 "Failed at line %d in func %s!\n",
723 return idtcm_sync_pps_output(channel);
726 static int _idtcm_settime_v487(struct idtcm_channel *channel,
727 struct timespec64 const *ts,
728 enum scsr_tod_write_type_sel wr_type)
730 return _idtcm_set_dpll_scsr_tod(channel, ts,
731 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
735 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
740 struct idtcm *idtcm = channel->idtcm;
744 for (i = 0; i < 4; i++) {
745 buf[i] = 0xff & (offset_ns);
749 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
755 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
760 struct idtcm *idtcm = channel->idtcm;
764 if (max_ffo_ppb & 0xff000000)
767 for (i = 0; i < 3; i++) {
768 buf[i] = 0xff & (max_ffo_ppb);
772 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
773 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
778 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
781 struct idtcm *idtcm = channel->idtcm;
785 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
793 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
794 PULL_IN_CTRL, &buf, sizeof(buf));
802 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
808 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
813 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
818 err = idtcm_start_phase_pull_in(channel);
823 static int set_tod_write_overhead(struct idtcm_channel *channel)
825 struct idtcm *idtcm = channel->idtcm;
834 char buf[TOD_BYTE_COUNT] = {0};
836 /* Set page offset */
837 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
840 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
842 start = ktime_get_raw();
844 err = idtcm_write(idtcm, channel->hw_dpll_n,
845 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
850 stop = ktime_get_raw();
852 current_ns = ktime_to_ns(stop - start);
855 lowest_ns = current_ns;
857 if (current_ns < lowest_ns)
858 lowest_ns = current_ns;
862 idtcm->tod_write_overhead_ns = lowest_ns;
867 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
870 struct idtcm *idtcm = channel->idtcm;
871 struct timespec64 ts;
874 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
875 err = idtcm_do_phase_pull_in(channel, delta, 0);
877 idtcm->calculate_overhead_flag = 1;
879 err = set_tod_write_overhead(channel);
884 err = _idtcm_gettime(channel, &ts);
889 now = timespec64_to_ns(&ts);
892 ts = ns_to_timespec64(now);
894 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
900 static int idtcm_state_machine_reset(struct idtcm *idtcm)
903 u8 byte = SM_RESET_CMD;
905 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
908 msleep_interruptible(POST_SM_RESET_DELAY_MS);
913 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
915 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
918 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
923 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
925 *product_id = (buf[1] << 8) | buf[0];
930 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
935 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
942 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
944 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
947 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
949 return idtcm_read(idtcm,
956 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
959 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
960 config_select, sizeof(u8));
963 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
968 case TOD0_OUT_ALIGN_MASK_ADDR:
969 SET_U16_LSB(idtcm->channel[0].output_mask, val);
971 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
972 SET_U16_MSB(idtcm->channel[0].output_mask, val);
974 case TOD1_OUT_ALIGN_MASK_ADDR:
975 SET_U16_LSB(idtcm->channel[1].output_mask, val);
977 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
978 SET_U16_MSB(idtcm->channel[1].output_mask, val);
980 case TOD2_OUT_ALIGN_MASK_ADDR:
981 SET_U16_LSB(idtcm->channel[2].output_mask, val);
983 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
984 SET_U16_MSB(idtcm->channel[2].output_mask, val);
986 case TOD3_OUT_ALIGN_MASK_ADDR:
987 SET_U16_LSB(idtcm->channel[3].output_mask, val);
989 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
990 SET_U16_MSB(idtcm->channel[3].output_mask, val);
993 err = -EFAULT; /* Bad address */;
1000 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1002 if (index >= MAX_TOD) {
1003 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
1007 if (pll >= MAX_PLL) {
1008 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
1012 idtcm->channel[index].pll = pll;
1017 static int check_and_set_masks(struct idtcm *idtcm,
1025 if ((val & 0xf0) || !(val & 0x0f)) {
1026 dev_err(&idtcm->client->dev,
1027 "Invalid TOD mask 0x%hhx\n", val);
1030 idtcm->tod_mask = val;
1033 case TOD0_PTP_PLL_ADDR:
1034 err = set_tod_ptp_pll(idtcm, 0, val);
1036 case TOD1_PTP_PLL_ADDR:
1037 err = set_tod_ptp_pll(idtcm, 1, val);
1039 case TOD2_PTP_PLL_ADDR:
1040 err = set_tod_ptp_pll(idtcm, 2, val);
1042 case TOD3_PTP_PLL_ADDR:
1043 err = set_tod_ptp_pll(idtcm, 3, val);
1046 err = set_pll_output_mask(idtcm, regaddr, val);
1053 static void display_pll_and_masks(struct idtcm *idtcm)
1058 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
1060 for (i = 0; i < MAX_TOD; i++) {
1063 if (mask & idtcm->tod_mask)
1064 dev_dbg(&idtcm->client->dev,
1065 "TOD%d pll = %d output_mask = 0x%04x\n",
1066 i, idtcm->channel[i].pll,
1067 idtcm->channel[i].output_mask);
1071 static int idtcm_load_firmware(struct idtcm *idtcm,
1074 char fname[128] = FW_FILENAME;
1075 const struct firmware *fw;
1076 struct idtcm_fwrc *rec;
1083 if (firmware) /* module parameter */
1084 snprintf(fname, sizeof(fname), "%s", firmware);
1086 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
1088 err = request_firmware(&fw, fname, dev);
1091 dev_err(&idtcm->client->dev,
1092 "Failed at line %d in func %s!\n",
1098 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1100 rec = (struct idtcm_fwrc *) fw->data;
1103 idtcm_state_machine_reset(idtcm);
1105 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1107 if (rec->reserved) {
1108 dev_err(&idtcm->client->dev,
1109 "bad firmware, reserved field non-zero\n");
1112 regaddr = rec->hiaddr << 8;
1113 regaddr |= rec->loaddr;
1116 loaddr = rec->loaddr;
1120 err = check_and_set_masks(idtcm, regaddr, val);
1123 if (err != -EINVAL) {
1126 /* Top (status registers) and bottom are read-only */
1127 if ((regaddr < GPIO_USER_CONTROL)
1128 || (regaddr >= SCRATCH))
1131 /* Page size 128, last 4 bytes of page skipped */
1132 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
1136 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1143 display_pll_and_masks(idtcm);
1146 release_firmware(fw);
1150 static int idtcm_output_enable(struct idtcm_channel *channel,
1151 bool enable, unsigned int outn)
1153 struct idtcm *idtcm = channel->idtcm;
1157 err = idtcm_read(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1158 OUT_CTRL_1, &val, sizeof(val));
1164 val |= SQUELCH_DISABLE;
1166 val &= ~SQUELCH_DISABLE;
1168 return idtcm_write(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1169 OUT_CTRL_1, &val, sizeof(val));
1172 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1179 mask = channel->output_mask;
1186 err = idtcm_output_enable(channel, enable, outn);
1199 static int idtcm_perout_enable(struct idtcm_channel *channel,
1201 struct ptp_perout_request *perout)
1203 unsigned int flags = perout->flags;
1205 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1206 return idtcm_output_mask_enable(channel, enable);
1208 /* Enable/disable individual output instead */
1209 return idtcm_output_enable(channel, enable, perout->index);
1212 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1213 enum pll_mode pll_mode)
1215 struct idtcm *idtcm = channel->idtcm;
1219 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1220 &dpll_mode, sizeof(dpll_mode));
1224 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1226 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1228 channel->pll_mode = pll_mode;
1230 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1231 &dpll_mode, sizeof(dpll_mode));
1238 /* PTP Hardware Clock interface */
1241 * @brief Maximum absolute value for write phase offset in picoseconds
1243 * Destination signed register is 32-bit register in resolution of 50ps
1245 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1247 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1249 struct idtcm *idtcm = channel->idtcm;
1257 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1259 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1264 channel->write_phase_ready = 0;
1266 ptp_schedule_worker(channel->ptp_clock,
1267 msecs_to_jiffies(WR_PHASE_SETUP_MS));
1270 if (!channel->write_phase_ready)
1273 offset_ps = (s64)delta_ns * 1000;
1276 * Check for 32-bit signed max * 50:
1278 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1280 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1281 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1282 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1283 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1285 phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1);
1287 for (i = 0; i < 4; i++) {
1288 buf[i] = phase_50ps & 0xff;
1292 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1298 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1300 struct idtcm *idtcm = channel->idtcm;
1307 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1308 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1314 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1323 * FCW = -------------
1326 if (scaled_ppm < 0) {
1328 scaled_ppm = -scaled_ppm;
1331 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1332 fcw = scaled_ppm * 244140625ULL;
1334 fcw = div_u64(fcw, 1776);
1339 for (i = 0; i < 6; i++) {
1340 buf[i] = fcw & 0xff;
1344 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1350 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1352 struct idtcm_channel *channel =
1353 container_of(ptp, struct idtcm_channel, caps);
1354 struct idtcm *idtcm = channel->idtcm;
1357 mutex_lock(&idtcm->reg_lock);
1359 err = _idtcm_gettime(channel, ts);
1362 dev_err(&idtcm->client->dev,
1363 "Failed at line %d in func %s!\n",
1367 mutex_unlock(&idtcm->reg_lock);
1372 static int idtcm_settime(struct ptp_clock_info *ptp,
1373 const struct timespec64 *ts)
1375 struct idtcm_channel *channel =
1376 container_of(ptp, struct idtcm_channel, caps);
1377 struct idtcm *idtcm = channel->idtcm;
1380 mutex_lock(&idtcm->reg_lock);
1382 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
1385 dev_err(&idtcm->client->dev,
1386 "Failed at line %d in func %s!\n",
1390 mutex_unlock(&idtcm->reg_lock);
1395 static int idtcm_settime_v487(struct ptp_clock_info *ptp,
1396 const struct timespec64 *ts)
1398 struct idtcm_channel *channel =
1399 container_of(ptp, struct idtcm_channel, caps);
1400 struct idtcm *idtcm = channel->idtcm;
1403 mutex_lock(&idtcm->reg_lock);
1405 err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1408 dev_err(&idtcm->client->dev,
1409 "Failed at line %d in func %s!\n",
1413 mutex_unlock(&idtcm->reg_lock);
1418 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1420 struct idtcm_channel *channel =
1421 container_of(ptp, struct idtcm_channel, caps);
1422 struct idtcm *idtcm = channel->idtcm;
1425 mutex_lock(&idtcm->reg_lock);
1427 err = _idtcm_adjtime(channel, delta);
1430 dev_err(&idtcm->client->dev,
1431 "Failed at line %d in func %s!\n",
1435 mutex_unlock(&idtcm->reg_lock);
1440 static int idtcm_adjtime_v487(struct ptp_clock_info *ptp, s64 delta)
1442 struct idtcm_channel *channel =
1443 container_of(ptp, struct idtcm_channel, caps);
1444 struct idtcm *idtcm = channel->idtcm;
1445 struct timespec64 ts;
1446 enum scsr_tod_write_type_sel type;
1449 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_V487) {
1450 err = idtcm_do_phase_pull_in(channel, delta, 0);
1452 dev_err(&idtcm->client->dev,
1453 "Failed at line %d in func %s!\n",
1460 ts = ns_to_timespec64(delta);
1461 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1463 ts = ns_to_timespec64(-delta);
1464 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1467 mutex_lock(&idtcm->reg_lock);
1469 err = _idtcm_settime_v487(channel, &ts, type);
1472 dev_err(&idtcm->client->dev,
1473 "Failed at line %d in func %s!\n",
1477 mutex_unlock(&idtcm->reg_lock);
1482 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1484 struct idtcm_channel *channel =
1485 container_of(ptp, struct idtcm_channel, caps);
1487 struct idtcm *idtcm = channel->idtcm;
1491 mutex_lock(&idtcm->reg_lock);
1493 err = _idtcm_adjphase(channel, delta);
1496 dev_err(&idtcm->client->dev,
1497 "Failed at line %d in func %s!\n",
1501 mutex_unlock(&idtcm->reg_lock);
1506 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1508 struct idtcm_channel *channel =
1509 container_of(ptp, struct idtcm_channel, caps);
1511 struct idtcm *idtcm = channel->idtcm;
1515 mutex_lock(&idtcm->reg_lock);
1517 err = _idtcm_adjfine(channel, scaled_ppm);
1520 dev_err(&idtcm->client->dev,
1521 "Failed at line %d in func %s!\n",
1525 mutex_unlock(&idtcm->reg_lock);
1530 static int idtcm_enable(struct ptp_clock_info *ptp,
1531 struct ptp_clock_request *rq, int on)
1535 struct idtcm_channel *channel =
1536 container_of(ptp, struct idtcm_channel, caps);
1539 case PTP_CLK_REQ_PEROUT:
1541 err = idtcm_perout_enable(channel, false, &rq->perout);
1543 dev_err(&channel->idtcm->client->dev,
1544 "Failed at line %d in func %s!\n",
1550 /* Only accept a 1-PPS aligned to the second. */
1551 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1552 rq->perout.period.nsec)
1555 err = idtcm_perout_enable(channel, true, &rq->perout);
1557 dev_err(&channel->idtcm->client->dev,
1558 "Failed at line %d in func %s!\n",
1569 static int _enable_pll_tod_sync(struct idtcm *idtcm,
1578 u16 out0 = 0, out1 = 0;
1580 if ((qn == 0) && (qn_plus_1 == 0))
1641 * Enable OUTPUT OUT_SYNC.
1644 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1649 val &= ~OUT_SYNC_DISABLE;
1651 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1658 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1663 val &= ~OUT_SYNC_DISABLE;
1665 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1671 /* enable dpll sync tod pps, must be set before dpll_mode */
1672 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1676 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1677 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1680 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1683 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1685 struct idtcm *idtcm = channel->idtcm;
1693 u16 output_mask = channel->output_mask;
1699 * set tod_out_sync_enable to 0.
1701 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1705 cfg &= ~TOD_OUT_SYNC_ENABLE;
1707 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1711 switch (channel->tod_n) {
1728 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1729 &temp, sizeof(temp));
1733 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1734 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1737 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1738 &temp, sizeof(temp));
1742 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1743 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1746 for (pll = 0; pll < 8; pll++) {
1751 /* First 4 pll has 2 outputs */
1752 qn = output_mask & 0x1;
1753 output_mask = output_mask >> 1;
1754 qn_plus_1 = output_mask & 0x1;
1755 output_mask = output_mask >> 1;
1756 } else if (pll == 4) {
1757 if (out8_mux == 0) {
1758 qn = output_mask & 0x1;
1759 output_mask = output_mask >> 1;
1761 } else if (pll == 5) {
1763 qn_plus_1 = output_mask & 0x1;
1764 output_mask = output_mask >> 1;
1766 qn = output_mask & 0x1;
1767 output_mask = output_mask >> 1;
1768 } else if (pll == 6) {
1769 qn = output_mask & 0x1;
1770 output_mask = output_mask >> 1;
1772 qn_plus_1 = output_mask & 0x1;
1773 output_mask = output_mask >> 1;
1775 } else if (pll == 7) {
1776 if (out11_mux == 0) {
1777 qn = output_mask & 0x1;
1778 output_mask = output_mask >> 1;
1782 if ((qn != 0) || (qn_plus_1 != 0))
1783 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1793 static int idtcm_enable_tod(struct idtcm_channel *channel)
1795 struct idtcm *idtcm = channel->idtcm;
1796 struct timespec64 ts = {0, 0};
1801 * Start the TOD clock ticking.
1803 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1809 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1813 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
1816 static void idtcm_display_version_info(struct idtcm *idtcm)
1824 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n";
1826 idtcm_read_major_release(idtcm, &major);
1827 idtcm_read_minor_release(idtcm, &minor);
1828 idtcm_read_hotfix_release(idtcm, &hotfix);
1830 idtcm_read_product_id(idtcm, &product_id);
1831 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1833 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1835 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1836 major, minor, hotfix);
1838 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
1839 product_id, hw_rev_id, config_select);
1842 static const struct ptp_clock_info idtcm_caps_v487 = {
1843 .owner = THIS_MODULE,
1846 .adjphase = &idtcm_adjphase,
1847 .adjfine = &idtcm_adjfine,
1848 .adjtime = &idtcm_adjtime_v487,
1849 .gettime64 = &idtcm_gettime,
1850 .settime64 = &idtcm_settime_v487,
1851 .enable = &idtcm_enable,
1852 .do_aux_work = &set_write_phase_ready,
1855 static const struct ptp_clock_info idtcm_caps = {
1856 .owner = THIS_MODULE,
1859 .adjphase = &idtcm_adjphase,
1860 .adjfine = &idtcm_adjfine,
1861 .adjtime = &idtcm_adjtime,
1862 .gettime64 = &idtcm_gettime,
1863 .settime64 = &idtcm_settime,
1864 .enable = &idtcm_enable,
1865 .do_aux_work = &set_write_phase_ready,
1868 static int configure_channel_pll(struct idtcm_channel *channel)
1872 switch (channel->pll) {
1874 channel->dpll_freq = DPLL_FREQ_0;
1875 channel->dpll_n = DPLL_0;
1876 channel->hw_dpll_n = HW_DPLL_0;
1877 channel->dpll_phase = DPLL_PHASE_0;
1878 channel->dpll_ctrl_n = DPLL_CTRL_0;
1879 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1882 channel->dpll_freq = DPLL_FREQ_1;
1883 channel->dpll_n = DPLL_1;
1884 channel->hw_dpll_n = HW_DPLL_1;
1885 channel->dpll_phase = DPLL_PHASE_1;
1886 channel->dpll_ctrl_n = DPLL_CTRL_1;
1887 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1890 channel->dpll_freq = DPLL_FREQ_2;
1891 channel->dpll_n = DPLL_2;
1892 channel->hw_dpll_n = HW_DPLL_2;
1893 channel->dpll_phase = DPLL_PHASE_2;
1894 channel->dpll_ctrl_n = DPLL_CTRL_2;
1895 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
1898 channel->dpll_freq = DPLL_FREQ_3;
1899 channel->dpll_n = DPLL_3;
1900 channel->hw_dpll_n = HW_DPLL_3;
1901 channel->dpll_phase = DPLL_PHASE_3;
1902 channel->dpll_ctrl_n = DPLL_CTRL_3;
1903 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
1906 channel->dpll_freq = DPLL_FREQ_4;
1907 channel->dpll_n = DPLL_4;
1908 channel->hw_dpll_n = HW_DPLL_4;
1909 channel->dpll_phase = DPLL_PHASE_4;
1910 channel->dpll_ctrl_n = DPLL_CTRL_4;
1911 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
1914 channel->dpll_freq = DPLL_FREQ_5;
1915 channel->dpll_n = DPLL_5;
1916 channel->hw_dpll_n = HW_DPLL_5;
1917 channel->dpll_phase = DPLL_PHASE_5;
1918 channel->dpll_ctrl_n = DPLL_CTRL_5;
1919 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
1922 channel->dpll_freq = DPLL_FREQ_6;
1923 channel->dpll_n = DPLL_6;
1924 channel->hw_dpll_n = HW_DPLL_6;
1925 channel->dpll_phase = DPLL_PHASE_6;
1926 channel->dpll_ctrl_n = DPLL_CTRL_6;
1927 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
1930 channel->dpll_freq = DPLL_FREQ_7;
1931 channel->dpll_n = DPLL_7;
1932 channel->hw_dpll_n = HW_DPLL_7;
1933 channel->dpll_phase = DPLL_PHASE_7;
1934 channel->dpll_ctrl_n = DPLL_CTRL_7;
1935 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
1944 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
1946 struct idtcm_channel *channel;
1949 if (!(index < MAX_TOD))
1952 channel = &idtcm->channel[index];
1954 /* Set pll addresses */
1955 err = configure_channel_pll(channel);
1959 /* Set tod addresses */
1962 channel->tod_read_primary = TOD_READ_PRIMARY_0;
1963 channel->tod_write = TOD_WRITE_0;
1964 channel->tod_n = TOD_0;
1967 channel->tod_read_primary = TOD_READ_PRIMARY_1;
1968 channel->tod_write = TOD_WRITE_1;
1969 channel->tod_n = TOD_1;
1972 channel->tod_read_primary = TOD_READ_PRIMARY_2;
1973 channel->tod_write = TOD_WRITE_2;
1974 channel->tod_n = TOD_2;
1977 channel->tod_read_primary = TOD_READ_PRIMARY_3;
1978 channel->tod_write = TOD_WRITE_3;
1979 channel->tod_n = TOD_3;
1985 channel->idtcm = idtcm;
1987 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
1988 channel->caps = idtcm_caps_v487;
1990 channel->caps = idtcm_caps;
1992 snprintf(channel->caps.name, sizeof(channel->caps.name),
1993 "IDT CM TOD%u", index);
1995 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) {
1996 err = idtcm_enable_tod_sync(channel);
1998 dev_err(&idtcm->client->dev,
1999 "Failed at line %d in func %s!\n",
2006 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
2008 dev_err(&idtcm->client->dev,
2009 "Failed at line %d in func %s!\n",
2015 err = idtcm_enable_tod(channel);
2017 dev_err(&idtcm->client->dev,
2018 "Failed at line %d in func %s!\n",
2024 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2026 if (IS_ERR(channel->ptp_clock)) {
2027 err = PTR_ERR(channel->ptp_clock);
2028 channel->ptp_clock = NULL;
2032 if (!channel->ptp_clock)
2035 channel->write_phase_ready = 0;
2037 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2038 index, channel->ptp_clock->index);
2043 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2046 struct idtcm_channel *channel;
2048 for (i = 0; i < MAX_TOD; i++) {
2050 channel = &idtcm->channel[i];
2052 if (channel->ptp_clock)
2053 ptp_clock_unregister(channel->ptp_clock);
2057 static void set_default_masks(struct idtcm *idtcm)
2059 idtcm->tod_mask = DEFAULT_TOD_MASK;
2061 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2062 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2063 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2064 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2066 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2067 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2068 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2069 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2072 static int idtcm_probe(struct i2c_client *client,
2073 const struct i2c_device_id *id)
2075 struct idtcm *idtcm;
2078 char *fmt = "Failed at %d in line %s with channel output %d!\n";
2080 /* Unused for now */
2083 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2088 idtcm->client = client;
2089 idtcm->page_offset = 0xff;
2090 idtcm->calculate_overhead_flag = 0;
2092 set_default_masks(idtcm);
2094 mutex_init(&idtcm->reg_lock);
2095 mutex_lock(&idtcm->reg_lock);
2097 idtcm_display_version_info(idtcm);
2099 err = idtcm_load_firmware(idtcm, &client->dev);
2102 dev_warn(&idtcm->client->dev,
2103 "loading firmware failed with %d\n", err);
2105 if (idtcm->tod_mask) {
2106 for (i = 0; i < MAX_TOD; i++) {
2107 if (idtcm->tod_mask & (1 << i)) {
2108 err = idtcm_enable_channel(idtcm, i);
2110 dev_err(&idtcm->client->dev,
2120 dev_err(&idtcm->client->dev,
2121 "no PLLs flagged as PHCs, nothing to do\n");
2125 mutex_unlock(&idtcm->reg_lock);
2128 ptp_clock_unregister_all(idtcm);
2132 i2c_set_clientdata(client, idtcm);
2137 static int idtcm_remove(struct i2c_client *client)
2139 struct idtcm *idtcm = i2c_get_clientdata(client);
2141 ptp_clock_unregister_all(idtcm);
2143 mutex_destroy(&idtcm->reg_lock);
2149 static const struct of_device_id idtcm_dt_id[] = {
2150 { .compatible = "idt,8a34000" },
2151 { .compatible = "idt,8a34001" },
2152 { .compatible = "idt,8a34002" },
2153 { .compatible = "idt,8a34003" },
2154 { .compatible = "idt,8a34004" },
2155 { .compatible = "idt,8a34005" },
2156 { .compatible = "idt,8a34006" },
2157 { .compatible = "idt,8a34007" },
2158 { .compatible = "idt,8a34008" },
2159 { .compatible = "idt,8a34009" },
2160 { .compatible = "idt,8a34010" },
2161 { .compatible = "idt,8a34011" },
2162 { .compatible = "idt,8a34012" },
2163 { .compatible = "idt,8a34013" },
2164 { .compatible = "idt,8a34014" },
2165 { .compatible = "idt,8a34015" },
2166 { .compatible = "idt,8a34016" },
2167 { .compatible = "idt,8a34017" },
2168 { .compatible = "idt,8a34018" },
2169 { .compatible = "idt,8a34019" },
2170 { .compatible = "idt,8a34040" },
2171 { .compatible = "idt,8a34041" },
2172 { .compatible = "idt,8a34042" },
2173 { .compatible = "idt,8a34043" },
2174 { .compatible = "idt,8a34044" },
2175 { .compatible = "idt,8a34045" },
2176 { .compatible = "idt,8a34046" },
2177 { .compatible = "idt,8a34047" },
2178 { .compatible = "idt,8a34048" },
2179 { .compatible = "idt,8a34049" },
2182 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2185 static const struct i2c_device_id idtcm_i2c_id[] = {
2218 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2220 static struct i2c_driver idtcm_driver = {
2222 .of_match_table = of_match_ptr(idtcm_dt_id),
2225 .probe = idtcm_probe,
2226 .remove = idtcm_remove,
2227 .id_table = idtcm_i2c_id,
2230 module_i2c_driver(idtcm_driver);