1 // SPDX-License-Identifier: GPL-2.0+
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
8 #include <linux/firmware.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/timekeeping.h>
16 #include "ptp_private.h"
17 #include "ptp_clockmatrix.h"
19 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
20 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
21 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
22 MODULE_VERSION("1.0");
23 MODULE_LICENSE("GPL");
25 #define SETTIME_CORRECTION (0)
27 static int char_array_to_timespec(u8 *buf,
29 struct timespec64 *ts)
35 if (count < TOD_BYTE_COUNT)
38 /* Sub-nanoseconds are in buf[0]. */
40 for (i = 0; i < 3; i++) {
46 for (i = 0; i < 5; i++) {
57 static int timespec_to_char_array(struct timespec64 const *ts,
65 if (count < TOD_BYTE_COUNT)
71 /* Sub-nanoseconds are in buf[0]. */
73 for (i = 1; i < 5; i++) {
78 for (i = 5; i < TOD_BYTE_COUNT; i++) {
87 static int idtcm_xfer(struct idtcm *idtcm,
93 struct i2c_client *client = idtcm->client;
94 struct i2c_msg msg[2];
97 msg[0].addr = client->addr;
100 msg[0].buf = ®addr;
102 msg[1].addr = client->addr;
103 msg[1].flags = write ? 0 : I2C_M_RD;
107 cnt = i2c_transfer(client->adapter, msg, 2);
110 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
112 } else if (cnt != 2) {
113 dev_err(&client->dev,
114 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
121 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
126 if (idtcm->page_offset == val)
134 err = idtcm_xfer(idtcm, PAGE_ADDR, buf, sizeof(buf), 1);
137 dev_err(&idtcm->client->dev, "failed to set page offset\n");
139 idtcm->page_offset = val;
144 static int _idtcm_rdwr(struct idtcm *idtcm,
154 hi = (regaddr >> 8) & 0xff;
157 err = idtcm_page_offset(idtcm, hi);
162 err = idtcm_xfer(idtcm, lo, buf, count, write);
167 static int idtcm_read(struct idtcm *idtcm,
173 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
176 static int idtcm_write(struct idtcm *idtcm,
182 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
185 static int _idtcm_gettime(struct idtcm_channel *channel,
186 struct timespec64 *ts)
188 struct idtcm *idtcm = channel->idtcm;
189 u8 buf[TOD_BYTE_COUNT];
193 err = idtcm_read(idtcm, channel->tod_read_primary,
194 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
198 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
199 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
200 trigger |= TOD_READ_TRIGGER_MODE;
202 err = idtcm_write(idtcm, channel->tod_read_primary,
203 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
208 if (idtcm->calculate_overhead_flag)
209 idtcm->start_time = ktime_get_raw();
211 err = idtcm_read(idtcm, channel->tod_read_primary,
212 TOD_READ_PRIMARY, buf, sizeof(buf));
217 err = char_array_to_timespec(buf, sizeof(buf), ts);
222 static int _sync_pll_output(struct idtcm *idtcm,
233 if ((qn == 0) && (qn_plus_1 == 0))
238 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
239 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
242 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
243 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
246 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
247 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
250 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
251 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
254 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
255 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
258 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
259 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
262 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
263 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
266 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
267 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
273 val = SYNCTRL1_MASTER_SYNC_RST;
275 /* Place master sync in reset */
276 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
280 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
284 /* Set sync trigger mask */
285 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
288 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
291 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
293 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
297 /* Place master sync out of reset */
298 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
299 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
304 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
306 struct idtcm *idtcm = channel->idtcm;
314 u16 output_mask = channel->output_mask;
316 switch (channel->dpll_n) {
318 sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
321 sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
324 sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
327 sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
333 for (pll = 0; pll < 8; pll++) {
335 qn = output_mask & 0x1;
336 output_mask = output_mask >> 1;
339 /* First 4 pll has 2 outputs */
340 qn_plus_1 = output_mask & 0x1;
341 output_mask = output_mask >> 1;
346 if ((qn != 0) || (qn_plus_1 != 0))
347 err = _sync_pll_output(idtcm, pll, sync_src, qn,
357 static int _idtcm_set_dpll_tod(struct idtcm_channel *channel,
358 struct timespec64 const *ts,
359 enum hw_tod_write_trig_sel wr_trig)
361 struct idtcm *idtcm = channel->idtcm;
363 u8 buf[TOD_BYTE_COUNT];
366 struct timespec64 local_ts = *ts;
367 s64 total_overhead_ns;
369 /* Configure HW TOD write trigger. */
370 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
377 cmd |= wr_trig | 0x08;
379 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
385 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
387 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
392 err = idtcm_write(idtcm, channel->hw_dpll_n,
393 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
399 /* ARM HW TOD write trigger. */
402 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
405 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
407 if (idtcm->calculate_overhead_flag) {
408 total_overhead_ns = ktime_to_ns(ktime_get_raw()
410 + idtcm->tod_write_overhead_ns
411 + SETTIME_CORRECTION;
413 timespec64_add_ns(&local_ts, total_overhead_ns);
415 idtcm->calculate_overhead_flag = 0;
418 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
423 err = idtcm_write(idtcm, channel->hw_dpll_n,
424 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
430 static int _idtcm_settime(struct idtcm_channel *channel,
431 struct timespec64 const *ts,
432 enum hw_tod_write_trig_sel wr_trig)
434 struct idtcm *idtcm = channel->idtcm;
440 err = _idtcm_set_dpll_tod(channel, ts, wr_trig);
445 /* Wait for the operation to complete. */
446 for (i = 0; i < 10000; i++) {
447 err = idtcm_read(idtcm, channel->hw_dpll_n,
448 HW_DPLL_TOD_CTRL_1, &trig_sel,
454 if (trig_sel == 0x4a)
463 retval = idtcm_sync_pps_output(channel);
468 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
473 struct idtcm *idtcm = channel->idtcm;
477 for (i = 0; i < 4; i++) {
478 buf[i] = 0xff & (offset_ns);
482 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
488 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
493 struct idtcm *idtcm = channel->idtcm;
497 if (max_ffo_ppb & 0xff000000)
500 for (i = 0; i < 3; i++) {
501 buf[i] = 0xff & (max_ffo_ppb);
505 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
506 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
511 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
514 struct idtcm *idtcm = channel->idtcm;
518 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
526 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
527 PULL_IN_CTRL, &buf, sizeof(buf));
535 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
541 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
546 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
551 err = idtcm_start_phase_pull_in(channel);
556 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
559 struct idtcm *idtcm = channel->idtcm;
560 struct timespec64 ts;
563 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
564 err = idtcm_do_phase_pull_in(channel, delta, 0);
566 idtcm->calculate_overhead_flag = 1;
568 err = _idtcm_gettime(channel, &ts);
573 now = timespec64_to_ns(&ts);
576 ts = ns_to_timespec64(now);
578 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
584 static int idtcm_state_machine_reset(struct idtcm *idtcm)
587 u8 byte = SM_RESET_CMD;
589 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
592 msleep_interruptible(POST_SM_RESET_DELAY_MS);
597 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
599 return idtcm_read(idtcm,
606 static int idtcm_read_bond_id(struct idtcm *idtcm, u8 *bond_id)
608 return idtcm_read(idtcm,
615 static int idtcm_read_hw_csr_id(struct idtcm *idtcm, u16 *hw_csr_id)
620 err = idtcm_read(idtcm, GENERAL_STATUS, HW_CSR_ID, buf, sizeof(buf));
622 *hw_csr_id = (buf[1] << 8) | buf[0];
627 static int idtcm_read_hw_irq_id(struct idtcm *idtcm, u16 *hw_irq_id)
632 err = idtcm_read(idtcm, GENERAL_STATUS, HW_IRQ_ID, buf, sizeof(buf));
634 *hw_irq_id = (buf[1] << 8) | buf[0];
639 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
644 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
646 *product_id = (buf[1] << 8) | buf[0];
651 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
656 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
663 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
665 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
668 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
670 return idtcm_read(idtcm,
677 static int idtcm_read_pipeline(struct idtcm *idtcm, u32 *pipeline)
682 err = idtcm_read(idtcm,
688 *pipeline = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
693 static int process_pll_mask(struct idtcm *idtcm, u32 addr, u8 val, u8 *mask)
697 if (addr == PLL_MASK_ADDR) {
698 if ((val & 0xf0) || !(val & 0xf)) {
699 dev_err(&idtcm->client->dev,
700 "Invalid PLL mask 0x%hhx\n", val);
709 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
714 case OUTPUT_MASK_PLL0_ADDR:
715 SET_U16_LSB(idtcm->channel[0].output_mask, val);
717 case OUTPUT_MASK_PLL0_ADDR + 1:
718 SET_U16_MSB(idtcm->channel[0].output_mask, val);
720 case OUTPUT_MASK_PLL1_ADDR:
721 SET_U16_LSB(idtcm->channel[1].output_mask, val);
723 case OUTPUT_MASK_PLL1_ADDR + 1:
724 SET_U16_MSB(idtcm->channel[1].output_mask, val);
726 case OUTPUT_MASK_PLL2_ADDR:
727 SET_U16_LSB(idtcm->channel[2].output_mask, val);
729 case OUTPUT_MASK_PLL2_ADDR + 1:
730 SET_U16_MSB(idtcm->channel[2].output_mask, val);
732 case OUTPUT_MASK_PLL3_ADDR:
733 SET_U16_LSB(idtcm->channel[3].output_mask, val);
735 case OUTPUT_MASK_PLL3_ADDR + 1:
736 SET_U16_MSB(idtcm->channel[3].output_mask, val);
746 static int check_and_set_masks(struct idtcm *idtcm,
752 if (set_pll_output_mask(idtcm, regaddr, val)) {
753 /* Not an output mask, check for pll mask */
754 err = process_pll_mask(idtcm, regaddr, val, &idtcm->pll_mask);
760 static void display_pll_and_output_masks(struct idtcm *idtcm)
765 dev_dbg(&idtcm->client->dev, "pllmask = 0x%02x\n", idtcm->pll_mask);
767 for (i = 0; i < MAX_PHC_PLL; i++) {
770 if (mask & idtcm->pll_mask)
771 dev_dbg(&idtcm->client->dev,
772 "PLL%d output_mask = 0x%04x\n",
773 i, idtcm->channel[i].output_mask);
777 static int idtcm_load_firmware(struct idtcm *idtcm,
780 const struct firmware *fw;
781 struct idtcm_fwrc *rec;
788 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", FW_FILENAME);
790 err = request_firmware(&fw, FW_FILENAME, dev);
795 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
797 rec = (struct idtcm_fwrc *) fw->data;
800 idtcm_state_machine_reset(idtcm);
802 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
805 dev_err(&idtcm->client->dev,
806 "bad firmware, reserved field non-zero\n");
809 regaddr = rec->hiaddr << 8;
810 regaddr |= rec->loaddr;
813 loaddr = rec->loaddr;
817 err = check_and_set_masks(idtcm, regaddr, val);
821 /* Top (status registers) and bottom are read-only */
822 if ((regaddr < GPIO_USER_CONTROL)
823 || (regaddr >= SCRATCH))
826 /* Page size 128, last 4 bytes of page skipped */
827 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
828 || ((loaddr > 0xfb) && (loaddr <= 0xff)))
831 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
838 display_pll_and_output_masks(idtcm);
841 release_firmware(fw);
845 static int idtcm_pps_enable(struct idtcm_channel *channel, bool enable)
847 struct idtcm *idtcm = channel->idtcm;
853 * This assumes that the 1-PPS is on the second of the two
854 * output. But is this always true?
856 switch (channel->dpll_n) {
873 err = idtcm_read(idtcm, module, OUT_CTRL_1, &val, sizeof(val));
879 val |= SQUELCH_DISABLE;
881 val &= ~SQUELCH_DISABLE;
883 err = idtcm_write(idtcm, module, OUT_CTRL_1, &val, sizeof(val));
891 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
892 enum pll_mode pll_mode)
894 struct idtcm *idtcm = channel->idtcm;
898 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
899 &dpll_mode, sizeof(dpll_mode));
903 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
905 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
907 channel->pll_mode = pll_mode;
909 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
910 &dpll_mode, sizeof(dpll_mode));
917 /* PTP Hardware Clock interface */
919 static int idtcm_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
921 struct idtcm_channel *channel =
922 container_of(ptp, struct idtcm_channel, caps);
923 struct idtcm *idtcm = channel->idtcm;
930 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
931 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
937 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
946 * FCW = -------------
954 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
955 fcw = ppb * 1000000000000ULL;
957 fcw = div_u64(fcw, 111022);
962 for (i = 0; i < 6; i++) {
967 mutex_lock(&idtcm->reg_lock);
969 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
972 mutex_unlock(&idtcm->reg_lock);
976 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
978 struct idtcm_channel *channel =
979 container_of(ptp, struct idtcm_channel, caps);
980 struct idtcm *idtcm = channel->idtcm;
983 mutex_lock(&idtcm->reg_lock);
985 err = _idtcm_gettime(channel, ts);
987 mutex_unlock(&idtcm->reg_lock);
992 static int idtcm_settime(struct ptp_clock_info *ptp,
993 const struct timespec64 *ts)
995 struct idtcm_channel *channel =
996 container_of(ptp, struct idtcm_channel, caps);
997 struct idtcm *idtcm = channel->idtcm;
1000 mutex_lock(&idtcm->reg_lock);
1002 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
1004 mutex_unlock(&idtcm->reg_lock);
1009 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1011 struct idtcm_channel *channel =
1012 container_of(ptp, struct idtcm_channel, caps);
1013 struct idtcm *idtcm = channel->idtcm;
1016 mutex_lock(&idtcm->reg_lock);
1018 err = _idtcm_adjtime(channel, delta);
1020 mutex_unlock(&idtcm->reg_lock);
1025 static int idtcm_enable(struct ptp_clock_info *ptp,
1026 struct ptp_clock_request *rq, int on)
1028 struct idtcm_channel *channel =
1029 container_of(ptp, struct idtcm_channel, caps);
1032 case PTP_CLK_REQ_PEROUT:
1034 return idtcm_pps_enable(channel, false);
1036 /* Only accept a 1-PPS aligned to the second. */
1037 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1038 rq->perout.period.nsec)
1041 return idtcm_pps_enable(channel, true);
1049 static int idtcm_enable_tod(struct idtcm_channel *channel)
1051 struct idtcm *idtcm = channel->idtcm;
1052 struct timespec64 ts = {0, 0};
1056 err = idtcm_pps_enable(channel, false);
1061 * Start the TOD clock ticking.
1063 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1069 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1073 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
1076 static void idtcm_display_version_info(struct idtcm *idtcm)
1088 idtcm_read_major_release(idtcm, &major);
1089 idtcm_read_minor_release(idtcm, &minor);
1090 idtcm_read_hotfix_release(idtcm, &hotfix);
1091 idtcm_read_pipeline(idtcm, &pipeline);
1093 idtcm_read_product_id(idtcm, &product_id);
1094 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1095 idtcm_read_bond_id(idtcm, &bond_id);
1096 idtcm_read_hw_csr_id(idtcm, &csr_id);
1097 idtcm_read_hw_irq_id(idtcm, &irq_id);
1099 dev_info(&idtcm->client->dev, "Version: %d.%d.%d, Pipeline %u\t"
1100 "0x%04x, Rev %d, Bond %d, CSR %d, IRQ %d\n",
1101 major, minor, hotfix, pipeline,
1102 product_id, hw_rev_id, bond_id, csr_id, irq_id);
1105 static struct ptp_clock_info idtcm_caps = {
1106 .owner = THIS_MODULE,
1109 .adjfreq = &idtcm_adjfreq,
1110 .adjtime = &idtcm_adjtime,
1111 .gettime64 = &idtcm_gettime,
1112 .settime64 = &idtcm_settime,
1113 .enable = &idtcm_enable,
1116 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
1118 struct idtcm_channel *channel;
1121 if (!(index < MAX_PHC_PLL))
1124 channel = &idtcm->channel[index];
1128 channel->dpll_freq = DPLL_FREQ_0;
1129 channel->dpll_n = DPLL_0;
1130 channel->tod_read_primary = TOD_READ_PRIMARY_0;
1131 channel->tod_write = TOD_WRITE_0;
1132 channel->tod_n = TOD_0;
1133 channel->hw_dpll_n = HW_DPLL_0;
1134 channel->dpll_phase = DPLL_PHASE_0;
1135 channel->dpll_ctrl_n = DPLL_CTRL_0;
1136 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1139 channel->dpll_freq = DPLL_FREQ_1;
1140 channel->dpll_n = DPLL_1;
1141 channel->tod_read_primary = TOD_READ_PRIMARY_1;
1142 channel->tod_write = TOD_WRITE_1;
1143 channel->tod_n = TOD_1;
1144 channel->hw_dpll_n = HW_DPLL_1;
1145 channel->dpll_phase = DPLL_PHASE_1;
1146 channel->dpll_ctrl_n = DPLL_CTRL_1;
1147 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1150 channel->dpll_freq = DPLL_FREQ_2;
1151 channel->dpll_n = DPLL_2;
1152 channel->tod_read_primary = TOD_READ_PRIMARY_2;
1153 channel->tod_write = TOD_WRITE_2;
1154 channel->tod_n = TOD_2;
1155 channel->hw_dpll_n = HW_DPLL_2;
1156 channel->dpll_phase = DPLL_PHASE_2;
1157 channel->dpll_ctrl_n = DPLL_CTRL_2;
1158 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
1161 channel->dpll_freq = DPLL_FREQ_3;
1162 channel->dpll_n = DPLL_3;
1163 channel->tod_read_primary = TOD_READ_PRIMARY_3;
1164 channel->tod_write = TOD_WRITE_3;
1165 channel->tod_n = TOD_3;
1166 channel->hw_dpll_n = HW_DPLL_3;
1167 channel->dpll_phase = DPLL_PHASE_3;
1168 channel->dpll_ctrl_n = DPLL_CTRL_3;
1169 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
1175 channel->idtcm = idtcm;
1177 channel->caps = idtcm_caps;
1178 snprintf(channel->caps.name, sizeof(channel->caps.name),
1179 "IDT CM PLL%u", index);
1181 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1185 err = idtcm_enable_tod(channel);
1189 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
1191 if (IS_ERR(channel->ptp_clock)) {
1192 err = PTR_ERR(channel->ptp_clock);
1193 channel->ptp_clock = NULL;
1197 if (!channel->ptp_clock)
1200 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
1201 index, channel->ptp_clock->index);
1206 static void ptp_clock_unregister_all(struct idtcm *idtcm)
1209 struct idtcm_channel *channel;
1211 for (i = 0; i < MAX_PHC_PLL; i++) {
1213 channel = &idtcm->channel[i];
1215 if (channel->ptp_clock)
1216 ptp_clock_unregister(channel->ptp_clock);
1220 static void set_default_masks(struct idtcm *idtcm)
1222 idtcm->pll_mask = DEFAULT_PLL_MASK;
1224 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
1225 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
1226 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
1227 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
1230 static int set_tod_write_overhead(struct idtcm *idtcm)
1240 char buf[TOD_BYTE_COUNT];
1242 struct idtcm_channel *channel = &idtcm->channel[2];
1244 /* Set page offset */
1245 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1248 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
1250 start = ktime_get_raw();
1252 err = idtcm_write(idtcm, channel->hw_dpll_n,
1253 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
1258 stop = ktime_get_raw();
1260 total_ns += ktime_to_ns(stop - start);
1263 idtcm->tod_write_overhead_ns = div_s64(total_ns,
1264 TOD_WRITE_OVERHEAD_COUNT_MAX);
1269 static int idtcm_probe(struct i2c_client *client,
1270 const struct i2c_device_id *id)
1272 struct idtcm *idtcm;
1276 /* Unused for now */
1279 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
1284 idtcm->client = client;
1285 idtcm->page_offset = 0xff;
1286 idtcm->calculate_overhead_flag = 0;
1288 set_default_masks(idtcm);
1290 mutex_init(&idtcm->reg_lock);
1291 mutex_lock(&idtcm->reg_lock);
1293 idtcm_display_version_info(idtcm);
1295 err = set_tod_write_overhead(idtcm);
1298 mutex_unlock(&idtcm->reg_lock);
1302 err = idtcm_load_firmware(idtcm, &client->dev);
1305 dev_warn(&idtcm->client->dev,
1306 "loading firmware failed with %d\n", err);
1308 if (idtcm->pll_mask) {
1309 for (i = 0; i < MAX_PHC_PLL; i++) {
1310 if (idtcm->pll_mask & (1 << i)) {
1311 err = idtcm_enable_channel(idtcm, i);
1317 dev_err(&idtcm->client->dev,
1318 "no PLLs flagged as PHCs, nothing to do\n");
1322 mutex_unlock(&idtcm->reg_lock);
1325 ptp_clock_unregister_all(idtcm);
1329 i2c_set_clientdata(client, idtcm);
1334 static int idtcm_remove(struct i2c_client *client)
1336 struct idtcm *idtcm = i2c_get_clientdata(client);
1338 ptp_clock_unregister_all(idtcm);
1340 mutex_destroy(&idtcm->reg_lock);
1346 static const struct of_device_id idtcm_dt_id[] = {
1347 { .compatible = "idt,8a34000" },
1348 { .compatible = "idt,8a34001" },
1349 { .compatible = "idt,8a34002" },
1350 { .compatible = "idt,8a34003" },
1351 { .compatible = "idt,8a34004" },
1352 { .compatible = "idt,8a34005" },
1353 { .compatible = "idt,8a34006" },
1354 { .compatible = "idt,8a34007" },
1355 { .compatible = "idt,8a34008" },
1356 { .compatible = "idt,8a34009" },
1357 { .compatible = "idt,8a34010" },
1358 { .compatible = "idt,8a34011" },
1359 { .compatible = "idt,8a34012" },
1360 { .compatible = "idt,8a34013" },
1361 { .compatible = "idt,8a34014" },
1362 { .compatible = "idt,8a34015" },
1363 { .compatible = "idt,8a34016" },
1364 { .compatible = "idt,8a34017" },
1365 { .compatible = "idt,8a34018" },
1366 { .compatible = "idt,8a34019" },
1367 { .compatible = "idt,8a34040" },
1368 { .compatible = "idt,8a34041" },
1369 { .compatible = "idt,8a34042" },
1370 { .compatible = "idt,8a34043" },
1371 { .compatible = "idt,8a34044" },
1372 { .compatible = "idt,8a34045" },
1373 { .compatible = "idt,8a34046" },
1374 { .compatible = "idt,8a34047" },
1375 { .compatible = "idt,8a34048" },
1376 { .compatible = "idt,8a34049" },
1379 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
1382 static const struct i2c_device_id idtcm_i2c_id[] = {
1415 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
1417 static struct i2c_driver idtcm_driver = {
1419 .of_match_table = of_match_ptr(idtcm_dt_id),
1422 .probe = idtcm_probe,
1423 .remove = idtcm_remove,
1424 .id_table = idtcm_i2c_id,
1427 module_i2c_driver(idtcm_driver);