1 // SPDX-License-Identifier: GPL-2.0+
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
8 #include <linux/firmware.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/timekeeping.h>
16 #include <linux/string.h>
18 #include "ptp_private.h"
19 #include "ptp_clockmatrix.h"
21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24 MODULE_VERSION("1.0");
25 MODULE_LICENSE("GPL");
28 * The name of the firmware file to be loaded
29 * over-rides any automatic selection
31 static char *firmware;
32 module_param(firmware, charp, 0);
34 #define SETTIME_CORRECTION (0)
36 static int contains_full_configuration(const struct firmware *fw)
38 s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES;
39 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
45 /* If the firmware contains 'full configuration' SM_RESET can be used
46 * to ensure proper configuration.
48 * Full configuration is defined as the number of programmable
49 * bytes within the configuration range minus page offset addr range.
51 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
52 regaddr = rec->hiaddr << 8;
53 regaddr |= rec->loaddr;
59 /* Top (status registers) and bottom are read-only */
60 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
63 /* Page size 128, last 4 bytes of page skipped */
64 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
70 return (count >= full_count);
73 static int char_array_to_timespec(u8 *buf,
75 struct timespec64 *ts)
81 if (count < TOD_BYTE_COUNT)
84 /* Sub-nanoseconds are in buf[0]. */
86 for (i = 0; i < 3; i++) {
92 for (i = 0; i < 5; i++) {
103 static int timespec_to_char_array(struct timespec64 const *ts,
111 if (count < TOD_BYTE_COUNT)
117 /* Sub-nanoseconds are in buf[0]. */
119 for (i = 1; i < 5; i++) {
120 buf[i] = nsec & 0xff;
124 for (i = 5; i < TOD_BYTE_COUNT; i++) {
133 static int idtcm_strverscmp(const char *version1, const char *version2)
138 if (sscanf(version1, "%hhu.%hhu.%hhu",
139 &ver1[0], &ver1[1], &ver1[2]) != 3)
141 if (sscanf(version2, "%hhu.%hhu.%hhu",
142 &ver2[0], &ver2[1], &ver2[2]) != 3)
145 for (i = 0; i < 3; i++) {
146 if (ver1[i] > ver2[i])
148 if (ver1[i] < ver2[i])
155 static int idtcm_xfer_read(struct idtcm *idtcm,
160 struct i2c_client *client = idtcm->client;
161 struct i2c_msg msg[2];
163 char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
165 msg[0].addr = client->addr;
168 msg[0].buf = ®addr;
170 msg[1].addr = client->addr;
171 msg[1].flags = I2C_M_RD;
175 cnt = i2c_transfer(client->adapter, msg, 2);
178 dev_err(&client->dev,
184 } else if (cnt != 2) {
185 dev_err(&client->dev,
186 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
193 static int idtcm_xfer_write(struct idtcm *idtcm,
198 struct i2c_client *client = idtcm->client;
199 /* we add 1 byte for device register */
200 u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
202 char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
204 if (count > IDTCM_MAX_WRITE_COUNT)
208 memcpy(&msg[1], buf, count);
210 cnt = i2c_master_send(client, msg, count + 1);
213 dev_err(&client->dev,
224 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
229 if (idtcm->page_offset == val)
237 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
240 idtcm->page_offset = 0xff;
241 dev_err(&idtcm->client->dev, "failed to set page offset\n");
243 idtcm->page_offset = val;
249 static int _idtcm_rdwr(struct idtcm *idtcm,
259 hi = (regaddr >> 8) & 0xff;
262 err = idtcm_page_offset(idtcm, hi);
268 return idtcm_xfer_write(idtcm, lo, buf, count);
270 return idtcm_xfer_read(idtcm, lo, buf, count);
273 static int idtcm_read(struct idtcm *idtcm,
279 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
282 static int idtcm_write(struct idtcm *idtcm,
288 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
291 static int clear_boot_status(struct idtcm *idtcm)
296 err = idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
301 static int read_boot_status(struct idtcm *idtcm, u32 *status)
306 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
308 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
313 static int wait_for_boot_status_ready(struct idtcm *idtcm)
316 u8 i = 30; /* 30 * 100ms = 3s */
320 err = read_boot_status(idtcm, &status);
333 dev_warn(&idtcm->client->dev, "%s timed out\n", __func__);
338 static int _idtcm_gettime(struct idtcm_channel *channel,
339 struct timespec64 *ts)
341 struct idtcm *idtcm = channel->idtcm;
342 u8 buf[TOD_BYTE_COUNT];
347 err = idtcm_read(idtcm, channel->tod_read_primary,
348 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
352 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
353 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
354 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
356 err = idtcm_write(idtcm, channel->tod_read_primary,
357 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
361 /* wait trigger to be 0 */
362 while (trigger & TOD_READ_TRIGGER_MASK) {
364 if (idtcm->calculate_overhead_flag)
365 idtcm->start_time = ktime_get_raw();
367 err = idtcm_read(idtcm, channel->tod_read_primary,
368 TOD_READ_PRIMARY_CMD, &trigger,
378 err = idtcm_read(idtcm, channel->tod_read_primary,
379 TOD_READ_PRIMARY, buf, sizeof(buf));
384 err = char_array_to_timespec(buf, sizeof(buf), ts);
389 static int _sync_pll_output(struct idtcm *idtcm,
401 if ((qn == 0) && (qn_plus_1 == 0))
406 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
407 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
410 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
411 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
414 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
415 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
418 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
419 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
422 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
423 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
426 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
427 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
430 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
431 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
434 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
435 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
441 val = SYNCTRL1_MASTER_SYNC_RST;
443 /* Place master sync in reset */
444 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
448 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
452 /* Set sync trigger mask */
453 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
456 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
459 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
461 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
465 /* PLL5 can have OUT8 as second additional output. */
466 if ((pll == 5) && (qn_plus_1 != 0)) {
467 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
468 &temp, sizeof(temp));
472 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
474 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
475 &temp, sizeof(temp));
479 temp |= Q9_TO_Q8_SYNC_TRIG;
481 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
482 &temp, sizeof(temp));
487 /* PLL6 can have OUT11 as second additional output. */
488 if ((pll == 6) && (qn_plus_1 != 0)) {
489 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
490 &temp, sizeof(temp));
494 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
496 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
497 &temp, sizeof(temp));
501 temp |= Q10_TO_Q11_SYNC_TRIG;
503 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
504 &temp, sizeof(temp));
509 /* Place master sync out of reset */
510 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
511 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
516 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
522 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
525 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
528 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
531 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
540 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
542 struct idtcm *idtcm = channel->idtcm;
553 u16 output_mask = channel->output_mask;
555 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
559 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
560 &temp, sizeof(temp));
564 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
565 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
568 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
569 &temp, sizeof(temp));
573 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
574 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
577 for (pll = 0; pll < 8; pll++) {
582 /* First 4 pll has 2 outputs */
583 qn = output_mask & 0x1;
584 output_mask = output_mask >> 1;
585 qn_plus_1 = output_mask & 0x1;
586 output_mask = output_mask >> 1;
587 } else if (pll == 4) {
589 qn = output_mask & 0x1;
590 output_mask = output_mask >> 1;
592 } else if (pll == 5) {
594 qn_plus_1 = output_mask & 0x1;
595 output_mask = output_mask >> 1;
597 qn = output_mask & 0x1;
598 output_mask = output_mask >> 1;
599 } else if (pll == 6) {
600 qn = output_mask & 0x1;
601 output_mask = output_mask >> 1;
603 qn_plus_1 = output_mask & 0x1;
604 output_mask = output_mask >> 1;
606 } else if (pll == 7) {
607 if (out11_mux == 0) {
608 qn = output_mask & 0x1;
609 output_mask = output_mask >> 1;
613 if ((qn != 0) || (qn_plus_1 != 0))
614 err = _sync_pll_output(idtcm, pll, sync_src, qn,
624 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
625 struct timespec64 const *ts,
626 enum hw_tod_write_trig_sel wr_trig)
628 struct idtcm *idtcm = channel->idtcm;
630 u8 buf[TOD_BYTE_COUNT];
633 struct timespec64 local_ts = *ts;
634 s64 total_overhead_ns;
636 /* Configure HW TOD write trigger. */
637 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
644 cmd |= wr_trig | 0x08;
646 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
652 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
654 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
659 err = idtcm_write(idtcm, channel->hw_dpll_n,
660 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
666 /* ARM HW TOD write trigger. */
669 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
672 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
674 if (idtcm->calculate_overhead_flag) {
675 /* Assumption: I2C @ 400KHz */
676 ktime_t diff = ktime_sub(ktime_get_raw(),
678 total_overhead_ns = ktime_to_ns(diff)
679 + idtcm->tod_write_overhead_ns
680 + SETTIME_CORRECTION;
682 timespec64_add_ns(&local_ts, total_overhead_ns);
684 idtcm->calculate_overhead_flag = 0;
687 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
692 err = idtcm_write(idtcm, channel->hw_dpll_n,
693 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
699 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
700 struct timespec64 const *ts,
701 enum scsr_tod_write_trig_sel wr_trig,
702 enum scsr_tod_write_type_sel wr_type)
704 struct idtcm *idtcm = channel->idtcm;
705 unsigned char buf[TOD_BYTE_COUNT], cmd;
706 struct timespec64 local_ts = *ts;
709 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
711 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
716 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
721 /* Trigger the write operation. */
722 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
727 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
728 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
729 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
730 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
732 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
737 /* Wait for the operation to complete. */
739 /* pps trigger takes up to 1 sec to complete */
740 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
743 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
748 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
752 dev_err(&idtcm->client->dev,
753 "Timed out waiting for the write counter\n");
761 static int get_output_base_addr(u8 outn)
809 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
810 struct timespec64 const *ts)
812 struct idtcm *idtcm = channel->idtcm;
815 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
818 dev_err(&idtcm->client->dev,
819 "%s: Set HW ToD failed\n", __func__);
823 return idtcm_sync_pps_output(channel);
826 static int _idtcm_settime(struct idtcm_channel *channel,
827 struct timespec64 const *ts,
828 enum scsr_tod_write_type_sel wr_type)
830 return _idtcm_set_dpll_scsr_tod(channel, ts,
831 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
835 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
840 struct idtcm *idtcm = channel->idtcm;
844 for (i = 0; i < 4; i++) {
845 buf[i] = 0xff & (offset_ns);
849 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
855 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
860 struct idtcm *idtcm = channel->idtcm;
864 if (max_ffo_ppb & 0xff000000)
867 for (i = 0; i < 3; i++) {
868 buf[i] = 0xff & (max_ffo_ppb);
872 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
873 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
878 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
881 struct idtcm *idtcm = channel->idtcm;
885 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
893 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
894 PULL_IN_CTRL, &buf, sizeof(buf));
902 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
908 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
913 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
918 err = idtcm_start_phase_pull_in(channel);
923 static int set_tod_write_overhead(struct idtcm_channel *channel)
925 struct idtcm *idtcm = channel->idtcm;
935 char buf[TOD_BYTE_COUNT] = {0};
937 /* Set page offset */
938 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
941 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
943 start = ktime_get_raw();
945 err = idtcm_write(idtcm, channel->hw_dpll_n,
946 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
951 stop = ktime_get_raw();
953 diff = ktime_sub(stop, start);
955 current_ns = ktime_to_ns(diff);
958 lowest_ns = current_ns;
960 if (current_ns < lowest_ns)
961 lowest_ns = current_ns;
965 idtcm->tod_write_overhead_ns = lowest_ns;
970 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
973 struct idtcm *idtcm = channel->idtcm;
974 struct timespec64 ts;
977 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
978 err = idtcm_do_phase_pull_in(channel, delta, 0);
980 idtcm->calculate_overhead_flag = 1;
982 err = set_tod_write_overhead(channel);
987 err = _idtcm_gettime(channel, &ts);
992 now = timespec64_to_ns(&ts);
995 ts = ns_to_timespec64(now);
997 err = _idtcm_settime_deprecated(channel, &ts);
1003 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1005 u8 byte = SM_RESET_CMD;
1010 clear_boot_status(idtcm);
1012 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
1015 for (i = 0; i < 30; i++) {
1016 msleep_interruptible(100);
1017 read_boot_status(idtcm, &status);
1019 if (status == 0xA0) {
1020 dev_dbg(&idtcm->client->dev,
1021 "SM_RESET completed in %d ms\n",
1028 dev_err(&idtcm->client->dev, "Timed out waiting for CM_RESET to complete\n");
1034 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1036 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1039 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1044 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1046 *product_id = (buf[1] << 8) | buf[0];
1051 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1056 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1063 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1065 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1068 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1070 return idtcm_read(idtcm,
1077 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1080 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1081 config_select, sizeof(u8));
1084 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1089 case TOD0_OUT_ALIGN_MASK_ADDR:
1090 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1092 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1093 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1095 case TOD1_OUT_ALIGN_MASK_ADDR:
1096 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1098 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1099 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1101 case TOD2_OUT_ALIGN_MASK_ADDR:
1102 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1104 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1105 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1107 case TOD3_OUT_ALIGN_MASK_ADDR:
1108 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1110 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1111 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1114 err = -EFAULT; /* Bad address */;
1121 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1123 if (index >= MAX_TOD) {
1124 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
1128 if (pll >= MAX_PLL) {
1129 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
1133 idtcm->channel[index].pll = pll;
1138 static int check_and_set_masks(struct idtcm *idtcm,
1146 if ((val & 0xf0) || !(val & 0x0f)) {
1147 dev_err(&idtcm->client->dev,
1148 "Invalid TOD mask 0x%hhx\n", val);
1151 idtcm->tod_mask = val;
1154 case TOD0_PTP_PLL_ADDR:
1155 err = set_tod_ptp_pll(idtcm, 0, val);
1157 case TOD1_PTP_PLL_ADDR:
1158 err = set_tod_ptp_pll(idtcm, 1, val);
1160 case TOD2_PTP_PLL_ADDR:
1161 err = set_tod_ptp_pll(idtcm, 2, val);
1163 case TOD3_PTP_PLL_ADDR:
1164 err = set_tod_ptp_pll(idtcm, 3, val);
1167 err = set_pll_output_mask(idtcm, regaddr, val);
1174 static void display_pll_and_masks(struct idtcm *idtcm)
1179 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
1181 for (i = 0; i < MAX_TOD; i++) {
1184 if (mask & idtcm->tod_mask)
1185 dev_dbg(&idtcm->client->dev,
1186 "TOD%d pll = %d output_mask = 0x%04x\n",
1187 i, idtcm->channel[i].pll,
1188 idtcm->channel[i].output_mask);
1192 static int idtcm_load_firmware(struct idtcm *idtcm,
1195 char fname[128] = FW_FILENAME;
1196 const struct firmware *fw;
1197 struct idtcm_fwrc *rec;
1204 if (firmware) /* module parameter */
1205 snprintf(fname, sizeof(fname), "%s", firmware);
1207 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
1209 err = request_firmware(&fw, fname, dev);
1212 dev_err(&idtcm->client->dev,
1213 "Failed at line %d in func %s!\n",
1219 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1221 rec = (struct idtcm_fwrc *) fw->data;
1223 if (contains_full_configuration(fw))
1224 idtcm_state_machine_reset(idtcm);
1226 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1228 if (rec->reserved) {
1229 dev_err(&idtcm->client->dev,
1230 "bad firmware, reserved field non-zero\n");
1233 regaddr = rec->hiaddr << 8;
1234 regaddr |= rec->loaddr;
1237 loaddr = rec->loaddr;
1241 err = check_and_set_masks(idtcm, regaddr, val);
1244 if (err != -EINVAL) {
1247 /* Top (status registers) and bottom are read-only */
1248 if ((regaddr < GPIO_USER_CONTROL)
1249 || (regaddr >= SCRATCH))
1252 /* Page size 128, last 4 bytes of page skipped */
1253 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
1257 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1264 display_pll_and_masks(idtcm);
1267 release_firmware(fw);
1271 static int idtcm_output_enable(struct idtcm_channel *channel,
1272 bool enable, unsigned int outn)
1274 struct idtcm *idtcm = channel->idtcm;
1279 base = get_output_base_addr(outn);
1282 dev_err(&idtcm->client->dev,
1283 "%s - Unsupported out%d", __func__, outn);
1287 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1293 val |= SQUELCH_DISABLE;
1295 val &= ~SQUELCH_DISABLE;
1297 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1300 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1307 mask = channel->output_mask;
1314 err = idtcm_output_enable(channel, enable, outn);
1327 static int idtcm_perout_enable(struct idtcm_channel *channel,
1329 struct ptp_perout_request *perout)
1331 unsigned int flags = perout->flags;
1333 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1334 return idtcm_output_mask_enable(channel, enable);
1336 /* Enable/disable individual output instead */
1337 return idtcm_output_enable(channel, enable, perout->index);
1340 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1341 enum pll_mode *pll_mode)
1343 struct idtcm *idtcm = channel->idtcm;
1347 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1348 &dpll_mode, sizeof(dpll_mode));
1352 *pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1357 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1358 enum pll_mode pll_mode)
1360 struct idtcm *idtcm = channel->idtcm;
1364 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1365 &dpll_mode, sizeof(dpll_mode));
1369 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1371 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1373 channel->pll_mode = pll_mode;
1375 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1376 &dpll_mode, sizeof(dpll_mode));
1383 /* PTP Hardware Clock interface */
1386 * @brief Maximum absolute value for write phase offset in picoseconds
1388 * Destination signed register is 32-bit register in resolution of 50ps
1390 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1392 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1394 struct idtcm *idtcm = channel->idtcm;
1402 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1404 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1410 offset_ps = (s64)delta_ns * 1000;
1413 * Check for 32-bit signed max * 50:
1415 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1417 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1418 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1419 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1420 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1422 phase_50ps = div_s64(offset_ps, 50);
1424 for (i = 0; i < 4; i++) {
1425 buf[i] = phase_50ps & 0xff;
1429 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1435 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1437 struct idtcm *idtcm = channel->idtcm;
1443 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1444 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1450 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1459 * FCW = -------------
1463 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1464 fcw = scaled_ppm * 244140625ULL;
1466 fcw = div_s64(fcw, 1776);
1468 for (i = 0; i < 6; i++) {
1469 buf[i] = fcw & 0xff;
1473 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1479 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1481 struct idtcm_channel *channel =
1482 container_of(ptp, struct idtcm_channel, caps);
1483 struct idtcm *idtcm = channel->idtcm;
1486 mutex_lock(&idtcm->reg_lock);
1488 err = _idtcm_gettime(channel, ts);
1491 dev_err(&idtcm->client->dev,
1492 "Failed at line %d in func %s!\n",
1496 mutex_unlock(&idtcm->reg_lock);
1501 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1502 const struct timespec64 *ts)
1504 struct idtcm_channel *channel =
1505 container_of(ptp, struct idtcm_channel, caps);
1506 struct idtcm *idtcm = channel->idtcm;
1509 mutex_lock(&idtcm->reg_lock);
1511 err = _idtcm_settime_deprecated(channel, ts);
1514 dev_err(&idtcm->client->dev,
1515 "Failed at line %d in func %s!\n",
1519 mutex_unlock(&idtcm->reg_lock);
1524 static int idtcm_settime(struct ptp_clock_info *ptp,
1525 const struct timespec64 *ts)
1527 struct idtcm_channel *channel =
1528 container_of(ptp, struct idtcm_channel, caps);
1529 struct idtcm *idtcm = channel->idtcm;
1532 mutex_lock(&idtcm->reg_lock);
1534 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1537 dev_err(&idtcm->client->dev,
1538 "Failed at line %d in func %s!\n",
1542 mutex_unlock(&idtcm->reg_lock);
1547 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1549 struct idtcm_channel *channel =
1550 container_of(ptp, struct idtcm_channel, caps);
1551 struct idtcm *idtcm = channel->idtcm;
1554 mutex_lock(&idtcm->reg_lock);
1556 err = _idtcm_adjtime_deprecated(channel, delta);
1559 dev_err(&idtcm->client->dev,
1560 "Failed at line %d in func %s!\n",
1564 mutex_unlock(&idtcm->reg_lock);
1569 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1571 struct idtcm_channel *channel =
1572 container_of(ptp, struct idtcm_channel, caps);
1573 struct idtcm *idtcm = channel->idtcm;
1574 struct timespec64 ts;
1575 enum scsr_tod_write_type_sel type;
1578 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1579 err = idtcm_do_phase_pull_in(channel, delta, 0);
1581 dev_err(&idtcm->client->dev,
1582 "Failed at line %d in func %s!\n",
1589 ts = ns_to_timespec64(delta);
1590 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1592 ts = ns_to_timespec64(-delta);
1593 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1596 mutex_lock(&idtcm->reg_lock);
1598 err = _idtcm_settime(channel, &ts, type);
1601 dev_err(&idtcm->client->dev,
1602 "Failed at line %d in func %s!\n",
1606 mutex_unlock(&idtcm->reg_lock);
1611 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1613 struct idtcm_channel *channel =
1614 container_of(ptp, struct idtcm_channel, caps);
1616 struct idtcm *idtcm = channel->idtcm;
1620 mutex_lock(&idtcm->reg_lock);
1622 err = _idtcm_adjphase(channel, delta);
1625 dev_err(&idtcm->client->dev,
1626 "Failed at line %d in func %s!\n",
1630 mutex_unlock(&idtcm->reg_lock);
1635 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1637 struct idtcm_channel *channel =
1638 container_of(ptp, struct idtcm_channel, caps);
1640 struct idtcm *idtcm = channel->idtcm;
1644 mutex_lock(&idtcm->reg_lock);
1646 err = _idtcm_adjfine(channel, scaled_ppm);
1649 dev_err(&idtcm->client->dev,
1650 "Failed at line %d in func %s!\n",
1654 mutex_unlock(&idtcm->reg_lock);
1659 static int idtcm_enable(struct ptp_clock_info *ptp,
1660 struct ptp_clock_request *rq, int on)
1664 struct idtcm_channel *channel =
1665 container_of(ptp, struct idtcm_channel, caps);
1668 case PTP_CLK_REQ_PEROUT:
1670 err = idtcm_perout_enable(channel, false, &rq->perout);
1672 dev_err(&channel->idtcm->client->dev,
1673 "Failed at line %d in func %s!\n",
1679 /* Only accept a 1-PPS aligned to the second. */
1680 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1681 rq->perout.period.nsec)
1684 err = idtcm_perout_enable(channel, true, &rq->perout);
1686 dev_err(&channel->idtcm->client->dev,
1687 "Failed at line %d in func %s!\n",
1698 static int _enable_pll_tod_sync(struct idtcm *idtcm,
1707 u16 out0 = 0, out1 = 0;
1709 if ((qn == 0) && (qn_plus_1 == 0))
1770 * Enable OUTPUT OUT_SYNC.
1773 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1778 val &= ~OUT_SYNC_DISABLE;
1780 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1787 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1792 val &= ~OUT_SYNC_DISABLE;
1794 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1800 /* enable dpll sync tod pps, must be set before dpll_mode */
1801 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1805 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1806 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1809 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1812 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1814 struct idtcm *idtcm = channel->idtcm;
1822 u16 output_mask = channel->output_mask;
1828 * set tod_out_sync_enable to 0.
1830 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1834 cfg &= ~TOD_OUT_SYNC_ENABLE;
1836 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1840 switch (channel->tod_n) {
1857 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1858 &temp, sizeof(temp));
1862 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1863 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1866 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1867 &temp, sizeof(temp));
1871 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1872 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1875 for (pll = 0; pll < 8; pll++) {
1880 /* First 4 pll has 2 outputs */
1881 qn = output_mask & 0x1;
1882 output_mask = output_mask >> 1;
1883 qn_plus_1 = output_mask & 0x1;
1884 output_mask = output_mask >> 1;
1885 } else if (pll == 4) {
1886 if (out8_mux == 0) {
1887 qn = output_mask & 0x1;
1888 output_mask = output_mask >> 1;
1890 } else if (pll == 5) {
1892 qn_plus_1 = output_mask & 0x1;
1893 output_mask = output_mask >> 1;
1895 qn = output_mask & 0x1;
1896 output_mask = output_mask >> 1;
1897 } else if (pll == 6) {
1898 qn = output_mask & 0x1;
1899 output_mask = output_mask >> 1;
1901 qn_plus_1 = output_mask & 0x1;
1902 output_mask = output_mask >> 1;
1904 } else if (pll == 7) {
1905 if (out11_mux == 0) {
1906 qn = output_mask & 0x1;
1907 output_mask = output_mask >> 1;
1911 if ((qn != 0) || (qn_plus_1 != 0))
1912 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1922 static int idtcm_enable_tod(struct idtcm_channel *channel)
1924 struct idtcm *idtcm = channel->idtcm;
1925 struct timespec64 ts = {0, 0};
1930 * Start the TOD clock ticking.
1932 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1938 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1942 if (idtcm->deprecated)
1943 return _idtcm_settime_deprecated(channel, &ts);
1945 return _idtcm_settime(channel, &ts,
1946 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1949 static void idtcm_set_version_info(struct idtcm *idtcm)
1957 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n";
1959 idtcm_read_major_release(idtcm, &major);
1960 idtcm_read_minor_release(idtcm, &minor);
1961 idtcm_read_hotfix_release(idtcm, &hotfix);
1963 idtcm_read_product_id(idtcm, &product_id);
1964 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1966 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1968 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1969 major, minor, hotfix);
1971 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
1972 idtcm->deprecated = 0;
1974 idtcm->deprecated = 1;
1976 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
1977 product_id, hw_rev_id, config_select);
1980 static const struct ptp_clock_info idtcm_caps = {
1981 .owner = THIS_MODULE,
1984 .adjphase = &idtcm_adjphase,
1985 .adjfine = &idtcm_adjfine,
1986 .adjtime = &idtcm_adjtime,
1987 .gettime64 = &idtcm_gettime,
1988 .settime64 = &idtcm_settime,
1989 .enable = &idtcm_enable,
1992 static const struct ptp_clock_info idtcm_caps_deprecated = {
1993 .owner = THIS_MODULE,
1996 .adjphase = &idtcm_adjphase,
1997 .adjfine = &idtcm_adjfine,
1998 .adjtime = &idtcm_adjtime_deprecated,
1999 .gettime64 = &idtcm_gettime,
2000 .settime64 = &idtcm_settime_deprecated,
2001 .enable = &idtcm_enable,
2004 static int configure_channel_pll(struct idtcm_channel *channel)
2008 switch (channel->pll) {
2010 channel->dpll_freq = DPLL_FREQ_0;
2011 channel->dpll_n = DPLL_0;
2012 channel->hw_dpll_n = HW_DPLL_0;
2013 channel->dpll_phase = DPLL_PHASE_0;
2014 channel->dpll_ctrl_n = DPLL_CTRL_0;
2015 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2018 channel->dpll_freq = DPLL_FREQ_1;
2019 channel->dpll_n = DPLL_1;
2020 channel->hw_dpll_n = HW_DPLL_1;
2021 channel->dpll_phase = DPLL_PHASE_1;
2022 channel->dpll_ctrl_n = DPLL_CTRL_1;
2023 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2026 channel->dpll_freq = DPLL_FREQ_2;
2027 channel->dpll_n = DPLL_2;
2028 channel->hw_dpll_n = HW_DPLL_2;
2029 channel->dpll_phase = DPLL_PHASE_2;
2030 channel->dpll_ctrl_n = DPLL_CTRL_2;
2031 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2034 channel->dpll_freq = DPLL_FREQ_3;
2035 channel->dpll_n = DPLL_3;
2036 channel->hw_dpll_n = HW_DPLL_3;
2037 channel->dpll_phase = DPLL_PHASE_3;
2038 channel->dpll_ctrl_n = DPLL_CTRL_3;
2039 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2042 channel->dpll_freq = DPLL_FREQ_4;
2043 channel->dpll_n = DPLL_4;
2044 channel->hw_dpll_n = HW_DPLL_4;
2045 channel->dpll_phase = DPLL_PHASE_4;
2046 channel->dpll_ctrl_n = DPLL_CTRL_4;
2047 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2050 channel->dpll_freq = DPLL_FREQ_5;
2051 channel->dpll_n = DPLL_5;
2052 channel->hw_dpll_n = HW_DPLL_5;
2053 channel->dpll_phase = DPLL_PHASE_5;
2054 channel->dpll_ctrl_n = DPLL_CTRL_5;
2055 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2058 channel->dpll_freq = DPLL_FREQ_6;
2059 channel->dpll_n = DPLL_6;
2060 channel->hw_dpll_n = HW_DPLL_6;
2061 channel->dpll_phase = DPLL_PHASE_6;
2062 channel->dpll_ctrl_n = DPLL_CTRL_6;
2063 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2066 channel->dpll_freq = DPLL_FREQ_7;
2067 channel->dpll_n = DPLL_7;
2068 channel->hw_dpll_n = HW_DPLL_7;
2069 channel->dpll_phase = DPLL_PHASE_7;
2070 channel->dpll_ctrl_n = DPLL_CTRL_7;
2071 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2080 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2082 struct idtcm_channel *channel;
2085 if (!(index < MAX_TOD))
2088 channel = &idtcm->channel[index];
2090 /* Set pll addresses */
2091 err = configure_channel_pll(channel);
2095 /* Set tod addresses */
2098 channel->tod_read_primary = TOD_READ_PRIMARY_0;
2099 channel->tod_write = TOD_WRITE_0;
2100 channel->tod_n = TOD_0;
2103 channel->tod_read_primary = TOD_READ_PRIMARY_1;
2104 channel->tod_write = TOD_WRITE_1;
2105 channel->tod_n = TOD_1;
2108 channel->tod_read_primary = TOD_READ_PRIMARY_2;
2109 channel->tod_write = TOD_WRITE_2;
2110 channel->tod_n = TOD_2;
2113 channel->tod_read_primary = TOD_READ_PRIMARY_3;
2114 channel->tod_write = TOD_WRITE_3;
2115 channel->tod_n = TOD_3;
2121 channel->idtcm = idtcm;
2123 if (idtcm->deprecated)
2124 channel->caps = idtcm_caps_deprecated;
2126 channel->caps = idtcm_caps;
2128 snprintf(channel->caps.name, sizeof(channel->caps.name),
2129 "IDT CM TOD%u", index);
2131 if (!idtcm->deprecated) {
2132 err = idtcm_enable_tod_sync(channel);
2134 dev_err(&idtcm->client->dev,
2135 "Failed at line %d in func %s!\n",
2142 /* Sync pll mode with hardware */
2143 err = idtcm_get_pll_mode(channel, &channel->pll_mode);
2145 dev_err(&idtcm->client->dev,
2146 "Error: %s - Unable to read pll mode\n", __func__);
2150 err = idtcm_enable_tod(channel);
2152 dev_err(&idtcm->client->dev,
2153 "Failed at line %d in func %s!\n",
2159 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2161 if (IS_ERR(channel->ptp_clock)) {
2162 err = PTR_ERR(channel->ptp_clock);
2163 channel->ptp_clock = NULL;
2167 if (!channel->ptp_clock)
2170 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2171 index, channel->ptp_clock->index);
2176 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2179 struct idtcm_channel *channel;
2181 for (i = 0; i < MAX_TOD; i++) {
2183 channel = &idtcm->channel[i];
2185 if (channel->ptp_clock)
2186 ptp_clock_unregister(channel->ptp_clock);
2190 static void set_default_masks(struct idtcm *idtcm)
2192 idtcm->tod_mask = DEFAULT_TOD_MASK;
2194 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2195 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2196 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2197 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2199 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2200 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2201 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2202 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2205 static int idtcm_probe(struct i2c_client *client,
2206 const struct i2c_device_id *id)
2208 struct idtcm *idtcm;
2211 char *fmt = "Failed at %d in line %s with channel output %d!\n";
2213 /* Unused for now */
2216 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2221 idtcm->client = client;
2222 idtcm->page_offset = 0xff;
2223 idtcm->calculate_overhead_flag = 0;
2225 set_default_masks(idtcm);
2227 mutex_init(&idtcm->reg_lock);
2228 mutex_lock(&idtcm->reg_lock);
2230 idtcm_set_version_info(idtcm);
2232 err = idtcm_load_firmware(idtcm, &client->dev);
2235 dev_warn(&idtcm->client->dev,
2236 "loading firmware failed with %d\n", err);
2238 if (wait_for_boot_status_ready(idtcm))
2239 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0\n");
2241 if (idtcm->tod_mask) {
2242 for (i = 0; i < MAX_TOD; i++) {
2243 if (idtcm->tod_mask & (1 << i)) {
2244 err = idtcm_enable_channel(idtcm, i);
2246 dev_err(&idtcm->client->dev,
2256 dev_err(&idtcm->client->dev,
2257 "no PLLs flagged as PHCs, nothing to do\n");
2261 mutex_unlock(&idtcm->reg_lock);
2264 ptp_clock_unregister_all(idtcm);
2268 i2c_set_clientdata(client, idtcm);
2273 static int idtcm_remove(struct i2c_client *client)
2275 struct idtcm *idtcm = i2c_get_clientdata(client);
2277 ptp_clock_unregister_all(idtcm);
2279 mutex_destroy(&idtcm->reg_lock);
2285 static const struct of_device_id idtcm_dt_id[] = {
2286 { .compatible = "idt,8a34000" },
2287 { .compatible = "idt,8a34001" },
2288 { .compatible = "idt,8a34002" },
2289 { .compatible = "idt,8a34003" },
2290 { .compatible = "idt,8a34004" },
2291 { .compatible = "idt,8a34005" },
2292 { .compatible = "idt,8a34006" },
2293 { .compatible = "idt,8a34007" },
2294 { .compatible = "idt,8a34008" },
2295 { .compatible = "idt,8a34009" },
2296 { .compatible = "idt,8a34010" },
2297 { .compatible = "idt,8a34011" },
2298 { .compatible = "idt,8a34012" },
2299 { .compatible = "idt,8a34013" },
2300 { .compatible = "idt,8a34014" },
2301 { .compatible = "idt,8a34015" },
2302 { .compatible = "idt,8a34016" },
2303 { .compatible = "idt,8a34017" },
2304 { .compatible = "idt,8a34018" },
2305 { .compatible = "idt,8a34019" },
2306 { .compatible = "idt,8a34040" },
2307 { .compatible = "idt,8a34041" },
2308 { .compatible = "idt,8a34042" },
2309 { .compatible = "idt,8a34043" },
2310 { .compatible = "idt,8a34044" },
2311 { .compatible = "idt,8a34045" },
2312 { .compatible = "idt,8a34046" },
2313 { .compatible = "idt,8a34047" },
2314 { .compatible = "idt,8a34048" },
2315 { .compatible = "idt,8a34049" },
2318 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2321 static const struct i2c_device_id idtcm_i2c_id[] = {
2354 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2356 static struct i2c_driver idtcm_driver = {
2358 .of_match_table = of_match_ptr(idtcm_dt_id),
2361 .probe = idtcm_probe,
2362 .remove = idtcm_remove,
2363 .id_table = idtcm_i2c_id,
2366 module_i2c_driver(idtcm_driver);