drivers/ptp/ptp_clockmatrix.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
   4  * synchronization devices.
   5  *
   6  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
   7  */
   8 #include <linux/firmware.h>
   9 #include <linux/i2c.h>
  10 #include <linux/module.h>
  11 #include <linux/ptp_clock_kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/jiffies.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timekeeping.h>
  16 #include <linux/string.h>
  17
  18 #include "ptp_private.h"
  19 #include "ptp_clockmatrix.h"
  20
  21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
  22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
  23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  24 MODULE_VERSION("1.0");
  25 MODULE_LICENSE("GPL");
  26
  27 /*
  28  * The name of the firmware file to be loaded
  29  * over-rides any automatic selection
  30  */
  31 static char *firmware;
  32 module_param(firmware, charp, 0);
  33
  34 #define SETTIME_CORRECTION (0)
  35
  36 static int contains_full_configuration(const struct firmware *fw)
  37 {
  38         s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES;
  39         struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
  40         s32 count = 0;
  41         u16 regaddr;
  42         u8 loaddr;
  43         s32 len;
  44
  45         /* If the firmware contains 'full configuration' SM_RESET can be used
  46          * to ensure proper configuration.
  47          *
  48          * Full configuration is defined as the number of programmable
  49          * bytes within the configuration range minus page offset addr range.
  50          */
  51         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
  52                 regaddr = rec->hiaddr << 8;
  53                 regaddr |= rec->loaddr;
  54
  55                 loaddr = rec->loaddr;
  56
  57                 rec++;
  58
  59                 /* Top (status registers) and bottom are read-only */
  60                 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
  61                         continue;
  62
  63                 /* Page size 128, last 4 bytes of page skipped */
  64                 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
  65                         continue;
  66
  67                 count++;
  68         }
  69
  70         return (count >= full_count);
  71 }
  72
  73 static int char_array_to_timespec(u8 *buf,
  74                                   u8 count,
  75                                   struct timespec64 *ts)
  76 {
  77         u8 i;
  78         u64 nsec;
  79         time64_t sec;
  80
  81         if (count < TOD_BYTE_COUNT)
  82                 return 1;
  83
  84         /* Sub-nanoseconds are in buf[0]. */
  85         nsec = buf[4];
  86         for (i = 0; i < 3; i++) {
  87                 nsec <<= 8;
  88                 nsec |= buf[3 - i];
  89         }
  90
  91         sec = buf[10];
  92         for (i = 0; i < 5; i++) {
  93                 sec <<= 8;
  94                 sec |= buf[9 - i];
  95         }
  96
  97         ts->tv_sec = sec;
  98         ts->tv_nsec = nsec;
  99
 100         return 0;
 101 }
 102
 103 static int timespec_to_char_array(struct timespec64 const *ts,
 104                                   u8 *buf,
 105                                   u8 count)
 106 {
 107         u8 i;
 108         s32 nsec;
 109         time64_t sec;
 110
 111         if (count < TOD_BYTE_COUNT)
 112                 return 1;
 113
 114         nsec = ts->tv_nsec;
 115         sec = ts->tv_sec;
 116
 117         /* Sub-nanoseconds are in buf[0]. */
 118         buf[0] = 0;
 119         for (i = 1; i < 5; i++) {
 120                 buf[i] = nsec & 0xff;
 121                 nsec >>= 8;
 122         }
 123
 124         for (i = 5; i < TOD_BYTE_COUNT; i++) {
 125
 126                 buf[i] = sec & 0xff;
 127                 sec >>= 8;
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int idtcm_strverscmp(const char *version1, const char *version2)
 134 {
 135         u8 ver1[3], ver2[3];
 136         int i;
 137
 138         if (sscanf(version1, "%hhu.%hhu.%hhu",
 139                    &ver1[0], &ver1[1], &ver1[2]) != 3)
 140                 return -1;
 141         if (sscanf(version2, "%hhu.%hhu.%hhu",
 142                    &ver2[0], &ver2[1], &ver2[2]) != 3)
 143                 return -1;
 144
 145         for (i = 0; i < 3; i++) {
 146                 if (ver1[i] > ver2[i])
 147                         return 1;
 148                 if (ver1[i] < ver2[i])
 149                         return -1;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int idtcm_xfer_read(struct idtcm *idtcm,
 156                            u8 regaddr,
 157                            u8 *buf,
 158                            u16 count)
 159 {
 160         struct i2c_client *client = idtcm->client;
 161         struct i2c_msg msg[2];
 162         int cnt;
 163         char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
 164
 165         msg[0].addr = client->addr;
 166         msg[0].flags = 0;
 167         msg[0].len = 1;
 168         msg[0].buf = &regaddr;
 169
 170         msg[1].addr = client->addr;
 171         msg[1].flags = I2C_M_RD;
 172         msg[1].len = count;
 173         msg[1].buf = buf;
 174
 175         cnt = i2c_transfer(client->adapter, msg, 2);
 176
 177         if (cnt < 0) {
 178                 dev_err(&client->dev,
 179                         fmt,
 180                         __LINE__,
 181                         __func__,
 182                         regaddr);
 183                 return cnt;
 184         } else if (cnt != 2) {
 185                 dev_err(&client->dev,
 186                         "i2c_transfer sent only %d of %d messages\n", cnt, 2);
 187                 return -EIO;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int idtcm_xfer_write(struct idtcm *idtcm,
 194                             u8 regaddr,
 195                             u8 *buf,
 196                             u16 count)
 197 {
 198         struct i2c_client *client = idtcm->client;
 199         /* we add 1 byte for device register */
 200         u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
 201         int cnt;
 202         char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
 203
 204         if (count > IDTCM_MAX_WRITE_COUNT)
 205                 return -EINVAL;
 206
 207         msg[0] = regaddr;
 208         memcpy(&msg[1], buf, count);
 209
 210         cnt = i2c_master_send(client, msg, count + 1);
 211
 212         if (cnt < 0) {
 213                 dev_err(&client->dev,
 214                         fmt,
 215                         __LINE__,
 216                         __func__,
 217                         regaddr);
 218                 return cnt;
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
 225 {
 226         u8 buf[4];
 227         int err;
 228
 229         if (idtcm->page_offset == val)
 230                 return 0;
 231
 232         buf[0] = 0x0;
 233         buf[1] = val;
 234         buf[2] = 0x10;
 235         buf[3] = 0x20;
 236
 237         err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
 238
 239         if (err) {
 240                 idtcm->page_offset = 0xff;
 241                 dev_err(&idtcm->client->dev, "failed to set page offset\n");
 242         } else {
 243                 idtcm->page_offset = val;
 244         }
 245
 246         return err;
 247 }
 248
 249 static int _idtcm_rdwr(struct idtcm *idtcm,
 250                        u16 regaddr,
 251                        u8 *buf,
 252                        u16 count,
 253                        bool write)
 254 {
 255         u8 hi;
 256         u8 lo;
 257         int err;
 258
 259         hi = (regaddr >> 8) & 0xff;
 260         lo = regaddr & 0xff;
 261
 262         err = idtcm_page_offset(idtcm, hi);
 263
 264         if (err)
 265                 return err;
 266
 267         if (write)
 268                 return idtcm_xfer_write(idtcm, lo, buf, count);
 269
 270         return idtcm_xfer_read(idtcm, lo, buf, count);
 271 }
 272
 273 static int idtcm_read(struct idtcm *idtcm,
 274                       u16 module,
 275                       u16 regaddr,
 276                       u8 *buf,
 277                       u16 count)
 278 {
 279         return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
 280 }
 281
 282 static int idtcm_write(struct idtcm *idtcm,
 283                        u16 module,
 284                        u16 regaddr,
 285                        u8 *buf,
 286                        u16 count)
 287 {
 288         return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
 289 }
 290
 291 static int clear_boot_status(struct idtcm *idtcm)
 292 {
 293         int err;
 294         u8 buf[4] = {0};
 295
 296         err = idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
 297
 298         return err;
 299 }
 300
 301 static int read_boot_status(struct idtcm *idtcm, u32 *status)
 302 {
 303         int err;
 304         u8 buf[4] = {0};
 305
 306         err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
 307
 308         *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
 309
 310         return err;
 311 }
 312
 313 static int wait_for_boot_status_ready(struct idtcm *idtcm)
 314 {
 315         u32 status = 0;
 316         u8 i = 30;      /* 30 * 100ms = 3s */
 317         int err;
 318
 319         do {
 320                 err = read_boot_status(idtcm, &status);
 321
 322                 if (err)
 323                         return err;
 324
 325                 if (status == 0xA0)
 326                         return 0;
 327
 328                 msleep(100);
 329                 i--;
 330
 331         } while (i);
 332
 333         dev_warn(&idtcm->client->dev, "%s timed out\n", __func__);
 334
 335         return -EBUSY;
 336 }
 337
 338 static int _idtcm_gettime(struct idtcm_channel *channel,
 339                           struct timespec64 *ts)
 340 {
 341         struct idtcm *idtcm = channel->idtcm;
 342         u8 buf[TOD_BYTE_COUNT];
 343         u8 timeout = 10;
 344         u8 trigger;
 345         int err;
 346
 347         err = idtcm_read(idtcm, channel->tod_read_primary,
 348                          TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
 349         if (err)
 350                 return err;
 351
 352         trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
 353         trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
 354         trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
 355
 356         err = idtcm_write(idtcm, channel->tod_read_primary,
 357                           TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
 358         if (err)
 359                 return err;
 360
 361         /* wait trigger to be 0 */
 362         while (trigger & TOD_READ_TRIGGER_MASK) {
 363
 364                 if (idtcm->calculate_overhead_flag)
 365                         idtcm->start_time = ktime_get_raw();
 366
 367                 err = idtcm_read(idtcm, channel->tod_read_primary,
 368                                  TOD_READ_PRIMARY_CMD, &trigger,
 369                                  sizeof(trigger));
 370
 371                 if (err)
 372                         return err;
 373
 374                 if (--timeout == 0)
 375                         return -EIO;
 376         }
 377
 378         err = idtcm_read(idtcm, channel->tod_read_primary,
 379                          TOD_READ_PRIMARY, buf, sizeof(buf));
 380
 381         if (err)
 382                 return err;
 383
 384         err = char_array_to_timespec(buf, sizeof(buf), ts);
 385
 386         return err;
 387 }
 388
 389 static int _sync_pll_output(struct idtcm *idtcm,
 390                             u8 pll,
 391                             u8 sync_src,
 392                             u8 qn,
 393                             u8 qn_plus_1)
 394 {
 395         int err;
 396         u8 val;
 397         u16 sync_ctrl0;
 398         u16 sync_ctrl1;
 399         u8 temp;
 400
 401         if ((qn == 0) && (qn_plus_1 == 0))
 402                 return 0;
 403
 404         switch (pll) {
 405         case 0:
 406                 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
 407                 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
 408                 break;
 409         case 1:
 410                 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
 411                 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
 412                 break;
 413         case 2:
 414                 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
 415                 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
 416                 break;
 417         case 3:
 418                 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
 419                 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
 420                 break;
 421         case 4:
 422                 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
 423                 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
 424                 break;
 425         case 5:
 426                 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
 427                 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
 428                 break;
 429         case 6:
 430                 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
 431                 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
 432                 break;
 433         case 7:
 434                 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
 435                 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
 436                 break;
 437         default:
 438                 return -EINVAL;
 439         }
 440
 441         val = SYNCTRL1_MASTER_SYNC_RST;
 442
 443         /* Place master sync in reset */
 444         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 445         if (err)
 446                 return err;
 447
 448         err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
 449         if (err)
 450                 return err;
 451
 452         /* Set sync trigger mask */
 453         val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
 454
 455         if (qn)
 456                 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
 457
 458         if (qn_plus_1)
 459                 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
 460
 461         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 462         if (err)
 463                 return err;
 464
 465         /* PLL5 can have OUT8 as second additional output. */
 466         if ((pll == 5) && (qn_plus_1 != 0)) {
 467                 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
 468                                  &temp, sizeof(temp));
 469                 if (err)
 470                         return err;
 471
 472                 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
 473
 474                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
 475                                   &temp, sizeof(temp));
 476                 if (err)
 477                         return err;
 478
 479                 temp |= Q9_TO_Q8_SYNC_TRIG;
 480
 481                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
 482                                   &temp, sizeof(temp));
 483                 if (err)
 484                         return err;
 485         }
 486
 487         /* PLL6 can have OUT11 as second additional output. */
 488         if ((pll == 6) && (qn_plus_1 != 0)) {
 489                 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
 490                                  &temp, sizeof(temp));
 491                 if (err)
 492                         return err;
 493
 494                 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
 495
 496                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
 497                                   &temp, sizeof(temp));
 498                 if (err)
 499                         return err;
 500
 501                 temp |= Q10_TO_Q11_SYNC_TRIG;
 502
 503                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
 504                                   &temp, sizeof(temp));
 505                 if (err)
 506                         return err;
 507         }
 508
 509         /* Place master sync out of reset */
 510         val &= ~(SYNCTRL1_MASTER_SYNC_RST);
 511         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 512
 513         return err;
 514 }
 515
 516 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
 517 {
 518         int err = 0;
 519
 520         switch (tod_addr) {
 521         case TOD_0:
 522                 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
 523                 break;
 524         case TOD_1:
 525                 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
 526                 break;
 527         case TOD_2:
 528                 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
 529                 break;
 530         case TOD_3:
 531                 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
 532                 break;
 533         default:
 534                 err = -EINVAL;
 535         }
 536
 537         return err;
 538 }
 539
 540 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
 541 {
 542         struct idtcm *idtcm = channel->idtcm;
 543
 544         u8 pll;
 545         u8 sync_src;
 546         u8 qn;
 547         u8 qn_plus_1;
 548         int err = 0;
 549         u8 out8_mux = 0;
 550         u8 out11_mux = 0;
 551         u8 temp;
 552
 553         u16 output_mask = channel->output_mask;
 554
 555         err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
 556         if (err)
 557                 return err;
 558
 559         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
 560                          &temp, sizeof(temp));
 561         if (err)
 562                 return err;
 563
 564         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
 565             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
 566                 out8_mux = 1;
 567
 568         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
 569                          &temp, sizeof(temp));
 570         if (err)
 571                 return err;
 572
 573         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
 574             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
 575                 out11_mux = 1;
 576
 577         for (pll = 0; pll < 8; pll++) {
 578                 qn = 0;
 579                 qn_plus_1 = 0;
 580
 581                 if (pll < 4) {
 582                         /* First 4 pll has 2 outputs */
 583                         qn = output_mask & 0x1;
 584                         output_mask = output_mask >> 1;
 585                         qn_plus_1 = output_mask & 0x1;
 586                         output_mask = output_mask >> 1;
 587                 } else if (pll == 4) {
 588                         if (out8_mux == 0) {
 589                                 qn = output_mask & 0x1;
 590                                 output_mask = output_mask >> 1;
 591                         }
 592                 } else if (pll == 5) {
 593                         if (out8_mux) {
 594                                 qn_plus_1 = output_mask & 0x1;
 595                                 output_mask = output_mask >> 1;
 596                         }
 597                         qn = output_mask & 0x1;
 598                         output_mask = output_mask >> 1;
 599                 } else if (pll == 6) {
 600                         qn = output_mask & 0x1;
 601                         output_mask = output_mask >> 1;
 602                         if (out11_mux) {
 603                                 qn_plus_1 = output_mask & 0x1;
 604                                 output_mask = output_mask >> 1;
 605                         }
 606                 } else if (pll == 7) {
 607                         if (out11_mux == 0) {
 608                                 qn = output_mask & 0x1;
 609                                 output_mask = output_mask >> 1;
 610                         }
 611                 }
 612
 613                 if ((qn != 0) || (qn_plus_1 != 0))
 614                         err = _sync_pll_output(idtcm, pll, sync_src, qn,
 615                                                qn_plus_1);
 616
 617                 if (err)
 618                         return err;
 619         }
 620
 621         return err;
 622 }
 623
 624 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
 625                                struct timespec64 const *ts,
 626                                enum hw_tod_write_trig_sel wr_trig)
 627 {
 628         struct idtcm *idtcm = channel->idtcm;
 629
 630         u8 buf[TOD_BYTE_COUNT];
 631         u8 cmd;
 632         int err;
 633         struct timespec64 local_ts = *ts;
 634         s64 total_overhead_ns;
 635
 636         /* Configure HW TOD write trigger. */
 637         err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 638                          &cmd, sizeof(cmd));
 639
 640         if (err)
 641                 return err;
 642
 643         cmd &= ~(0x0f);
 644         cmd |= wr_trig | 0x08;
 645
 646         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 647                           &cmd, sizeof(cmd));
 648
 649         if (err)
 650                 return err;
 651
 652         if (wr_trig  != HW_TOD_WR_TRIG_SEL_MSB) {
 653
 654                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 655
 656                 if (err)
 657                         return err;
 658
 659                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 660                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 661
 662                 if (err)
 663                         return err;
 664         }
 665
 666         /* ARM HW TOD write trigger. */
 667         cmd &= ~(0x08);
 668
 669         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 670                           &cmd, sizeof(cmd));
 671
 672         if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
 673
 674                 if (idtcm->calculate_overhead_flag) {
 675                         /* Assumption: I2C @ 400KHz */
 676                         ktime_t diff = ktime_sub(ktime_get_raw(),
 677                                                  idtcm->start_time);
 678                         total_overhead_ns =  ktime_to_ns(diff)
 679                                              + idtcm->tod_write_overhead_ns
 680                                              + SETTIME_CORRECTION;
 681
 682                         timespec64_add_ns(&local_ts, total_overhead_ns);
 683
 684                         idtcm->calculate_overhead_flag = 0;
 685                 }
 686
 687                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 688
 689                 if (err)
 690                         return err;
 691
 692                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 693                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 694         }
 695
 696         return err;
 697 }
 698
 699 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
 700                                     struct timespec64 const *ts,
 701                                     enum scsr_tod_write_trig_sel wr_trig,
 702                                     enum scsr_tod_write_type_sel wr_type)
 703 {
 704         struct idtcm *idtcm = channel->idtcm;
 705         unsigned char buf[TOD_BYTE_COUNT], cmd;
 706         struct timespec64 local_ts = *ts;
 707         int err, count = 0;
 708
 709         timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
 710
 711         err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 712
 713         if (err)
 714                 return err;
 715
 716         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
 717                           buf, sizeof(buf));
 718         if (err)
 719                 return err;
 720
 721         /* Trigger the write operation. */
 722         err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
 723                          &cmd, sizeof(cmd));
 724         if (err)
 725                 return err;
 726
 727         cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
 728         cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
 729         cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
 730         cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
 731
 732         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
 733                            &cmd, sizeof(cmd));
 734         if (err)
 735                 return err;
 736
 737         /* Wait for the operation to complete. */
 738         while (1) {
 739                 /* pps trigger takes up to 1 sec to complete */
 740                 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
 741                         msleep(50);
 742
 743                 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
 744                                  &cmd, sizeof(cmd));
 745                 if (err)
 746                         return err;
 747
 748                 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
 749                         break;
 750
 751                 if (++count > 20) {
 752                         dev_err(&idtcm->client->dev,
 753                                 "Timed out waiting for the write counter\n");
 754                         return -EIO;
 755                 }
 756         }
 757
 758         return 0;
 759 }
 760
 761 static int get_output_base_addr(u8 outn)
 762 {
 763         int base;
 764
 765         switch (outn) {
 766         case 0:
 767                 base = OUTPUT_0;
 768                 break;
 769         case 1:
 770                 base = OUTPUT_1;
 771                 break;
 772         case 2:
 773                 base = OUTPUT_2;
 774                 break;
 775         case 3:
 776                 base = OUTPUT_3;
 777                 break;
 778         case 4:
 779                 base = OUTPUT_4;
 780                 break;
 781         case 5:
 782                 base = OUTPUT_5;
 783                 break;
 784         case 6:
 785                 base = OUTPUT_6;
 786                 break;
 787         case 7:
 788                 base = OUTPUT_7;
 789                 break;
 790         case 8:
 791                 base = OUTPUT_8;
 792                 break;
 793         case 9:
 794                 base = OUTPUT_9;
 795                 break;
 796         case 10:
 797                 base = OUTPUT_10;
 798                 break;
 799         case 11:
 800                 base = OUTPUT_11;
 801                 break;
 802         default:
 803                 base = -EINVAL;
 804         }
 805
 806         return base;
 807 }
 808
 809 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
 810                                      struct timespec64 const *ts)
 811 {
 812         struct idtcm *idtcm = channel->idtcm;
 813         int err;
 814
 815         err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
 816
 817         if (err) {
 818                 dev_err(&idtcm->client->dev,
 819                         "%s: Set HW ToD failed\n", __func__);
 820                 return err;
 821         }
 822
 823         return idtcm_sync_pps_output(channel);
 824 }
 825
 826 static int _idtcm_settime(struct idtcm_channel *channel,
 827                           struct timespec64 const *ts,
 828                           enum scsr_tod_write_type_sel wr_type)
 829 {
 830         return _idtcm_set_dpll_scsr_tod(channel, ts,
 831                                         SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
 832                                         wr_type);
 833 }
 834
 835 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
 836                                           s32 offset_ns)
 837 {
 838         int err;
 839         int i;
 840         struct idtcm *idtcm = channel->idtcm;
 841
 842         u8 buf[4];
 843
 844         for (i = 0; i < 4; i++) {
 845                 buf[i] = 0xff & (offset_ns);
 846                 offset_ns >>= 8;
 847         }
 848
 849         err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
 850                           buf, sizeof(buf));
 851
 852         return err;
 853 }
 854
 855 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
 856                                                u32 max_ffo_ppb)
 857 {
 858         int err;
 859         u8 i;
 860         struct idtcm *idtcm = channel->idtcm;
 861
 862         u8 buf[3];
 863
 864         if (max_ffo_ppb & 0xff000000)
 865                 max_ffo_ppb = 0;
 866
 867         for (i = 0; i < 3; i++) {
 868                 buf[i] = 0xff & (max_ffo_ppb);
 869                 max_ffo_ppb >>= 8;
 870         }
 871
 872         err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
 873                           PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
 874
 875         return err;
 876 }
 877
 878 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
 879 {
 880         int err;
 881         struct idtcm *idtcm = channel->idtcm;
 882
 883         u8 buf;
 884
 885         err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
 886                          &buf, sizeof(buf));
 887
 888         if (err)
 889                 return err;
 890
 891         if (buf == 0) {
 892                 buf = 0x01;
 893                 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
 894                                   PULL_IN_CTRL, &buf, sizeof(buf));
 895         } else {
 896                 err = -EBUSY;
 897         }
 898
 899         return err;
 900 }
 901
 902 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
 903                                   s32 offset_ns,
 904                                   u32 max_ffo_ppb)
 905 {
 906         int err;
 907
 908         err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
 909
 910         if (err)
 911                 return err;
 912
 913         err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
 914
 915         if (err)
 916                 return err;
 917
 918         err = idtcm_start_phase_pull_in(channel);
 919
 920         return err;
 921 }
 922
 923 static int set_tod_write_overhead(struct idtcm_channel *channel)
 924 {
 925         struct idtcm *idtcm = channel->idtcm;
 926         s64 current_ns = 0;
 927         s64 lowest_ns = 0;
 928         int err;
 929         u8 i;
 930
 931         ktime_t start;
 932         ktime_t stop;
 933         ktime_t diff;
 934
 935         char buf[TOD_BYTE_COUNT] = {0};
 936
 937         /* Set page offset */
 938         idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
 939                     buf, sizeof(buf));
 940
 941         for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
 942
 943                 start = ktime_get_raw();
 944
 945                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 946                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 947
 948                 if (err)
 949                         return err;
 950
 951                 stop = ktime_get_raw();
 952
 953                 diff = ktime_sub(stop, start);
 954
 955                 current_ns = ktime_to_ns(diff);
 956
 957                 if (i == 0) {
 958                         lowest_ns = current_ns;
 959                 } else {
 960                         if (current_ns < lowest_ns)
 961                                 lowest_ns = current_ns;
 962                 }
 963         }
 964
 965         idtcm->tod_write_overhead_ns = lowest_ns;
 966
 967         return err;
 968 }
 969
 970 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
 971 {
 972         int err;
 973         struct idtcm *idtcm = channel->idtcm;
 974         struct timespec64 ts;
 975         s64 now;
 976
 977         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
 978                 err = idtcm_do_phase_pull_in(channel, delta, 0);
 979         } else {
 980                 idtcm->calculate_overhead_flag = 1;
 981
 982                 err = set_tod_write_overhead(channel);
 983
 984                 if (err)
 985                         return err;
 986
 987                 err = _idtcm_gettime(channel, &ts);
 988
 989                 if (err)
 990                         return err;
 991
 992                 now = timespec64_to_ns(&ts);
 993                 now += delta;
 994
 995                 ts = ns_to_timespec64(now);
 996
 997                 err = _idtcm_settime_deprecated(channel, &ts);
 998         }
 999
1000         return err;
1001 }
1002
1003 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1004 {
1005         u8 byte = SM_RESET_CMD;
1006         u32 status = 0;
1007         int err;
1008         u8 i;
1009
1010         clear_boot_status(idtcm);
1011
1012         err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
1013
1014         if (!err) {
1015                 for (i = 0; i < 30; i++) {
1016                         msleep_interruptible(100);
1017                         read_boot_status(idtcm, &status);
1018
1019                         if (status == 0xA0) {
1020                                 dev_dbg(&idtcm->client->dev,
1021                                         "SM_RESET completed in %d ms\n",
1022                                         i * 100);
1023                                 break;
1024                         }
1025                 }
1026
1027                 if (!status)
1028                         dev_err(&idtcm->client->dev, "Timed out waiting for CM_RESET to complete\n");
1029         }
1030
1031         return err;
1032 }
1033
1034 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1035 {
1036         return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1037 }
1038
1039 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1040 {
1041         int err;
1042         u8 buf[2] = {0};
1043
1044         err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1045
1046         *product_id = (buf[1] << 8) | buf[0];
1047
1048         return err;
1049 }
1050
1051 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1052 {
1053         int err;
1054         u8 buf = 0;
1055
1056         err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1057
1058         *major = buf >> 1;
1059
1060         return err;
1061 }
1062
1063 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1064 {
1065         return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1066 }
1067
1068 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1069 {
1070         return idtcm_read(idtcm,
1071                           GENERAL_STATUS,
1072                           HOTFIX_REL,
1073                           hotfix,
1074                           sizeof(u8));
1075 }
1076
1077 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1078                                              u8 *config_select)
1079 {
1080         return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1081                           config_select, sizeof(u8));
1082 }
1083
1084 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1085 {
1086         int err = 0;
1087
1088         switch (addr) {
1089         case TOD0_OUT_ALIGN_MASK_ADDR:
1090                 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1091                 break;
1092         case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1093                 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1094                 break;
1095         case TOD1_OUT_ALIGN_MASK_ADDR:
1096                 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1097                 break;
1098         case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1099                 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1100                 break;
1101         case TOD2_OUT_ALIGN_MASK_ADDR:
1102                 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1103                 break;
1104         case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1105                 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1106                 break;
1107         case TOD3_OUT_ALIGN_MASK_ADDR:
1108                 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1109                 break;
1110         case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1111                 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1112                 break;
1113         default:
1114                 err = -EFAULT; /* Bad address */;
1115                 break;
1116         }
1117
1118         return err;
1119 }
1120
1121 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1122 {
1123         if (index >= MAX_TOD) {
1124                 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
1125                 return -EINVAL;
1126         }
1127
1128         if (pll >= MAX_PLL) {
1129                 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
1130                 return -EINVAL;
1131         }
1132
1133         idtcm->channel[index].pll = pll;
1134
1135         return 0;
1136 }
1137
1138 static int check_and_set_masks(struct idtcm *idtcm,
1139                                u16 regaddr,
1140                                u8 val)
1141 {
1142         int err = 0;
1143
1144         switch (regaddr) {
1145         case TOD_MASK_ADDR:
1146                 if ((val & 0xf0) || !(val & 0x0f)) {
1147                         dev_err(&idtcm->client->dev,
1148                                 "Invalid TOD mask 0x%hhx\n", val);
1149                         err = -EINVAL;
1150                 } else {
1151                         idtcm->tod_mask = val;
1152                 }
1153                 break;
1154         case TOD0_PTP_PLL_ADDR:
1155                 err = set_tod_ptp_pll(idtcm, 0, val);
1156                 break;
1157         case TOD1_PTP_PLL_ADDR:
1158                 err = set_tod_ptp_pll(idtcm, 1, val);
1159                 break;
1160         case TOD2_PTP_PLL_ADDR:
1161                 err = set_tod_ptp_pll(idtcm, 2, val);
1162                 break;
1163         case TOD3_PTP_PLL_ADDR:
1164                 err = set_tod_ptp_pll(idtcm, 3, val);
1165                 break;
1166         default:
1167                 err = set_pll_output_mask(idtcm, regaddr, val);
1168                 break;
1169         }
1170
1171         return err;
1172 }
1173
1174 static void display_pll_and_masks(struct idtcm *idtcm)
1175 {
1176         u8 i;
1177         u8 mask;
1178
1179         dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
1180
1181         for (i = 0; i < MAX_TOD; i++) {
1182                 mask = 1 << i;
1183
1184                 if (mask & idtcm->tod_mask)
1185                         dev_dbg(&idtcm->client->dev,
1186                                 "TOD%d pll = %d    output_mask = 0x%04x\n",
1187                                 i, idtcm->channel[i].pll,
1188                                 idtcm->channel[i].output_mask);
1189         }
1190 }
1191
1192 static int idtcm_load_firmware(struct idtcm *idtcm,
1193                                struct device *dev)
1194 {
1195         char fname[128] = FW_FILENAME;
1196         const struct firmware *fw;
1197         struct idtcm_fwrc *rec;
1198         u32 regaddr;
1199         int err;
1200         s32 len;
1201         u8 val;
1202         u8 loaddr;
1203
1204         if (firmware) /* module parameter */
1205                 snprintf(fname, sizeof(fname), "%s", firmware);
1206
1207         dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
1208
1209         err = request_firmware(&fw, fname, dev);
1210
1211         if (err) {
1212                 dev_err(&idtcm->client->dev,
1213                         "Failed at line %d in func %s!\n",
1214                         __LINE__,
1215                         __func__);
1216                 return err;
1217         }
1218
1219         dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1220
1221         rec = (struct idtcm_fwrc *) fw->data;
1222
1223         if (contains_full_configuration(fw))
1224                 idtcm_state_machine_reset(idtcm);
1225
1226         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1227
1228                 if (rec->reserved) {
1229                         dev_err(&idtcm->client->dev,
1230                                 "bad firmware, reserved field non-zero\n");
1231                         err = -EINVAL;
1232                 } else {
1233                         regaddr = rec->hiaddr << 8;
1234                         regaddr |= rec->loaddr;
1235
1236                         val = rec->value;
1237                         loaddr = rec->loaddr;
1238
1239                         rec++;
1240
1241                         err = check_and_set_masks(idtcm, regaddr, val);
1242                 }
1243
1244                 if (err != -EINVAL) {
1245                         err = 0;
1246
1247                         /* Top (status registers) and bottom are read-only */
1248                         if ((regaddr < GPIO_USER_CONTROL)
1249                             || (regaddr >= SCRATCH))
1250                                 continue;
1251
1252                         /* Page size 128, last 4 bytes of page skipped */
1253                         if (((loaddr > 0x7b) && (loaddr <= 0x7f))
1254                              || loaddr > 0xfb)
1255                                 continue;
1256
1257                         err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1258                 }
1259
1260                 if (err)
1261                         goto out;
1262         }
1263
1264         display_pll_and_masks(idtcm);
1265
1266 out:
1267         release_firmware(fw);
1268         return err;
1269 }
1270
1271 static int idtcm_output_enable(struct idtcm_channel *channel,
1272                                bool enable, unsigned int outn)
1273 {
1274         struct idtcm *idtcm = channel->idtcm;
1275         int base;
1276         int err;
1277         u8 val;
1278
1279         base = get_output_base_addr(outn);
1280
1281         if (!(base > 0)) {
1282                 dev_err(&idtcm->client->dev,
1283                         "%s - Unsupported out%d", __func__, outn);
1284                 return base;
1285         }
1286
1287         err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1288
1289         if (err)
1290                 return err;
1291
1292         if (enable)
1293                 val |= SQUELCH_DISABLE;
1294         else
1295                 val &= ~SQUELCH_DISABLE;
1296
1297         return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1298 }
1299
1300 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1301                                     bool enable)
1302 {
1303         u16 mask;
1304         int err;
1305         u8 outn;
1306
1307         mask = channel->output_mask;
1308         outn = 0;
1309
1310         while (mask) {
1311
1312                 if (mask & 0x1) {
1313
1314                         err = idtcm_output_enable(channel, enable, outn);
1315
1316                         if (err)
1317                                 return err;
1318                 }
1319
1320                 mask >>= 0x1;
1321                 outn++;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int idtcm_perout_enable(struct idtcm_channel *channel,
1328                                bool enable,
1329                                struct ptp_perout_request *perout)
1330 {
1331         unsigned int flags = perout->flags;
1332
1333         if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1334                 return idtcm_output_mask_enable(channel, enable);
1335
1336         /* Enable/disable individual output instead */
1337         return idtcm_output_enable(channel, enable, perout->index);
1338 }
1339
1340 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1341                               enum pll_mode *pll_mode)
1342 {
1343         struct idtcm *idtcm = channel->idtcm;
1344         int err;
1345         u8 dpll_mode;
1346
1347         err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1348                          &dpll_mode, sizeof(dpll_mode));
1349         if (err)
1350                 return err;
1351
1352         *pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1353
1354         return 0;
1355 }
1356
1357 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1358                               enum pll_mode pll_mode)
1359 {
1360         struct idtcm *idtcm = channel->idtcm;
1361         int err;
1362         u8 dpll_mode;
1363
1364         err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1365                          &dpll_mode, sizeof(dpll_mode));
1366         if (err)
1367                 return err;
1368
1369         dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1370
1371         dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1372
1373         channel->pll_mode = pll_mode;
1374
1375         err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1376                           &dpll_mode, sizeof(dpll_mode));
1377         if (err)
1378                 return err;
1379
1380         return 0;
1381 }
1382
1383 /* PTP Hardware Clock interface */
1384
1385 /**
1386  * @brief Maximum absolute value for write phase offset in picoseconds
1387  *
1388  * Destination signed register is 32-bit register in resolution of 50ps
1389  *
1390  * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1391  */
1392 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1393 {
1394         struct idtcm *idtcm = channel->idtcm;
1395
1396         int err;
1397         u8 i;
1398         u8 buf[4] = {0};
1399         s32 phase_50ps;
1400         s64 offset_ps;
1401
1402         if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1403
1404                 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1405
1406                 if (err)
1407                         return err;
1408         }
1409
1410         offset_ps = (s64)delta_ns * 1000;
1411
1412         /*
1413          * Check for 32-bit signed max * 50:
1414          *
1415          * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1416          */
1417         if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1418                 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1419         else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1420                 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1421
1422         phase_50ps = div_s64(offset_ps, 50);
1423
1424         for (i = 0; i < 4; i++) {
1425                 buf[i] = phase_50ps & 0xff;
1426                 phase_50ps >>= 8;
1427         }
1428
1429         err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1430                           buf, sizeof(buf));
1431
1432         return err;
1433 }
1434
1435 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1436 {
1437         struct idtcm *idtcm = channel->idtcm;
1438         u8 i;
1439         int err;
1440         u8 buf[6] = {0};
1441         s64 fcw;
1442
1443         if (channel->pll_mode  != PLL_MODE_WRITE_FREQUENCY) {
1444                 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1445                 if (err)
1446                         return err;
1447         }
1448
1449         /*
1450          * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1451          *
1452          * adjfreq:
1453          *       ppb * 10^9
1454          * FCW = ----------
1455          *          111
1456          *
1457          * adjfine:
1458          *       ppm_16 * 5^12
1459          * FCW = -------------
1460          *         111 * 2^4
1461          */
1462
1463         /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1464         fcw = scaled_ppm * 244140625ULL;
1465
1466         fcw = div_s64(fcw, 1776);
1467
1468         for (i = 0; i < 6; i++) {
1469                 buf[i] = fcw & 0xff;
1470                 fcw >>= 8;
1471         }
1472
1473         err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1474                           buf, sizeof(buf));
1475
1476         return err;
1477 }
1478
1479 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1480 {
1481         struct idtcm_channel *channel =
1482                 container_of(ptp, struct idtcm_channel, caps);
1483         struct idtcm *idtcm = channel->idtcm;
1484         int err;
1485
1486         mutex_lock(&idtcm->reg_lock);
1487
1488         err = _idtcm_gettime(channel, ts);
1489
1490         if (err)
1491                 dev_err(&idtcm->client->dev,
1492                         "Failed at line %d in func %s!\n",
1493                         __LINE__,
1494                         __func__);
1495
1496         mutex_unlock(&idtcm->reg_lock);
1497
1498         return err;
1499 }
1500
1501 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1502                                     const struct timespec64 *ts)
1503 {
1504         struct idtcm_channel *channel =
1505                 container_of(ptp, struct idtcm_channel, caps);
1506         struct idtcm *idtcm = channel->idtcm;
1507         int err;
1508
1509         mutex_lock(&idtcm->reg_lock);
1510
1511         err = _idtcm_settime_deprecated(channel, ts);
1512
1513         if (err)
1514                 dev_err(&idtcm->client->dev,
1515                         "Failed at line %d in func %s!\n",
1516                         __LINE__,
1517                         __func__);
1518
1519         mutex_unlock(&idtcm->reg_lock);
1520
1521         return err;
1522 }
1523
1524 static int idtcm_settime(struct ptp_clock_info *ptp,
1525                          const struct timespec64 *ts)
1526 {
1527         struct idtcm_channel *channel =
1528                 container_of(ptp, struct idtcm_channel, caps);
1529         struct idtcm *idtcm = channel->idtcm;
1530         int err;
1531
1532         mutex_lock(&idtcm->reg_lock);
1533
1534         err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1535
1536         if (err)
1537                 dev_err(&idtcm->client->dev,
1538                         "Failed at line %d in func %s!\n",
1539                         __LINE__,
1540                         __func__);
1541
1542         mutex_unlock(&idtcm->reg_lock);
1543
1544         return err;
1545 }
1546
1547 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1548 {
1549         struct idtcm_channel *channel =
1550                 container_of(ptp, struct idtcm_channel, caps);
1551         struct idtcm *idtcm = channel->idtcm;
1552         int err;
1553
1554         mutex_lock(&idtcm->reg_lock);
1555
1556         err = _idtcm_adjtime_deprecated(channel, delta);
1557
1558         if (err)
1559                 dev_err(&idtcm->client->dev,
1560                         "Failed at line %d in func %s!\n",
1561                         __LINE__,
1562                         __func__);
1563
1564         mutex_unlock(&idtcm->reg_lock);
1565
1566         return err;
1567 }
1568
1569 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1570 {
1571         struct idtcm_channel *channel =
1572                 container_of(ptp, struct idtcm_channel, caps);
1573         struct idtcm *idtcm = channel->idtcm;
1574         struct timespec64 ts;
1575         enum scsr_tod_write_type_sel type;
1576         int err;
1577
1578         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1579                 err = idtcm_do_phase_pull_in(channel, delta, 0);
1580                 if (err)
1581                         dev_err(&idtcm->client->dev,
1582                                 "Failed at line %d in func %s!\n",
1583                                 __LINE__,
1584                                 __func__);
1585                 return err;
1586         }
1587
1588         if (delta >= 0) {
1589                 ts = ns_to_timespec64(delta);
1590                 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1591         } else {
1592                 ts = ns_to_timespec64(-delta);
1593                 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1594         }
1595
1596         mutex_lock(&idtcm->reg_lock);
1597
1598         err = _idtcm_settime(channel, &ts, type);
1599
1600         if (err)
1601                 dev_err(&idtcm->client->dev,
1602                         "Failed at line %d in func %s!\n",
1603                         __LINE__,
1604                         __func__);
1605
1606         mutex_unlock(&idtcm->reg_lock);
1607
1608         return err;
1609 }
1610
1611 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1612 {
1613         struct idtcm_channel *channel =
1614                 container_of(ptp, struct idtcm_channel, caps);
1615
1616         struct idtcm *idtcm = channel->idtcm;
1617
1618         int err;
1619
1620         mutex_lock(&idtcm->reg_lock);
1621
1622         err = _idtcm_adjphase(channel, delta);
1623
1624         if (err)
1625                 dev_err(&idtcm->client->dev,
1626                         "Failed at line %d in func %s!\n",
1627                         __LINE__,
1628                         __func__);
1629
1630         mutex_unlock(&idtcm->reg_lock);
1631
1632         return err;
1633 }
1634
1635 static int idtcm_adjfine(struct ptp_clock_info *ptp,  long scaled_ppm)
1636 {
1637         struct idtcm_channel *channel =
1638                 container_of(ptp, struct idtcm_channel, caps);
1639
1640         struct idtcm *idtcm = channel->idtcm;
1641
1642         int err;
1643
1644         mutex_lock(&idtcm->reg_lock);
1645
1646         err = _idtcm_adjfine(channel, scaled_ppm);
1647
1648         if (err)
1649                 dev_err(&idtcm->client->dev,
1650                         "Failed at line %d in func %s!\n",
1651                         __LINE__,
1652                         __func__);
1653
1654         mutex_unlock(&idtcm->reg_lock);
1655
1656         return err;
1657 }
1658
1659 static int idtcm_enable(struct ptp_clock_info *ptp,
1660                         struct ptp_clock_request *rq, int on)
1661 {
1662         int err;
1663
1664         struct idtcm_channel *channel =
1665                 container_of(ptp, struct idtcm_channel, caps);
1666
1667         switch (rq->type) {
1668         case PTP_CLK_REQ_PEROUT:
1669                 if (!on) {
1670                         err = idtcm_perout_enable(channel, false, &rq->perout);
1671                         if (err)
1672                                 dev_err(&channel->idtcm->client->dev,
1673                                         "Failed at line %d in func %s!\n",
1674                                         __LINE__,
1675                                         __func__);
1676                         return err;
1677                 }
1678
1679                 /* Only accept a 1-PPS aligned to the second. */
1680                 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1681                     rq->perout.period.nsec)
1682                         return -ERANGE;
1683
1684                 err = idtcm_perout_enable(channel, true, &rq->perout);
1685                 if (err)
1686                         dev_err(&channel->idtcm->client->dev,
1687                                 "Failed at line %d in func %s!\n",
1688                                 __LINE__,
1689                                 __func__);
1690                 return err;
1691         default:
1692                 break;
1693         }
1694
1695         return -EOPNOTSUPP;
1696 }
1697
1698 static int _enable_pll_tod_sync(struct idtcm *idtcm,
1699                                 u8 pll,
1700                                 u8 sync_src,
1701                                 u8 qn,
1702                                 u8 qn_plus_1)
1703 {
1704         int err;
1705         u8 val;
1706         u16 dpll;
1707         u16 out0 = 0, out1 = 0;
1708
1709         if ((qn == 0) && (qn_plus_1 == 0))
1710                 return 0;
1711
1712         switch (pll) {
1713         case 0:
1714                 dpll = DPLL_0;
1715                 if (qn)
1716                         out0 = OUTPUT_0;
1717                 if (qn_plus_1)
1718                         out1 = OUTPUT_1;
1719                 break;
1720         case 1:
1721                 dpll = DPLL_1;
1722                 if (qn)
1723                         out0 = OUTPUT_2;
1724                 if (qn_plus_1)
1725                         out1 = OUTPUT_3;
1726                 break;
1727         case 2:
1728                 dpll = DPLL_2;
1729                 if (qn)
1730                         out0 = OUTPUT_4;
1731                 if (qn_plus_1)
1732                         out1 = OUTPUT_5;
1733                 break;
1734         case 3:
1735                 dpll = DPLL_3;
1736                 if (qn)
1737                         out0 = OUTPUT_6;
1738                 if (qn_plus_1)
1739                         out1 = OUTPUT_7;
1740                 break;
1741         case 4:
1742                 dpll = DPLL_4;
1743                 if (qn)
1744                         out0 = OUTPUT_8;
1745                 break;
1746         case 5:
1747                 dpll = DPLL_5;
1748                 if (qn)
1749                         out0 = OUTPUT_9;
1750                 if (qn_plus_1)
1751                         out1 = OUTPUT_8;
1752                 break;
1753         case 6:
1754                 dpll = DPLL_6;
1755                 if (qn)
1756                         out0 = OUTPUT_10;
1757                 if (qn_plus_1)
1758                         out1 = OUTPUT_11;
1759                 break;
1760         case 7:
1761                 dpll = DPLL_7;
1762                 if (qn)
1763                         out0 = OUTPUT_11;
1764                 break;
1765         default:
1766                 return -EINVAL;
1767         }
1768
1769         /*
1770          * Enable OUTPUT OUT_SYNC.
1771          */
1772         if (out0) {
1773                 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1774
1775                 if (err)
1776                         return err;
1777
1778                 val &= ~OUT_SYNC_DISABLE;
1779
1780                 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1781
1782                 if (err)
1783                         return err;
1784         }
1785
1786         if (out1) {
1787                 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1788
1789                 if (err)
1790                         return err;
1791
1792                 val &= ~OUT_SYNC_DISABLE;
1793
1794                 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1795
1796                 if (err)
1797                         return err;
1798         }
1799
1800         /* enable dpll sync tod pps, must be set before dpll_mode */
1801         err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1802         if (err)
1803                 return err;
1804
1805         val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1806         val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1807         val |= TOD_SYNC_EN;
1808
1809         return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1810 }
1811
1812 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1813 {
1814         struct idtcm *idtcm = channel->idtcm;
1815
1816         u8 pll;
1817         u8 sync_src;
1818         u8 qn;
1819         u8 qn_plus_1;
1820         u8 cfg;
1821         int err = 0;
1822         u16 output_mask = channel->output_mask;
1823         u8 out8_mux = 0;
1824         u8 out11_mux = 0;
1825         u8 temp;
1826
1827         /*
1828          * set tod_out_sync_enable to 0.
1829          */
1830         err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1831         if (err)
1832                 return err;
1833
1834         cfg &= ~TOD_OUT_SYNC_ENABLE;
1835
1836         err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1837         if (err)
1838                 return err;
1839
1840         switch (channel->tod_n) {
1841         case TOD_0:
1842                 sync_src = 0;
1843                 break;
1844         case TOD_1:
1845                 sync_src = 1;
1846                 break;
1847         case TOD_2:
1848                 sync_src = 2;
1849                 break;
1850         case TOD_3:
1851                 sync_src = 3;
1852                 break;
1853         default:
1854                 return -EINVAL;
1855         }
1856
1857         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1858                          &temp, sizeof(temp));
1859         if (err)
1860                 return err;
1861
1862         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1863             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1864                 out8_mux = 1;
1865
1866         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1867                          &temp, sizeof(temp));
1868         if (err)
1869                 return err;
1870
1871         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1872             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1873                 out11_mux = 1;
1874
1875         for (pll = 0; pll < 8; pll++) {
1876                 qn = 0;
1877                 qn_plus_1 = 0;
1878
1879                 if (pll < 4) {
1880                         /* First 4 pll has 2 outputs */
1881                         qn = output_mask & 0x1;
1882                         output_mask = output_mask >> 1;
1883                         qn_plus_1 = output_mask & 0x1;
1884                         output_mask = output_mask >> 1;
1885                 } else if (pll == 4) {
1886                         if (out8_mux == 0) {
1887                                 qn = output_mask & 0x1;
1888                                 output_mask = output_mask >> 1;
1889                         }
1890                 } else if (pll == 5) {
1891                         if (out8_mux) {
1892                                 qn_plus_1 = output_mask & 0x1;
1893                                 output_mask = output_mask >> 1;
1894                         }
1895                         qn = output_mask & 0x1;
1896                         output_mask = output_mask >> 1;
1897                 } else if (pll == 6) {
1898                         qn = output_mask & 0x1;
1899                         output_mask = output_mask >> 1;
1900                         if (out11_mux) {
1901                                 qn_plus_1 = output_mask & 0x1;
1902                                 output_mask = output_mask >> 1;
1903                         }
1904                 } else if (pll == 7) {
1905                         if (out11_mux == 0) {
1906                                 qn = output_mask & 0x1;
1907                                 output_mask = output_mask >> 1;
1908                         }
1909                 }
1910
1911                 if ((qn != 0) || (qn_plus_1 != 0))
1912                         err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1913                                                qn_plus_1);
1914
1915                 if (err)
1916                         return err;
1917         }
1918
1919         return err;
1920 }
1921
1922 static int idtcm_enable_tod(struct idtcm_channel *channel)
1923 {
1924         struct idtcm *idtcm = channel->idtcm;
1925         struct timespec64 ts = {0, 0};
1926         u8 cfg;
1927         int err;
1928
1929         /*
1930          * Start the TOD clock ticking.
1931          */
1932         err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1933         if (err)
1934                 return err;
1935
1936         cfg |= TOD_ENABLE;
1937
1938         err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1939         if (err)
1940                 return err;
1941
1942         if (idtcm->deprecated)
1943                 return _idtcm_settime_deprecated(channel, &ts);
1944         else
1945                 return _idtcm_settime(channel, &ts,
1946                                       SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1947 }
1948
1949 static void idtcm_set_version_info(struct idtcm *idtcm)
1950 {
1951         u8 major;
1952         u8 minor;
1953         u8 hotfix;
1954         u16 product_id;
1955         u8 hw_rev_id;
1956         u8 config_select;
1957         char *fmt = "%d.%d.%d, Id: 0x%04x  HW Rev: %d  OTP Config Select: %d\n";
1958
1959         idtcm_read_major_release(idtcm, &major);
1960         idtcm_read_minor_release(idtcm, &minor);
1961         idtcm_read_hotfix_release(idtcm, &hotfix);
1962
1963         idtcm_read_product_id(idtcm, &product_id);
1964         idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1965
1966         idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1967
1968         snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1969                  major, minor, hotfix);
1970
1971         if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
1972                 idtcm->deprecated = 0;
1973         else
1974                 idtcm->deprecated = 1;
1975
1976         dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
1977                  product_id, hw_rev_id, config_select);
1978 }
1979
1980 static const struct ptp_clock_info idtcm_caps = {
1981         .owner          = THIS_MODULE,
1982         .max_adj        = 244000,
1983         .n_per_out      = 12,
1984         .adjphase       = &idtcm_adjphase,
1985         .adjfine        = &idtcm_adjfine,
1986         .adjtime        = &idtcm_adjtime,
1987         .gettime64      = &idtcm_gettime,
1988         .settime64      = &idtcm_settime,
1989         .enable         = &idtcm_enable,
1990 };
1991
1992 static const struct ptp_clock_info idtcm_caps_deprecated = {
1993         .owner          = THIS_MODULE,
1994         .max_adj        = 244000,
1995         .n_per_out      = 12,
1996         .adjphase       = &idtcm_adjphase,
1997         .adjfine        = &idtcm_adjfine,
1998         .adjtime        = &idtcm_adjtime_deprecated,
1999         .gettime64      = &idtcm_gettime,
2000         .settime64      = &idtcm_settime_deprecated,
2001         .enable         = &idtcm_enable,
2002 };
2003
2004 static int configure_channel_pll(struct idtcm_channel *channel)
2005 {
2006         int err = 0;
2007
2008         switch (channel->pll) {
2009         case 0:
2010                 channel->dpll_freq = DPLL_FREQ_0;
2011                 channel->dpll_n = DPLL_0;
2012                 channel->hw_dpll_n = HW_DPLL_0;
2013                 channel->dpll_phase = DPLL_PHASE_0;
2014                 channel->dpll_ctrl_n = DPLL_CTRL_0;
2015                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2016                 break;
2017         case 1:
2018                 channel->dpll_freq = DPLL_FREQ_1;
2019                 channel->dpll_n = DPLL_1;
2020                 channel->hw_dpll_n = HW_DPLL_1;
2021                 channel->dpll_phase = DPLL_PHASE_1;
2022                 channel->dpll_ctrl_n = DPLL_CTRL_1;
2023                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2024                 break;
2025         case 2:
2026                 channel->dpll_freq = DPLL_FREQ_2;
2027                 channel->dpll_n = DPLL_2;
2028                 channel->hw_dpll_n = HW_DPLL_2;
2029                 channel->dpll_phase = DPLL_PHASE_2;
2030                 channel->dpll_ctrl_n = DPLL_CTRL_2;
2031                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2032                 break;
2033         case 3:
2034                 channel->dpll_freq = DPLL_FREQ_3;
2035                 channel->dpll_n = DPLL_3;
2036                 channel->hw_dpll_n = HW_DPLL_3;
2037                 channel->dpll_phase = DPLL_PHASE_3;
2038                 channel->dpll_ctrl_n = DPLL_CTRL_3;
2039                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2040                 break;
2041         case 4:
2042                 channel->dpll_freq = DPLL_FREQ_4;
2043                 channel->dpll_n = DPLL_4;
2044                 channel->hw_dpll_n = HW_DPLL_4;
2045                 channel->dpll_phase = DPLL_PHASE_4;
2046                 channel->dpll_ctrl_n = DPLL_CTRL_4;
2047                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2048                 break;
2049         case 5:
2050                 channel->dpll_freq = DPLL_FREQ_5;
2051                 channel->dpll_n = DPLL_5;
2052                 channel->hw_dpll_n = HW_DPLL_5;
2053                 channel->dpll_phase = DPLL_PHASE_5;
2054                 channel->dpll_ctrl_n = DPLL_CTRL_5;
2055                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2056                 break;
2057         case 6:
2058                 channel->dpll_freq = DPLL_FREQ_6;
2059                 channel->dpll_n = DPLL_6;
2060                 channel->hw_dpll_n = HW_DPLL_6;
2061                 channel->dpll_phase = DPLL_PHASE_6;
2062                 channel->dpll_ctrl_n = DPLL_CTRL_6;
2063                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2064                 break;
2065         case 7:
2066                 channel->dpll_freq = DPLL_FREQ_7;
2067                 channel->dpll_n = DPLL_7;
2068                 channel->hw_dpll_n = HW_DPLL_7;
2069                 channel->dpll_phase = DPLL_PHASE_7;
2070                 channel->dpll_ctrl_n = DPLL_CTRL_7;
2071                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2072                 break;
2073         default:
2074                 err = -EINVAL;
2075         }
2076
2077         return err;
2078 }
2079
2080 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2081 {
2082         struct idtcm_channel *channel;
2083         int err;
2084
2085         if (!(index < MAX_TOD))
2086                 return -EINVAL;
2087
2088         channel = &idtcm->channel[index];
2089
2090         /* Set pll addresses */
2091         err = configure_channel_pll(channel);
2092         if (err)
2093                 return err;
2094
2095         /* Set tod addresses */
2096         switch (index) {
2097         case 0:
2098                 channel->tod_read_primary = TOD_READ_PRIMARY_0;
2099                 channel->tod_write = TOD_WRITE_0;
2100                 channel->tod_n = TOD_0;
2101                 break;
2102         case 1:
2103                 channel->tod_read_primary = TOD_READ_PRIMARY_1;
2104                 channel->tod_write = TOD_WRITE_1;
2105                 channel->tod_n = TOD_1;
2106                 break;
2107         case 2:
2108                 channel->tod_read_primary = TOD_READ_PRIMARY_2;
2109                 channel->tod_write = TOD_WRITE_2;
2110                 channel->tod_n = TOD_2;
2111                 break;
2112         case 3:
2113                 channel->tod_read_primary = TOD_READ_PRIMARY_3;
2114                 channel->tod_write = TOD_WRITE_3;
2115                 channel->tod_n = TOD_3;
2116                 break;
2117         default:
2118                 return -EINVAL;
2119         }
2120
2121         channel->idtcm = idtcm;
2122
2123         if (idtcm->deprecated)
2124                 channel->caps = idtcm_caps_deprecated;
2125         else
2126                 channel->caps = idtcm_caps;
2127
2128         snprintf(channel->caps.name, sizeof(channel->caps.name),
2129                  "IDT CM TOD%u", index);
2130
2131         if (!idtcm->deprecated) {
2132                 err = idtcm_enable_tod_sync(channel);
2133                 if (err) {
2134                         dev_err(&idtcm->client->dev,
2135                                 "Failed at line %d in func %s!\n",
2136                                 __LINE__,
2137                                 __func__);
2138                         return err;
2139                 }
2140         }
2141
2142         /* Sync pll mode with hardware */
2143         err = idtcm_get_pll_mode(channel, &channel->pll_mode);
2144         if (err) {
2145                 dev_err(&idtcm->client->dev,
2146                         "Error: %s - Unable to read pll mode\n", __func__);
2147                 return err;
2148         }
2149
2150         err = idtcm_enable_tod(channel);
2151         if (err) {
2152                 dev_err(&idtcm->client->dev,
2153                         "Failed at line %d in func %s!\n",
2154                         __LINE__,
2155                         __func__);
2156                 return err;
2157         }
2158
2159         channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2160
2161         if (IS_ERR(channel->ptp_clock)) {
2162                 err = PTR_ERR(channel->ptp_clock);
2163                 channel->ptp_clock = NULL;
2164                 return err;
2165         }
2166
2167         if (!channel->ptp_clock)
2168                 return -ENOTSUPP;
2169
2170         dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2171                  index, channel->ptp_clock->index);
2172
2173         return 0;
2174 }
2175
2176 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2177 {
2178         u8 i;
2179         struct idtcm_channel *channel;
2180
2181         for (i = 0; i < MAX_TOD; i++) {
2182
2183                 channel = &idtcm->channel[i];
2184
2185                 if (channel->ptp_clock)
2186                         ptp_clock_unregister(channel->ptp_clock);
2187         }
2188 }
2189
2190 static void set_default_masks(struct idtcm *idtcm)
2191 {
2192         idtcm->tod_mask = DEFAULT_TOD_MASK;
2193
2194         idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2195         idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2196         idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2197         idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2198
2199         idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2200         idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2201         idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2202         idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2203 }
2204
2205 static int idtcm_probe(struct i2c_client *client,
2206                        const struct i2c_device_id *id)
2207 {
2208         struct idtcm *idtcm;
2209         int err;
2210         u8 i;
2211         char *fmt = "Failed at %d in line %s with channel output %d!\n";
2212
2213         /* Unused for now */
2214         (void)id;
2215
2216         idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2217
2218         if (!idtcm)
2219                 return -ENOMEM;
2220
2221         idtcm->client = client;
2222         idtcm->page_offset = 0xff;
2223         idtcm->calculate_overhead_flag = 0;
2224
2225         set_default_masks(idtcm);
2226
2227         mutex_init(&idtcm->reg_lock);
2228         mutex_lock(&idtcm->reg_lock);
2229
2230         idtcm_set_version_info(idtcm);
2231
2232         err = idtcm_load_firmware(idtcm, &client->dev);
2233
2234         if (err)
2235                 dev_warn(&idtcm->client->dev,
2236                          "loading firmware failed with %d\n", err);
2237
2238         if (wait_for_boot_status_ready(idtcm))
2239                 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0\n");
2240
2241         if (idtcm->tod_mask) {
2242                 for (i = 0; i < MAX_TOD; i++) {
2243                         if (idtcm->tod_mask & (1 << i)) {
2244                                 err = idtcm_enable_channel(idtcm, i);
2245                                 if (err) {
2246                                         dev_err(&idtcm->client->dev,
2247                                                 fmt,
2248                                                 __LINE__,
2249                                                 __func__,
2250                                                 i);
2251                                         break;
2252                                 }
2253                         }
2254                 }
2255         } else {
2256                 dev_err(&idtcm->client->dev,
2257                         "no PLLs flagged as PHCs, nothing to do\n");
2258                 err = -ENODEV;
2259         }
2260
2261         mutex_unlock(&idtcm->reg_lock);
2262
2263         if (err) {
2264                 ptp_clock_unregister_all(idtcm);
2265                 return err;
2266         }
2267
2268         i2c_set_clientdata(client, idtcm);
2269
2270         return 0;
2271 }
2272
2273 static int idtcm_remove(struct i2c_client *client)
2274 {
2275         struct idtcm *idtcm = i2c_get_clientdata(client);
2276
2277         ptp_clock_unregister_all(idtcm);
2278
2279         mutex_destroy(&idtcm->reg_lock);
2280
2281         return 0;
2282 }
2283
2284 #ifdef CONFIG_OF
2285 static const struct of_device_id idtcm_dt_id[] = {
2286         { .compatible = "idt,8a34000" },
2287         { .compatible = "idt,8a34001" },
2288         { .compatible = "idt,8a34002" },
2289         { .compatible = "idt,8a34003" },
2290         { .compatible = "idt,8a34004" },
2291         { .compatible = "idt,8a34005" },
2292         { .compatible = "idt,8a34006" },
2293         { .compatible = "idt,8a34007" },
2294         { .compatible = "idt,8a34008" },
2295         { .compatible = "idt,8a34009" },
2296         { .compatible = "idt,8a34010" },
2297         { .compatible = "idt,8a34011" },
2298         { .compatible = "idt,8a34012" },
2299         { .compatible = "idt,8a34013" },
2300         { .compatible = "idt,8a34014" },
2301         { .compatible = "idt,8a34015" },
2302         { .compatible = "idt,8a34016" },
2303         { .compatible = "idt,8a34017" },
2304         { .compatible = "idt,8a34018" },
2305         { .compatible = "idt,8a34019" },
2306         { .compatible = "idt,8a34040" },
2307         { .compatible = "idt,8a34041" },
2308         { .compatible = "idt,8a34042" },
2309         { .compatible = "idt,8a34043" },
2310         { .compatible = "idt,8a34044" },
2311         { .compatible = "idt,8a34045" },
2312         { .compatible = "idt,8a34046" },
2313         { .compatible = "idt,8a34047" },
2314         { .compatible = "idt,8a34048" },
2315         { .compatible = "idt,8a34049" },
2316         {},
2317 };
2318 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2319 #endif
2320
2321 static const struct i2c_device_id idtcm_i2c_id[] = {
2322         { "8a34000" },
2323         { "8a34001" },
2324         { "8a34002" },
2325         { "8a34003" },
2326         { "8a34004" },
2327         { "8a34005" },
2328         { "8a34006" },
2329         { "8a34007" },
2330         { "8a34008" },
2331         { "8a34009" },
2332         { "8a34010" },
2333         { "8a34011" },
2334         { "8a34012" },
2335         { "8a34013" },
2336         { "8a34014" },
2337         { "8a34015" },
2338         { "8a34016" },
2339         { "8a34017" },
2340         { "8a34018" },
2341         { "8a34019" },
2342         { "8a34040" },
2343         { "8a34041" },
2344         { "8a34042" },
2345         { "8a34043" },
2346         { "8a34044" },
2347         { "8a34045" },
2348         { "8a34046" },
2349         { "8a34047" },
2350         { "8a34048" },
2351         { "8a34049" },
2352         {},
2353 };
2354 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2355
2356 static struct i2c_driver idtcm_driver = {
2357         .driver = {
2358                 .of_match_table = of_match_ptr(idtcm_dt_id),
2359                 .name           = "idtcm",
2360         },
2361         .probe          = idtcm_probe,
2362         .remove         = idtcm_remove,
2363         .id_table       = idtcm_i2c_id,
2364 };
2365
2366 module_i2c_driver(idtcm_driver);