drivers/ptp/ptp_clockmatrix.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
   4  * synchronization devices.
   5  *
   6  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
   7  */
   8 #include <linux/firmware.h>
   9 #include <linux/i2c.h>
  10 #include <linux/module.h>
  11 #include <linux/ptp_clock_kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/jiffies.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timekeeping.h>
  16 #include <linux/string.h>
  17
  18 #include "ptp_private.h"
  19 #include "ptp_clockmatrix.h"
  20
  21 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
  22 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
  23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  24 MODULE_VERSION("1.0");
  25 MODULE_LICENSE("GPL");
  26
  27 /*
  28  * The name of the firmware file to be loaded
  29  * over-rides any automatic selection
  30  */
  31 static char *firmware;
  32 module_param(firmware, charp, 0);
  33
  34 #define SETTIME_CORRECTION (0)
  35
  36 static long set_write_phase_ready(struct ptp_clock_info *ptp)
  37 {
  38         struct idtcm_channel *channel =
  39                 container_of(ptp, struct idtcm_channel, caps);
  40
  41         channel->write_phase_ready = 1;
  42
  43         return 0;
  44 }
  45
  46 static int char_array_to_timespec(u8 *buf,
  47                                   u8 count,
  48                                   struct timespec64 *ts)
  49 {
  50         u8 i;
  51         u64 nsec;
  52         time64_t sec;
  53
  54         if (count < TOD_BYTE_COUNT)
  55                 return 1;
  56
  57         /* Sub-nanoseconds are in buf[0]. */
  58         nsec = buf[4];
  59         for (i = 0; i < 3; i++) {
  60                 nsec <<= 8;
  61                 nsec |= buf[3 - i];
  62         }
  63
  64         sec = buf[10];
  65         for (i = 0; i < 5; i++) {
  66                 sec <<= 8;
  67                 sec |= buf[9 - i];
  68         }
  69
  70         ts->tv_sec = sec;
  71         ts->tv_nsec = nsec;
  72
  73         return 0;
  74 }
  75
  76 static int timespec_to_char_array(struct timespec64 const *ts,
  77                                   u8 *buf,
  78                                   u8 count)
  79 {
  80         u8 i;
  81         s32 nsec;
  82         time64_t sec;
  83
  84         if (count < TOD_BYTE_COUNT)
  85                 return 1;
  86
  87         nsec = ts->tv_nsec;
  88         sec = ts->tv_sec;
  89
  90         /* Sub-nanoseconds are in buf[0]. */
  91         buf[0] = 0;
  92         for (i = 1; i < 5; i++) {
  93                 buf[i] = nsec & 0xff;
  94                 nsec >>= 8;
  95         }
  96
  97         for (i = 5; i < TOD_BYTE_COUNT; i++) {
  98
  99                 buf[i] = sec & 0xff;
 100                 sec >>= 8;
 101         }
 102
 103         return 0;
 104 }
 105
 106 static int idtcm_strverscmp(const char *ver1, const char *ver2)
 107 {
 108         u8 num1;
 109         u8 num2;
 110         int result = 0;
 111
 112         /* loop through each level of the version string */
 113         while (result == 0) {
 114                 /* extract leading version numbers */
 115                 if (kstrtou8(ver1, 10, &num1) < 0)
 116                         return -1;
 117
 118                 if (kstrtou8(ver2, 10, &num2) < 0)
 119                         return -1;
 120
 121                 /* if numbers differ, then set the result */
 122                 if (num1 < num2)
 123                         result = -1;
 124                 else if (num1 > num2)
 125                         result = 1;
 126                 else {
 127                         /* if numbers are the same, go to next level */
 128                         ver1 = strchr(ver1, '.');
 129                         ver2 = strchr(ver2, '.');
 130                         if (!ver1 && !ver2)
 131                                 break;
 132                         else if (!ver1)
 133                                 result = -1;
 134                         else if (!ver2)
 135                                 result = 1;
 136                         else {
 137                                 ver1++;
 138                                 ver2++;
 139                         }
 140                 }
 141         }
 142         return result;
 143 }
 144
 145 static int idtcm_xfer(struct idtcm *idtcm,
 146                       u8 regaddr,
 147                       u8 *buf,
 148                       u16 count,
 149                       bool write)
 150 {
 151         struct i2c_client *client = idtcm->client;
 152         struct i2c_msg msg[2];
 153         int cnt;
 154         char *fmt = "i2c_transfer failed at %d in %s for %s, at addr: %04X!\n";
 155
 156         msg[0].addr = client->addr;
 157         msg[0].flags = 0;
 158         msg[0].len = 1;
 159         msg[0].buf = &regaddr;
 160
 161         msg[1].addr = client->addr;
 162         msg[1].flags = write ? 0 : I2C_M_RD;
 163         msg[1].len = count;
 164         msg[1].buf = buf;
 165
 166         cnt = i2c_transfer(client->adapter, msg, 2);
 167
 168         if (cnt < 0) {
 169                 dev_err(&client->dev,
 170                         fmt,
 171                         __LINE__,
 172                         __func__,
 173                         write ? "write" : "read",
 174                         regaddr);
 175                 return cnt;
 176         } else if (cnt != 2) {
 177                 dev_err(&client->dev,
 178                         "i2c_transfer sent only %d of %d messages\n", cnt, 2);
 179                 return -EIO;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
 186 {
 187         u8 buf[4];
 188         int err;
 189
 190         if (idtcm->page_offset == val)
 191                 return 0;
 192
 193         buf[0] = 0x0;
 194         buf[1] = val;
 195         buf[2] = 0x10;
 196         buf[3] = 0x20;
 197
 198         err = idtcm_xfer(idtcm, PAGE_ADDR, buf, sizeof(buf), 1);
 199
 200         if (err) {
 201                 idtcm->page_offset = 0xff;
 202                 dev_err(&idtcm->client->dev, "failed to set page offset\n");
 203         } else {
 204                 idtcm->page_offset = val;
 205         }
 206
 207         return err;
 208 }
 209
 210 static int _idtcm_rdwr(struct idtcm *idtcm,
 211                        u16 regaddr,
 212                        u8 *buf,
 213                        u16 count,
 214                        bool write)
 215 {
 216         u8 hi;
 217         u8 lo;
 218         int err;
 219
 220         hi = (regaddr >> 8) & 0xff;
 221         lo = regaddr & 0xff;
 222
 223         err = idtcm_page_offset(idtcm, hi);
 224
 225         if (err)
 226                 goto out;
 227
 228         err = idtcm_xfer(idtcm, lo, buf, count, write);
 229 out:
 230         return err;
 231 }
 232
 233 static int idtcm_read(struct idtcm *idtcm,
 234                       u16 module,
 235                       u16 regaddr,
 236                       u8 *buf,
 237                       u16 count)
 238 {
 239         return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
 240 }
 241
 242 static int idtcm_write(struct idtcm *idtcm,
 243                        u16 module,
 244                        u16 regaddr,
 245                        u8 *buf,
 246                        u16 count)
 247 {
 248         return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
 249 }
 250
 251 static int _idtcm_gettime(struct idtcm_channel *channel,
 252                           struct timespec64 *ts)
 253 {
 254         struct idtcm *idtcm = channel->idtcm;
 255         u8 buf[TOD_BYTE_COUNT];
 256         u8 timeout = 10;
 257         u8 trigger;
 258         int err;
 259
 260         err = idtcm_read(idtcm, channel->tod_read_primary,
 261                          TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
 262         if (err)
 263                 return err;
 264
 265         trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
 266         trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
 267         trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
 268
 269         err = idtcm_write(idtcm, channel->tod_read_primary,
 270                           TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
 271         if (err)
 272                 return err;
 273
 274         /* wait trigger to be 0 */
 275         while (trigger & TOD_READ_TRIGGER_MASK) {
 276
 277                 if (idtcm->calculate_overhead_flag)
 278                         idtcm->start_time = ktime_get_raw();
 279
 280                 err = idtcm_read(idtcm, channel->tod_read_primary,
 281                                  TOD_READ_PRIMARY_CMD, &trigger,
 282                                  sizeof(trigger));
 283
 284                 if (err)
 285                         return err;
 286
 287                 if (--timeout == 0)
 288                         return -EIO;
 289         }
 290
 291         err = idtcm_read(idtcm, channel->tod_read_primary,
 292                          TOD_READ_PRIMARY, buf, sizeof(buf));
 293
 294         if (err)
 295                 return err;
 296
 297         err = char_array_to_timespec(buf, sizeof(buf), ts);
 298
 299         return err;
 300 }
 301
 302 static int _sync_pll_output(struct idtcm *idtcm,
 303                             u8 pll,
 304                             u8 sync_src,
 305                             u8 qn,
 306                             u8 qn_plus_1)
 307 {
 308         int err;
 309         u8 val;
 310         u16 sync_ctrl0;
 311         u16 sync_ctrl1;
 312         u8 temp;
 313
 314         if ((qn == 0) && (qn_plus_1 == 0))
 315                 return 0;
 316
 317         switch (pll) {
 318         case 0:
 319                 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
 320                 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
 321                 break;
 322         case 1:
 323                 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
 324                 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
 325                 break;
 326         case 2:
 327                 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
 328                 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
 329                 break;
 330         case 3:
 331                 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
 332                 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
 333                 break;
 334         case 4:
 335                 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
 336                 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
 337                 break;
 338         case 5:
 339                 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
 340                 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
 341                 break;
 342         case 6:
 343                 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
 344                 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
 345                 break;
 346         case 7:
 347                 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
 348                 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
 349                 break;
 350         default:
 351                 return -EINVAL;
 352         }
 353
 354         val = SYNCTRL1_MASTER_SYNC_RST;
 355
 356         /* Place master sync in reset */
 357         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 358         if (err)
 359                 return err;
 360
 361         err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
 362         if (err)
 363                 return err;
 364
 365         /* Set sync trigger mask */
 366         val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
 367
 368         if (qn)
 369                 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
 370
 371         if (qn_plus_1)
 372                 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
 373
 374         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 375         if (err)
 376                 return err;
 377
 378         /* PLL5 can have OUT8 as second additional output. */
 379         if ((pll == 5) && (qn_plus_1 != 0)) {
 380                 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
 381                                  &temp, sizeof(temp));
 382                 if (err)
 383                         return err;
 384
 385                 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
 386
 387                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
 388                                   &temp, sizeof(temp));
 389                 if (err)
 390                         return err;
 391
 392                 temp |= Q9_TO_Q8_SYNC_TRIG;
 393
 394                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
 395                                   &temp, sizeof(temp));
 396                 if (err)
 397                         return err;
 398         }
 399
 400         /* PLL6 can have OUT11 as second additional output. */
 401         if ((pll == 6) && (qn_plus_1 != 0)) {
 402                 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
 403                                  &temp, sizeof(temp));
 404                 if (err)
 405                         return err;
 406
 407                 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
 408
 409                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
 410                                   &temp, sizeof(temp));
 411                 if (err)
 412                         return err;
 413
 414                 temp |= Q10_TO_Q11_SYNC_TRIG;
 415
 416                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
 417                                   &temp, sizeof(temp));
 418                 if (err)
 419                         return err;
 420         }
 421
 422         /* Place master sync out of reset */
 423         val &= ~(SYNCTRL1_MASTER_SYNC_RST);
 424         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 425
 426         return err;
 427 }
 428
 429 static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
 430 {
 431         int err = 0;
 432
 433         switch (tod_addr) {
 434         case TOD_0:
 435                 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
 436                 break;
 437         case TOD_1:
 438                 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
 439                 break;
 440         case TOD_2:
 441                 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
 442                 break;
 443         case TOD_3:
 444                 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
 445                 break;
 446         default:
 447                 err = -EINVAL;
 448         }
 449
 450         return err;
 451 }
 452
 453 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
 454 {
 455         struct idtcm *idtcm = channel->idtcm;
 456
 457         u8 pll;
 458         u8 sync_src;
 459         u8 qn;
 460         u8 qn_plus_1;
 461         int err = 0;
 462         u8 out8_mux = 0;
 463         u8 out11_mux = 0;
 464         u8 temp;
 465
 466         u16 output_mask = channel->output_mask;
 467
 468         err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
 469         if (err)
 470                 return err;
 471
 472         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
 473                          &temp, sizeof(temp));
 474         if (err)
 475                 return err;
 476
 477         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
 478             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
 479                 out8_mux = 1;
 480
 481         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
 482                          &temp, sizeof(temp));
 483         if (err)
 484                 return err;
 485
 486         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
 487             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
 488                 out11_mux = 1;
 489
 490         for (pll = 0; pll < 8; pll++) {
 491                 qn = 0;
 492                 qn_plus_1 = 0;
 493
 494                 if (pll < 4) {
 495                         /* First 4 pll has 2 outputs */
 496                         qn = output_mask & 0x1;
 497                         output_mask = output_mask >> 1;
 498                         qn_plus_1 = output_mask & 0x1;
 499                         output_mask = output_mask >> 1;
 500                 } else if (pll == 4) {
 501                         if (out8_mux == 0) {
 502                                 qn = output_mask & 0x1;
 503                                 output_mask = output_mask >> 1;
 504                         }
 505                 } else if (pll == 5) {
 506                         if (out8_mux) {
 507                                 qn_plus_1 = output_mask & 0x1;
 508                                 output_mask = output_mask >> 1;
 509                         }
 510                         qn = output_mask & 0x1;
 511                         output_mask = output_mask >> 1;
 512                 } else if (pll == 6) {
 513                         qn = output_mask & 0x1;
 514                         output_mask = output_mask >> 1;
 515                         if (out11_mux) {
 516                                 qn_plus_1 = output_mask & 0x1;
 517                                 output_mask = output_mask >> 1;
 518                         }
 519                 } else if (pll == 7) {
 520                         if (out11_mux == 0) {
 521                                 qn = output_mask & 0x1;
 522                                 output_mask = output_mask >> 1;
 523                         }
 524                 }
 525
 526                 if ((qn != 0) || (qn_plus_1 != 0))
 527                         err = _sync_pll_output(idtcm, pll, sync_src, qn,
 528                                                qn_plus_1);
 529
 530                 if (err)
 531                         return err;
 532         }
 533
 534         return err;
 535 }
 536
 537 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
 538                                struct timespec64 const *ts,
 539                                enum hw_tod_write_trig_sel wr_trig)
 540 {
 541         struct idtcm *idtcm = channel->idtcm;
 542
 543         u8 buf[TOD_BYTE_COUNT];
 544         u8 cmd;
 545         int err;
 546         struct timespec64 local_ts = *ts;
 547         s64 total_overhead_ns;
 548
 549         /* Configure HW TOD write trigger. */
 550         err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 551                          &cmd, sizeof(cmd));
 552
 553         if (err)
 554                 return err;
 555
 556         cmd &= ~(0x0f);
 557         cmd |= wr_trig | 0x08;
 558
 559         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 560                           &cmd, sizeof(cmd));
 561
 562         if (err)
 563                 return err;
 564
 565         if (wr_trig  != HW_TOD_WR_TRIG_SEL_MSB) {
 566
 567                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 568
 569                 if (err)
 570                         return err;
 571
 572                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 573                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 574
 575                 if (err)
 576                         return err;
 577         }
 578
 579         /* ARM HW TOD write trigger. */
 580         cmd &= ~(0x08);
 581
 582         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 583                           &cmd, sizeof(cmd));
 584
 585         if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
 586
 587                 if (idtcm->calculate_overhead_flag) {
 588                         /* Assumption: I2C @ 400KHz */
 589                         total_overhead_ns =  ktime_to_ns(ktime_get_raw()
 590                                                          - idtcm->start_time)
 591                                              + idtcm->tod_write_overhead_ns
 592                                              + SETTIME_CORRECTION;
 593
 594                         timespec64_add_ns(&local_ts, total_overhead_ns);
 595
 596                         idtcm->calculate_overhead_flag = 0;
 597                 }
 598
 599                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 600
 601                 if (err)
 602                         return err;
 603
 604                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 605                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 606         }
 607
 608         return err;
 609 }
 610
 611 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
 612                                     struct timespec64 const *ts,
 613                                     enum scsr_tod_write_trig_sel wr_trig,
 614                                     enum scsr_tod_write_type_sel wr_type)
 615 {
 616         struct idtcm *idtcm = channel->idtcm;
 617         unsigned char buf[TOD_BYTE_COUNT], cmd;
 618         struct timespec64 local_ts = *ts;
 619         int err, count = 0;
 620
 621         timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
 622
 623         err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 624
 625         if (err)
 626                 return err;
 627
 628         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
 629                           buf, sizeof(buf));
 630         if (err)
 631                 return err;
 632
 633         /* Trigger the write operation. */
 634         err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
 635                          &cmd, sizeof(cmd));
 636         if (err)
 637                 return err;
 638
 639         cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
 640         cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
 641         cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
 642         cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
 643
 644         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
 645                            &cmd, sizeof(cmd));
 646         if (err)
 647                 return err;
 648
 649         /* Wait for the operation to complete. */
 650         while (1) {
 651                 /* pps trigger takes up to 1 sec to complete */
 652                 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
 653                         msleep(50);
 654
 655                 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
 656                                  &cmd, sizeof(cmd));
 657                 if (err)
 658                         return err;
 659
 660                 if (cmd == 0)
 661                         break;
 662
 663                 if (++count > 20) {
 664                         dev_err(&idtcm->client->dev,
 665                                 "Timed out waiting for the write counter\n");
 666                         return -EIO;
 667                 }
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int _idtcm_settime(struct idtcm_channel *channel,
 674                           struct timespec64 const *ts,
 675                           enum hw_tod_write_trig_sel wr_trig)
 676 {
 677         struct idtcm *idtcm = channel->idtcm;
 678         int err;
 679         int i;
 680         u8 trig_sel;
 681
 682         err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
 683
 684         if (err)
 685                 return err;
 686
 687         /* Wait for the operation to complete. */
 688         for (i = 0; i < 10000; i++) {
 689                 err = idtcm_read(idtcm, channel->hw_dpll_n,
 690                                  HW_DPLL_TOD_CTRL_1, &trig_sel,
 691                                  sizeof(trig_sel));
 692
 693                 if (err)
 694                         return err;
 695
 696                 if (trig_sel == 0x4a)
 697                         break;
 698
 699                 err = 1;
 700         }
 701
 702         if (err) {
 703                 dev_err(&idtcm->client->dev,
 704                         "Failed at line %d in func %s!\n",
 705                         __LINE__,
 706                         __func__);
 707                 return err;
 708         }
 709
 710         return idtcm_sync_pps_output(channel);
 711 }
 712
 713 static int _idtcm_settime_v487(struct idtcm_channel *channel,
 714                                struct timespec64 const *ts,
 715                                enum scsr_tod_write_type_sel wr_type)
 716 {
 717         return _idtcm_set_dpll_scsr_tod(channel, ts,
 718                                         SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
 719                                         wr_type);
 720 }
 721
 722 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
 723                                           s32 offset_ns)
 724 {
 725         int err;
 726         int i;
 727         struct idtcm *idtcm = channel->idtcm;
 728
 729         u8 buf[4];
 730
 731         for (i = 0; i < 4; i++) {
 732                 buf[i] = 0xff & (offset_ns);
 733                 offset_ns >>= 8;
 734         }
 735
 736         err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
 737                           buf, sizeof(buf));
 738
 739         return err;
 740 }
 741
 742 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
 743                                                u32 max_ffo_ppb)
 744 {
 745         int err;
 746         u8 i;
 747         struct idtcm *idtcm = channel->idtcm;
 748
 749         u8 buf[3];
 750
 751         if (max_ffo_ppb & 0xff000000)
 752                 max_ffo_ppb = 0;
 753
 754         for (i = 0; i < 3; i++) {
 755                 buf[i] = 0xff & (max_ffo_ppb);
 756                 max_ffo_ppb >>= 8;
 757         }
 758
 759         err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
 760                           PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
 761
 762         return err;
 763 }
 764
 765 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
 766 {
 767         int err;
 768         struct idtcm *idtcm = channel->idtcm;
 769
 770         u8 buf;
 771
 772         err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
 773                          &buf, sizeof(buf));
 774
 775         if (err)
 776                 return err;
 777
 778         if (buf == 0) {
 779                 buf = 0x01;
 780                 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
 781                                   PULL_IN_CTRL, &buf, sizeof(buf));
 782         } else {
 783                 err = -EBUSY;
 784         }
 785
 786         return err;
 787 }
 788
 789 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
 790                                   s32 offset_ns,
 791                                   u32 max_ffo_ppb)
 792 {
 793         int err;
 794
 795         err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
 796
 797         if (err)
 798                 return err;
 799
 800         err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
 801
 802         if (err)
 803                 return err;
 804
 805         err = idtcm_start_phase_pull_in(channel);
 806
 807         return err;
 808 }
 809
 810 static int set_tod_write_overhead(struct idtcm_channel *channel)
 811 {
 812         struct idtcm *idtcm = channel->idtcm;
 813         s64 current_ns = 0;
 814         s64 lowest_ns = 0;
 815         int err;
 816         u8 i;
 817
 818         ktime_t start;
 819         ktime_t stop;
 820
 821         char buf[TOD_BYTE_COUNT] = {0};
 822
 823         /* Set page offset */
 824         idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
 825                     buf, sizeof(buf));
 826
 827         for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
 828
 829                 start = ktime_get_raw();
 830
 831                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 832                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 833
 834                 if (err)
 835                         return err;
 836
 837                 stop = ktime_get_raw();
 838
 839                 current_ns = ktime_to_ns(stop - start);
 840
 841                 if (i == 0) {
 842                         lowest_ns = current_ns;
 843                 } else {
 844                         if (current_ns < lowest_ns)
 845                                 lowest_ns = current_ns;
 846                 }
 847         }
 848
 849         idtcm->tod_write_overhead_ns = lowest_ns;
 850
 851         return err;
 852 }
 853
 854 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
 855 {
 856         int err;
 857         struct idtcm *idtcm = channel->idtcm;
 858         struct timespec64 ts;
 859         s64 now;
 860
 861         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
 862                 err = idtcm_do_phase_pull_in(channel, delta, 0);
 863         } else {
 864                 idtcm->calculate_overhead_flag = 1;
 865
 866                 err = set_tod_write_overhead(channel);
 867
 868                 if (err)
 869                         return err;
 870
 871                 err = _idtcm_gettime(channel, &ts);
 872
 873                 if (err)
 874                         return err;
 875
 876                 now = timespec64_to_ns(&ts);
 877                 now += delta;
 878
 879                 ts = ns_to_timespec64(now);
 880
 881                 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
 882         }
 883
 884         return err;
 885 }
 886
 887 static int idtcm_state_machine_reset(struct idtcm *idtcm)
 888 {
 889         int err;
 890         u8 byte = SM_RESET_CMD;
 891
 892         err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
 893
 894         if (!err)
 895                 msleep_interruptible(POST_SM_RESET_DELAY_MS);
 896
 897         return err;
 898 }
 899
 900 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
 901 {
 902         return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
 903 }
 904
 905 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
 906 {
 907         int err;
 908         u8 buf[2] = {0};
 909
 910         err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
 911
 912         *product_id = (buf[1] << 8) | buf[0];
 913
 914         return err;
 915 }
 916
 917 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
 918 {
 919         int err;
 920         u8 buf = 0;
 921
 922         err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
 923
 924         *major = buf >> 1;
 925
 926         return err;
 927 }
 928
 929 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
 930 {
 931         return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
 932 }
 933
 934 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
 935 {
 936         return idtcm_read(idtcm,
 937                           GENERAL_STATUS,
 938                           HOTFIX_REL,
 939                           hotfix,
 940                           sizeof(u8));
 941 }
 942
 943 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
 944                                              u8 *config_select)
 945 {
 946         return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
 947                           config_select, sizeof(u8));
 948 }
 949
 950 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
 951 {
 952         int err = 0;
 953
 954         switch (addr) {
 955         case TOD0_OUT_ALIGN_MASK_ADDR:
 956                 SET_U16_LSB(idtcm->channel[0].output_mask, val);
 957                 break;
 958         case TOD0_OUT_ALIGN_MASK_ADDR + 1:
 959                 SET_U16_MSB(idtcm->channel[0].output_mask, val);
 960                 break;
 961         case TOD1_OUT_ALIGN_MASK_ADDR:
 962                 SET_U16_LSB(idtcm->channel[1].output_mask, val);
 963                 break;
 964         case TOD1_OUT_ALIGN_MASK_ADDR + 1:
 965                 SET_U16_MSB(idtcm->channel[1].output_mask, val);
 966                 break;
 967         case TOD2_OUT_ALIGN_MASK_ADDR:
 968                 SET_U16_LSB(idtcm->channel[2].output_mask, val);
 969                 break;
 970         case TOD2_OUT_ALIGN_MASK_ADDR + 1:
 971                 SET_U16_MSB(idtcm->channel[2].output_mask, val);
 972                 break;
 973         case TOD3_OUT_ALIGN_MASK_ADDR:
 974                 SET_U16_LSB(idtcm->channel[3].output_mask, val);
 975                 break;
 976         case TOD3_OUT_ALIGN_MASK_ADDR + 1:
 977                 SET_U16_MSB(idtcm->channel[3].output_mask, val);
 978                 break;
 979         default:
 980                 err = -EFAULT; /* Bad address */;
 981                 break;
 982         }
 983
 984         return err;
 985 }
 986
 987 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
 988 {
 989         if (index >= MAX_TOD) {
 990                 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
 991                 return -EINVAL;
 992         }
 993
 994         if (pll >= MAX_PLL) {
 995                 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
 996                 return -EINVAL;
 997         }
 998
 999         idtcm->channel[index].pll = pll;
1000
1001         return 0;
1002 }
1003
1004 static int check_and_set_masks(struct idtcm *idtcm,
1005                                u16 regaddr,
1006                                u8 val)
1007 {
1008         int err = 0;
1009
1010         switch (regaddr) {
1011         case TOD_MASK_ADDR:
1012                 if ((val & 0xf0) || !(val & 0x0f)) {
1013                         dev_err(&idtcm->client->dev,
1014                                 "Invalid TOD mask 0x%hhx\n", val);
1015                         err = -EINVAL;
1016                 } else {
1017                         idtcm->tod_mask = val;
1018                 }
1019                 break;
1020         case TOD0_PTP_PLL_ADDR:
1021                 err = set_tod_ptp_pll(idtcm, 0, val);
1022                 break;
1023         case TOD1_PTP_PLL_ADDR:
1024                 err = set_tod_ptp_pll(idtcm, 1, val);
1025                 break;
1026         case TOD2_PTP_PLL_ADDR:
1027                 err = set_tod_ptp_pll(idtcm, 2, val);
1028                 break;
1029         case TOD3_PTP_PLL_ADDR:
1030                 err = set_tod_ptp_pll(idtcm, 3, val);
1031                 break;
1032         default:
1033                 err = set_pll_output_mask(idtcm, regaddr, val);
1034                 break;
1035         }
1036
1037         return err;
1038 }
1039
1040 static void display_pll_and_masks(struct idtcm *idtcm)
1041 {
1042         u8 i;
1043         u8 mask;
1044
1045         dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
1046
1047         for (i = 0; i < MAX_TOD; i++) {
1048                 mask = 1 << i;
1049
1050                 if (mask & idtcm->tod_mask)
1051                         dev_dbg(&idtcm->client->dev,
1052                                 "TOD%d pll = %d    output_mask = 0x%04x\n",
1053                                 i, idtcm->channel[i].pll,
1054                                 idtcm->channel[i].output_mask);
1055         }
1056 }
1057
1058 static int idtcm_load_firmware(struct idtcm *idtcm,
1059                                struct device *dev)
1060 {
1061         char fname[128] = FW_FILENAME;
1062         const struct firmware *fw;
1063         struct idtcm_fwrc *rec;
1064         u32 regaddr;
1065         int err;
1066         s32 len;
1067         u8 val;
1068         u8 loaddr;
1069
1070         if (firmware) /* module parameter */
1071                 snprintf(fname, sizeof(fname), "%s", firmware);
1072
1073         dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
1074
1075         err = request_firmware(&fw, fname, dev);
1076
1077         if (err) {
1078                 dev_err(&idtcm->client->dev,
1079                         "Failed at line %d in func %s!\n",
1080                         __LINE__,
1081                         __func__);
1082                 return err;
1083         }
1084
1085         dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1086
1087         rec = (struct idtcm_fwrc *) fw->data;
1088
1089         if (fw->size > 0)
1090                 idtcm_state_machine_reset(idtcm);
1091
1092         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1093
1094                 if (rec->reserved) {
1095                         dev_err(&idtcm->client->dev,
1096                                 "bad firmware, reserved field non-zero\n");
1097                         err = -EINVAL;
1098                 } else {
1099                         regaddr = rec->hiaddr << 8;
1100                         regaddr |= rec->loaddr;
1101
1102                         val = rec->value;
1103                         loaddr = rec->loaddr;
1104
1105                         rec++;
1106
1107                         err = check_and_set_masks(idtcm, regaddr, val);
1108                 }
1109
1110                 if (err != -EINVAL) {
1111                         err = 0;
1112
1113                         /* Top (status registers) and bottom are read-only */
1114                         if ((regaddr < GPIO_USER_CONTROL)
1115                             || (regaddr >= SCRATCH))
1116                                 continue;
1117
1118                         /* Page size 128, last 4 bytes of page skipped */
1119                         if (((loaddr > 0x7b) && (loaddr <= 0x7f))
1120                              || loaddr > 0xfb)
1121                                 continue;
1122
1123                         err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1124                 }
1125
1126                 if (err)
1127                         goto out;
1128         }
1129
1130         display_pll_and_masks(idtcm);
1131
1132 out:
1133         release_firmware(fw);
1134         return err;
1135 }
1136
1137 static int idtcm_output_enable(struct idtcm_channel *channel,
1138                                bool enable, unsigned int outn)
1139 {
1140         struct idtcm *idtcm = channel->idtcm;
1141         int err;
1142         u8 val;
1143
1144         err = idtcm_read(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1145                          OUT_CTRL_1, &val, sizeof(val));
1146
1147         if (err)
1148                 return err;
1149
1150         if (enable)
1151                 val |= SQUELCH_DISABLE;
1152         else
1153                 val &= ~SQUELCH_DISABLE;
1154
1155         return idtcm_write(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1156                            OUT_CTRL_1, &val, sizeof(val));
1157 }
1158
1159 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1160                                     bool enable)
1161 {
1162         u16 mask;
1163         int err;
1164         u8 outn;
1165
1166         mask = channel->output_mask;
1167         outn = 0;
1168
1169         while (mask) {
1170
1171                 if (mask & 0x1) {
1172
1173                         err = idtcm_output_enable(channel, enable, outn);
1174
1175                         if (err)
1176                                 return err;
1177                 }
1178
1179                 mask >>= 0x1;
1180                 outn++;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int idtcm_perout_enable(struct idtcm_channel *channel,
1187                                bool enable,
1188                                struct ptp_perout_request *perout)
1189 {
1190         unsigned int flags = perout->flags;
1191
1192         if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1193                 return idtcm_output_mask_enable(channel, enable);
1194
1195         /* Enable/disable individual output instead */
1196         return idtcm_output_enable(channel, enable, perout->index);
1197 }
1198
1199 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1200                               enum pll_mode pll_mode)
1201 {
1202         struct idtcm *idtcm = channel->idtcm;
1203         int err;
1204         u8 dpll_mode;
1205
1206         err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1207                          &dpll_mode, sizeof(dpll_mode));
1208         if (err)
1209                 return err;
1210
1211         dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1212
1213         dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1214
1215         channel->pll_mode = pll_mode;
1216
1217         err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1218                           &dpll_mode, sizeof(dpll_mode));
1219         if (err)
1220                 return err;
1221
1222         return 0;
1223 }
1224
1225 /* PTP Hardware Clock interface */
1226
1227 /**
1228  * @brief Maximum absolute value for write phase offset in picoseconds
1229  *
1230  * Destination signed register is 32-bit register in resolution of 50ps
1231  *
1232  * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1233  */
1234 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1235 {
1236         struct idtcm *idtcm = channel->idtcm;
1237
1238         int err;
1239         u8 i;
1240         u8 buf[4] = {0};
1241         s32 phase_50ps;
1242         s64 offset_ps;
1243
1244         if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1245
1246                 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1247
1248                 if (err)
1249                         return err;
1250
1251                 channel->write_phase_ready = 0;
1252
1253                 ptp_schedule_worker(channel->ptp_clock,
1254                                     msecs_to_jiffies(WR_PHASE_SETUP_MS));
1255         }
1256
1257         if (!channel->write_phase_ready)
1258                 delta_ns = 0;
1259
1260         offset_ps = (s64)delta_ns * 1000;
1261
1262         /*
1263          * Check for 32-bit signed max * 50:
1264          *
1265          * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1266          */
1267         if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1268                 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1269         else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1270                 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1271
1272         phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1);
1273
1274         for (i = 0; i < 4; i++) {
1275                 buf[i] = phase_50ps & 0xff;
1276                 phase_50ps >>= 8;
1277         }
1278
1279         err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1280                           buf, sizeof(buf));
1281
1282         return err;
1283 }
1284
1285 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1286 {
1287         struct idtcm *idtcm = channel->idtcm;
1288         u8 i;
1289         bool neg_adj = 0;
1290         int err;
1291         u8 buf[6] = {0};
1292         s64 fcw;
1293
1294         if (channel->pll_mode  != PLL_MODE_WRITE_FREQUENCY) {
1295                 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1296                 if (err)
1297                         return err;
1298         }
1299
1300         /*
1301          * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1302          *
1303          * adjfreq:
1304          *       ppb * 10^9
1305          * FCW = ----------
1306          *          111
1307          *
1308          * adjfine:
1309          *       ppm_16 * 5^12
1310          * FCW = -------------
1311          *         111 * 2^4
1312          */
1313         if (scaled_ppm < 0) {
1314                 neg_adj = 1;
1315                 scaled_ppm = -scaled_ppm;
1316         }
1317
1318         /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1319         fcw = scaled_ppm * 244140625ULL;
1320
1321         fcw = div_u64(fcw, 1776);
1322
1323         if (neg_adj)
1324                 fcw = -fcw;
1325
1326         for (i = 0; i < 6; i++) {
1327                 buf[i] = fcw & 0xff;
1328                 fcw >>= 8;
1329         }
1330
1331         err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1332                           buf, sizeof(buf));
1333
1334         return err;
1335 }
1336
1337 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1338 {
1339         struct idtcm_channel *channel =
1340                 container_of(ptp, struct idtcm_channel, caps);
1341         struct idtcm *idtcm = channel->idtcm;
1342         int err;
1343
1344         mutex_lock(&idtcm->reg_lock);
1345
1346         err = _idtcm_gettime(channel, ts);
1347
1348         if (err)
1349                 dev_err(&idtcm->client->dev,
1350                         "Failed at line %d in func %s!\n",
1351                         __LINE__,
1352                         __func__);
1353
1354         mutex_unlock(&idtcm->reg_lock);
1355
1356         return err;
1357 }
1358
1359 static int idtcm_settime(struct ptp_clock_info *ptp,
1360                          const struct timespec64 *ts)
1361 {
1362         struct idtcm_channel *channel =
1363                 container_of(ptp, struct idtcm_channel, caps);
1364         struct idtcm *idtcm = channel->idtcm;
1365         int err;
1366
1367         mutex_lock(&idtcm->reg_lock);
1368
1369         err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
1370
1371         if (err)
1372                 dev_err(&idtcm->client->dev,
1373                         "Failed at line %d in func %s!\n",
1374                         __LINE__,
1375                         __func__);
1376
1377         mutex_unlock(&idtcm->reg_lock);
1378
1379         return err;
1380 }
1381
1382 static int idtcm_settime_v487(struct ptp_clock_info *ptp,
1383                          const struct timespec64 *ts)
1384 {
1385         struct idtcm_channel *channel =
1386                 container_of(ptp, struct idtcm_channel, caps);
1387         struct idtcm *idtcm = channel->idtcm;
1388         int err;
1389
1390         mutex_lock(&idtcm->reg_lock);
1391
1392         err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1393
1394         if (err)
1395                 dev_err(&idtcm->client->dev,
1396                         "Failed at line %d in func %s!\n",
1397                         __LINE__,
1398                         __func__);
1399
1400         mutex_unlock(&idtcm->reg_lock);
1401
1402         return err;
1403 }
1404
1405 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1406 {
1407         struct idtcm_channel *channel =
1408                 container_of(ptp, struct idtcm_channel, caps);
1409         struct idtcm *idtcm = channel->idtcm;
1410         int err;
1411
1412         mutex_lock(&idtcm->reg_lock);
1413
1414         err = _idtcm_adjtime(channel, delta);
1415
1416         if (err)
1417                 dev_err(&idtcm->client->dev,
1418                         "Failed at line %d in func %s!\n",
1419                         __LINE__,
1420                         __func__);
1421
1422         mutex_unlock(&idtcm->reg_lock);
1423
1424         return err;
1425 }
1426
1427 static int idtcm_adjtime_v487(struct ptp_clock_info *ptp, s64 delta)
1428 {
1429         struct idtcm_channel *channel =
1430                 container_of(ptp, struct idtcm_channel, caps);
1431         struct idtcm *idtcm = channel->idtcm;
1432         struct timespec64 ts;
1433         enum scsr_tod_write_type_sel type;
1434         int err;
1435
1436         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_V487) {
1437                 err = idtcm_do_phase_pull_in(channel, delta, 0);
1438                 if (err)
1439                         dev_err(&idtcm->client->dev,
1440                                 "Failed at line %d in func %s!\n",
1441                                 __LINE__,
1442                                 __func__);
1443                 return err;
1444         }
1445
1446         if (delta >= 0) {
1447                 ts = ns_to_timespec64(delta);
1448                 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1449         } else {
1450                 ts = ns_to_timespec64(-delta);
1451                 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1452         }
1453
1454         mutex_lock(&idtcm->reg_lock);
1455
1456         err = _idtcm_settime_v487(channel, &ts, type);
1457
1458         if (err)
1459                 dev_err(&idtcm->client->dev,
1460                         "Failed at line %d in func %s!\n",
1461                         __LINE__,
1462                         __func__);
1463
1464         mutex_unlock(&idtcm->reg_lock);
1465
1466         return err;
1467 }
1468
1469 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1470 {
1471         struct idtcm_channel *channel =
1472                 container_of(ptp, struct idtcm_channel, caps);
1473
1474         struct idtcm *idtcm = channel->idtcm;
1475
1476         int err;
1477
1478         mutex_lock(&idtcm->reg_lock);
1479
1480         err = _idtcm_adjphase(channel, delta);
1481
1482         if (err)
1483                 dev_err(&idtcm->client->dev,
1484                         "Failed at line %d in func %s!\n",
1485                         __LINE__,
1486                         __func__);
1487
1488         mutex_unlock(&idtcm->reg_lock);
1489
1490         return err;
1491 }
1492
1493 static int idtcm_adjfine(struct ptp_clock_info *ptp,  long scaled_ppm)
1494 {
1495         struct idtcm_channel *channel =
1496                 container_of(ptp, struct idtcm_channel, caps);
1497
1498         struct idtcm *idtcm = channel->idtcm;
1499
1500         int err;
1501
1502         mutex_lock(&idtcm->reg_lock);
1503
1504         err = _idtcm_adjfine(channel, scaled_ppm);
1505
1506         if (err)
1507                 dev_err(&idtcm->client->dev,
1508                         "Failed at line %d in func %s!\n",
1509                         __LINE__,
1510                         __func__);
1511
1512         mutex_unlock(&idtcm->reg_lock);
1513
1514         return err;
1515 }
1516
1517 static int idtcm_enable(struct ptp_clock_info *ptp,
1518                         struct ptp_clock_request *rq, int on)
1519 {
1520         int err;
1521
1522         struct idtcm_channel *channel =
1523                 container_of(ptp, struct idtcm_channel, caps);
1524
1525         switch (rq->type) {
1526         case PTP_CLK_REQ_PEROUT:
1527                 if (!on) {
1528                         err = idtcm_perout_enable(channel, false, &rq->perout);
1529                         if (err)
1530                                 dev_err(&channel->idtcm->client->dev,
1531                                         "Failed at line %d in func %s!\n",
1532                                         __LINE__,
1533                                         __func__);
1534                         return err;
1535                 }
1536
1537                 /* Only accept a 1-PPS aligned to the second. */
1538                 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1539                     rq->perout.period.nsec)
1540                         return -ERANGE;
1541
1542                 err = idtcm_perout_enable(channel, true, &rq->perout);
1543                 if (err)
1544                         dev_err(&channel->idtcm->client->dev,
1545                                 "Failed at line %d in func %s!\n",
1546                                 __LINE__,
1547                                 __func__);
1548                 return err;
1549         default:
1550                 break;
1551         }
1552
1553         return -EOPNOTSUPP;
1554 }
1555
1556 static int _enable_pll_tod_sync(struct idtcm *idtcm,
1557                                 u8 pll,
1558                                 u8 sync_src,
1559                                 u8 qn,
1560                                 u8 qn_plus_1)
1561 {
1562         int err;
1563         u8 val;
1564         u16 dpll;
1565         u16 out0 = 0, out1 = 0;
1566
1567         if ((qn == 0) && (qn_plus_1 == 0))
1568                 return 0;
1569
1570         switch (pll) {
1571         case 0:
1572                 dpll = DPLL_0;
1573                 if (qn)
1574                         out0 = OUTPUT_0;
1575                 if (qn_plus_1)
1576                         out1 = OUTPUT_1;
1577                 break;
1578         case 1:
1579                 dpll = DPLL_1;
1580                 if (qn)
1581                         out0 = OUTPUT_2;
1582                 if (qn_plus_1)
1583                         out1 = OUTPUT_3;
1584                 break;
1585         case 2:
1586                 dpll = DPLL_2;
1587                 if (qn)
1588                         out0 = OUTPUT_4;
1589                 if (qn_plus_1)
1590                         out1 = OUTPUT_5;
1591                 break;
1592         case 3:
1593                 dpll = DPLL_3;
1594                 if (qn)
1595                         out0 = OUTPUT_6;
1596                 if (qn_plus_1)
1597                         out1 = OUTPUT_7;
1598                 break;
1599         case 4:
1600                 dpll = DPLL_4;
1601                 if (qn)
1602                         out0 = OUTPUT_8;
1603                 break;
1604         case 5:
1605                 dpll = DPLL_5;
1606                 if (qn)
1607                         out0 = OUTPUT_9;
1608                 if (qn_plus_1)
1609                         out1 = OUTPUT_8;
1610                 break;
1611         case 6:
1612                 dpll = DPLL_6;
1613                 if (qn)
1614                         out0 = OUTPUT_10;
1615                 if (qn_plus_1)
1616                         out1 = OUTPUT_11;
1617                 break;
1618         case 7:
1619                 dpll = DPLL_7;
1620                 if (qn)
1621                         out0 = OUTPUT_11;
1622                 break;
1623         default:
1624                 return -EINVAL;
1625         }
1626
1627         /*
1628          * Enable OUTPUT OUT_SYNC.
1629          */
1630         if (out0) {
1631                 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1632
1633                 if (err)
1634                         return err;
1635
1636                 val &= ~OUT_SYNC_DISABLE;
1637
1638                 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1639
1640                 if (err)
1641                         return err;
1642         }
1643
1644         if (out1) {
1645                 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1646
1647                 if (err)
1648                         return err;
1649
1650                 val &= ~OUT_SYNC_DISABLE;
1651
1652                 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1653
1654                 if (err)
1655                         return err;
1656         }
1657
1658         /* enable dpll sync tod pps, must be set before dpll_mode */
1659         err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1660         if (err)
1661                 return err;
1662
1663         val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1664         val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1665         val |= TOD_SYNC_EN;
1666
1667         return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1668 }
1669
1670 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1671 {
1672         struct idtcm *idtcm = channel->idtcm;
1673
1674         u8 pll;
1675         u8 sync_src;
1676         u8 qn;
1677         u8 qn_plus_1;
1678         u8 cfg;
1679         int err = 0;
1680         u16 output_mask = channel->output_mask;
1681         u8 out8_mux = 0;
1682         u8 out11_mux = 0;
1683         u8 temp;
1684
1685         /*
1686          * set tod_out_sync_enable to 0.
1687          */
1688         err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1689         if (err)
1690                 return err;
1691
1692         cfg &= ~TOD_OUT_SYNC_ENABLE;
1693
1694         err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1695         if (err)
1696                 return err;
1697
1698         switch (channel->tod_n) {
1699         case TOD_0:
1700                 sync_src = 0;
1701                 break;
1702         case TOD_1:
1703                 sync_src = 1;
1704                 break;
1705         case TOD_2:
1706                 sync_src = 2;
1707                 break;
1708         case TOD_3:
1709                 sync_src = 3;
1710                 break;
1711         default:
1712                 return -EINVAL;
1713         }
1714
1715         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1716                          &temp, sizeof(temp));
1717         if (err)
1718                 return err;
1719
1720         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1721             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1722                 out8_mux = 1;
1723
1724         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1725                          &temp, sizeof(temp));
1726         if (err)
1727                 return err;
1728
1729         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1730             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1731                 out11_mux = 1;
1732
1733         for (pll = 0; pll < 8; pll++) {
1734                 qn = 0;
1735                 qn_plus_1 = 0;
1736
1737                 if (pll < 4) {
1738                         /* First 4 pll has 2 outputs */
1739                         qn = output_mask & 0x1;
1740                         output_mask = output_mask >> 1;
1741                         qn_plus_1 = output_mask & 0x1;
1742                         output_mask = output_mask >> 1;
1743                 } else if (pll == 4) {
1744                         if (out8_mux == 0) {
1745                                 qn = output_mask & 0x1;
1746                                 output_mask = output_mask >> 1;
1747                         }
1748                 } else if (pll == 5) {
1749                         if (out8_mux) {
1750                                 qn_plus_1 = output_mask & 0x1;
1751                                 output_mask = output_mask >> 1;
1752                         }
1753                         qn = output_mask & 0x1;
1754                         output_mask = output_mask >> 1;
1755                 } else if (pll == 6) {
1756                         qn = output_mask & 0x1;
1757                         output_mask = output_mask >> 1;
1758                         if (out11_mux) {
1759                                 qn_plus_1 = output_mask & 0x1;
1760                                 output_mask = output_mask >> 1;
1761                         }
1762                 } else if (pll == 7) {
1763                         if (out11_mux == 0) {
1764                                 qn = output_mask & 0x1;
1765                                 output_mask = output_mask >> 1;
1766                         }
1767                 }
1768
1769                 if ((qn != 0) || (qn_plus_1 != 0))
1770                         err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1771                                                qn_plus_1);
1772
1773                 if (err)
1774                         return err;
1775         }
1776
1777         return err;
1778 }
1779
1780 static int idtcm_enable_tod(struct idtcm_channel *channel)
1781 {
1782         struct idtcm *idtcm = channel->idtcm;
1783         struct timespec64 ts = {0, 0};
1784         u8 cfg;
1785         int err;
1786
1787         /*
1788          * Start the TOD clock ticking.
1789          */
1790         err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1791         if (err)
1792                 return err;
1793
1794         cfg |= TOD_ENABLE;
1795
1796         err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1797         if (err)
1798                 return err;
1799
1800         return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
1801 }
1802
1803 static void idtcm_display_version_info(struct idtcm *idtcm)
1804 {
1805         u8 major;
1806         u8 minor;
1807         u8 hotfix;
1808         u16 product_id;
1809         u8 hw_rev_id;
1810         u8 config_select;
1811         char *fmt = "%d.%d.%d, Id: 0x%04x  HW Rev: %d  OTP Config Select: %d\n";
1812
1813         idtcm_read_major_release(idtcm, &major);
1814         idtcm_read_minor_release(idtcm, &minor);
1815         idtcm_read_hotfix_release(idtcm, &hotfix);
1816
1817         idtcm_read_product_id(idtcm, &product_id);
1818         idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1819
1820         idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1821
1822         snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1823                  major, minor, hotfix);
1824
1825         dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
1826                  product_id, hw_rev_id, config_select);
1827 }
1828
1829 static const struct ptp_clock_info idtcm_caps_v487 = {
1830         .owner          = THIS_MODULE,
1831         .max_adj        = 244000,
1832         .n_per_out      = 12,
1833         .adjphase       = &idtcm_adjphase,
1834         .adjfine        = &idtcm_adjfine,
1835         .adjtime        = &idtcm_adjtime_v487,
1836         .gettime64      = &idtcm_gettime,
1837         .settime64      = &idtcm_settime_v487,
1838         .enable         = &idtcm_enable,
1839         .do_aux_work    = &set_write_phase_ready,
1840 };
1841
1842 static const struct ptp_clock_info idtcm_caps = {
1843         .owner          = THIS_MODULE,
1844         .max_adj        = 244000,
1845         .n_per_out      = 12,
1846         .adjphase       = &idtcm_adjphase,
1847         .adjfine        = &idtcm_adjfine,
1848         .adjtime        = &idtcm_adjtime,
1849         .gettime64      = &idtcm_gettime,
1850         .settime64      = &idtcm_settime,
1851         .enable         = &idtcm_enable,
1852         .do_aux_work    = &set_write_phase_ready,
1853 };
1854
1855 static int configure_channel_pll(struct idtcm_channel *channel)
1856 {
1857         int err = 0;
1858
1859         switch (channel->pll) {
1860         case 0:
1861                 channel->dpll_freq = DPLL_FREQ_0;
1862                 channel->dpll_n = DPLL_0;
1863                 channel->hw_dpll_n = HW_DPLL_0;
1864                 channel->dpll_phase = DPLL_PHASE_0;
1865                 channel->dpll_ctrl_n = DPLL_CTRL_0;
1866                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1867                 break;
1868         case 1:
1869                 channel->dpll_freq = DPLL_FREQ_1;
1870                 channel->dpll_n = DPLL_1;
1871                 channel->hw_dpll_n = HW_DPLL_1;
1872                 channel->dpll_phase = DPLL_PHASE_1;
1873                 channel->dpll_ctrl_n = DPLL_CTRL_1;
1874                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1875                 break;
1876         case 2:
1877                 channel->dpll_freq = DPLL_FREQ_2;
1878                 channel->dpll_n = DPLL_2;
1879                 channel->hw_dpll_n = HW_DPLL_2;
1880                 channel->dpll_phase = DPLL_PHASE_2;
1881                 channel->dpll_ctrl_n = DPLL_CTRL_2;
1882                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
1883                 break;
1884         case 3:
1885                 channel->dpll_freq = DPLL_FREQ_3;
1886                 channel->dpll_n = DPLL_3;
1887                 channel->hw_dpll_n = HW_DPLL_3;
1888                 channel->dpll_phase = DPLL_PHASE_3;
1889                 channel->dpll_ctrl_n = DPLL_CTRL_3;
1890                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
1891                 break;
1892         case 4:
1893                 channel->dpll_freq = DPLL_FREQ_4;
1894                 channel->dpll_n = DPLL_4;
1895                 channel->hw_dpll_n = HW_DPLL_4;
1896                 channel->dpll_phase = DPLL_PHASE_4;
1897                 channel->dpll_ctrl_n = DPLL_CTRL_4;
1898                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
1899                 break;
1900         case 5:
1901                 channel->dpll_freq = DPLL_FREQ_5;
1902                 channel->dpll_n = DPLL_5;
1903                 channel->hw_dpll_n = HW_DPLL_5;
1904                 channel->dpll_phase = DPLL_PHASE_5;
1905                 channel->dpll_ctrl_n = DPLL_CTRL_5;
1906                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
1907                 break;
1908         case 6:
1909                 channel->dpll_freq = DPLL_FREQ_6;
1910                 channel->dpll_n = DPLL_6;
1911                 channel->hw_dpll_n = HW_DPLL_6;
1912                 channel->dpll_phase = DPLL_PHASE_6;
1913                 channel->dpll_ctrl_n = DPLL_CTRL_6;
1914                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
1915                 break;
1916         case 7:
1917                 channel->dpll_freq = DPLL_FREQ_7;
1918                 channel->dpll_n = DPLL_7;
1919                 channel->hw_dpll_n = HW_DPLL_7;
1920                 channel->dpll_phase = DPLL_PHASE_7;
1921                 channel->dpll_ctrl_n = DPLL_CTRL_7;
1922                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
1923                 break;
1924         default:
1925                 err = -EINVAL;
1926         }
1927
1928         return err;
1929 }
1930
1931 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
1932 {
1933         struct idtcm_channel *channel;
1934         int err;
1935
1936         if (!(index < MAX_TOD))
1937                 return -EINVAL;
1938
1939         channel = &idtcm->channel[index];
1940
1941         /* Set pll addresses */
1942         err = configure_channel_pll(channel);
1943         if (err)
1944                 return err;
1945
1946         /* Set tod addresses */
1947         switch (index) {
1948         case 0:
1949                 channel->tod_read_primary = TOD_READ_PRIMARY_0;
1950                 channel->tod_write = TOD_WRITE_0;
1951                 channel->tod_n = TOD_0;
1952                 break;
1953         case 1:
1954                 channel->tod_read_primary = TOD_READ_PRIMARY_1;
1955                 channel->tod_write = TOD_WRITE_1;
1956                 channel->tod_n = TOD_1;
1957                 break;
1958         case 2:
1959                 channel->tod_read_primary = TOD_READ_PRIMARY_2;
1960                 channel->tod_write = TOD_WRITE_2;
1961                 channel->tod_n = TOD_2;
1962                 break;
1963         case 3:
1964                 channel->tod_read_primary = TOD_READ_PRIMARY_3;
1965                 channel->tod_write = TOD_WRITE_3;
1966                 channel->tod_n = TOD_3;
1967                 break;
1968         default:
1969                 return -EINVAL;
1970         }
1971
1972         channel->idtcm = idtcm;
1973
1974         if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
1975                 channel->caps = idtcm_caps_v487;
1976         else
1977                 channel->caps = idtcm_caps;
1978
1979         snprintf(channel->caps.name, sizeof(channel->caps.name),
1980                  "IDT CM TOD%u", index);
1981
1982         if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) {
1983                 err = idtcm_enable_tod_sync(channel);
1984                 if (err) {
1985                         dev_err(&idtcm->client->dev,
1986                                 "Failed at line %d in func %s!\n",
1987                                 __LINE__,
1988                                 __func__);
1989                         return err;
1990                 }
1991         }
1992
1993         err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1994         if (err) {
1995                 dev_err(&idtcm->client->dev,
1996                         "Failed at line %d in func %s!\n",
1997                         __LINE__,
1998                         __func__);
1999                 return err;
2000         }
2001
2002         err = idtcm_enable_tod(channel);
2003         if (err) {
2004                 dev_err(&idtcm->client->dev,
2005                         "Failed at line %d in func %s!\n",
2006                         __LINE__,
2007                         __func__);
2008                 return err;
2009         }
2010
2011         channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2012
2013         if (IS_ERR(channel->ptp_clock)) {
2014                 err = PTR_ERR(channel->ptp_clock);
2015                 channel->ptp_clock = NULL;
2016                 return err;
2017         }
2018
2019         if (!channel->ptp_clock)
2020                 return -ENOTSUPP;
2021
2022         channel->write_phase_ready = 0;
2023
2024         dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2025                  index, channel->ptp_clock->index);
2026
2027         return 0;
2028 }
2029
2030 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2031 {
2032         u8 i;
2033         struct idtcm_channel *channel;
2034
2035         for (i = 0; i < MAX_TOD; i++) {
2036
2037                 channel = &idtcm->channel[i];
2038
2039                 if (channel->ptp_clock)
2040                         ptp_clock_unregister(channel->ptp_clock);
2041         }
2042 }
2043
2044 static void set_default_masks(struct idtcm *idtcm)
2045 {
2046         idtcm->tod_mask = DEFAULT_TOD_MASK;
2047
2048         idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2049         idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2050         idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2051         idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2052
2053         idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2054         idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2055         idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2056         idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2057 }
2058
2059 static int idtcm_probe(struct i2c_client *client,
2060                        const struct i2c_device_id *id)
2061 {
2062         struct idtcm *idtcm;
2063         int err;
2064         u8 i;
2065         char *fmt = "Failed at %d in line %s with channel output %d!\n";
2066
2067         /* Unused for now */
2068         (void)id;
2069
2070         idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2071
2072         if (!idtcm)
2073                 return -ENOMEM;
2074
2075         idtcm->client = client;
2076         idtcm->page_offset = 0xff;
2077         idtcm->calculate_overhead_flag = 0;
2078
2079         set_default_masks(idtcm);
2080
2081         mutex_init(&idtcm->reg_lock);
2082         mutex_lock(&idtcm->reg_lock);
2083
2084         idtcm_display_version_info(idtcm);
2085
2086         err = idtcm_load_firmware(idtcm, &client->dev);
2087
2088         if (err)
2089                 dev_warn(&idtcm->client->dev,
2090                          "loading firmware failed with %d\n", err);
2091
2092         if (idtcm->tod_mask) {
2093                 for (i = 0; i < MAX_TOD; i++) {
2094                         if (idtcm->tod_mask & (1 << i)) {
2095                                 err = idtcm_enable_channel(idtcm, i);
2096                                 if (err) {
2097                                         dev_err(&idtcm->client->dev,
2098                                                 fmt,
2099                                                 __LINE__,
2100                                                 __func__,
2101                                                 i);
2102                                         break;
2103                                 }
2104                         }
2105                 }
2106         } else {
2107                 dev_err(&idtcm->client->dev,
2108                         "no PLLs flagged as PHCs, nothing to do\n");
2109                 err = -ENODEV;
2110         }
2111
2112         mutex_unlock(&idtcm->reg_lock);
2113
2114         if (err) {
2115                 ptp_clock_unregister_all(idtcm);
2116                 return err;
2117         }
2118
2119         i2c_set_clientdata(client, idtcm);
2120
2121         return 0;
2122 }
2123
2124 static int idtcm_remove(struct i2c_client *client)
2125 {
2126         struct idtcm *idtcm = i2c_get_clientdata(client);
2127
2128         ptp_clock_unregister_all(idtcm);
2129
2130         mutex_destroy(&idtcm->reg_lock);
2131
2132         return 0;
2133 }
2134
2135 #ifdef CONFIG_OF
2136 static const struct of_device_id idtcm_dt_id[] = {
2137         { .compatible = "idt,8a34000" },
2138         { .compatible = "idt,8a34001" },
2139         { .compatible = "idt,8a34002" },
2140         { .compatible = "idt,8a34003" },
2141         { .compatible = "idt,8a34004" },
2142         { .compatible = "idt,8a34005" },
2143         { .compatible = "idt,8a34006" },
2144         { .compatible = "idt,8a34007" },
2145         { .compatible = "idt,8a34008" },
2146         { .compatible = "idt,8a34009" },
2147         { .compatible = "idt,8a34010" },
2148         { .compatible = "idt,8a34011" },
2149         { .compatible = "idt,8a34012" },
2150         { .compatible = "idt,8a34013" },
2151         { .compatible = "idt,8a34014" },
2152         { .compatible = "idt,8a34015" },
2153         { .compatible = "idt,8a34016" },
2154         { .compatible = "idt,8a34017" },
2155         { .compatible = "idt,8a34018" },
2156         { .compatible = "idt,8a34019" },
2157         { .compatible = "idt,8a34040" },
2158         { .compatible = "idt,8a34041" },
2159         { .compatible = "idt,8a34042" },
2160         { .compatible = "idt,8a34043" },
2161         { .compatible = "idt,8a34044" },
2162         { .compatible = "idt,8a34045" },
2163         { .compatible = "idt,8a34046" },
2164         { .compatible = "idt,8a34047" },
2165         { .compatible = "idt,8a34048" },
2166         { .compatible = "idt,8a34049" },
2167         {},
2168 };
2169 MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2170 #endif
2171
2172 static const struct i2c_device_id idtcm_i2c_id[] = {
2173         { "8a34000" },
2174         { "8a34001" },
2175         { "8a34002" },
2176         { "8a34003" },
2177         { "8a34004" },
2178         { "8a34005" },
2179         { "8a34006" },
2180         { "8a34007" },
2181         { "8a34008" },
2182         { "8a34009" },
2183         { "8a34010" },
2184         { "8a34011" },
2185         { "8a34012" },
2186         { "8a34013" },
2187         { "8a34014" },
2188         { "8a34015" },
2189         { "8a34016" },
2190         { "8a34017" },
2191         { "8a34018" },
2192         { "8a34019" },
2193         { "8a34040" },
2194         { "8a34041" },
2195         { "8a34042" },
2196         { "8a34043" },
2197         { "8a34044" },
2198         { "8a34045" },
2199         { "8a34046" },
2200         { "8a34047" },
2201         { "8a34048" },
2202         { "8a34049" },
2203         {},
2204 };
2205 MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2206
2207 static struct i2c_driver idtcm_driver = {
2208         .driver = {
2209                 .of_match_table = of_match_ptr(idtcm_dt_id),
2210                 .name           = "idtcm",
2211         },
2212         .probe          = idtcm_probe,
2213         .remove         = idtcm_remove,
2214         .id_table       = idtcm_i2c_id,
2215 };
2216
2217 module_i2c_driver(idtcm_driver);