1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019
5 * https://github.com/richardcochran/regen
7 * Hand modified to include some HW registers.
8 * Based on 4.8.0, SCSR rev C commit a03c7ae5
10 #ifndef HAVE_IDT8A340_REG
11 #define HAVE_IDT8A340_REG
13 #define PAGE_ADDR_BASE 0x0000
14 #define PAGE_ADDR 0x00fc
16 #define HW_REVISION 0x8180
19 #define HW_DPLL_0 (0x8a00)
20 #define HW_DPLL_1 (0x8b00)
21 #define HW_DPLL_2 (0x8c00)
22 #define HW_DPLL_3 (0x8d00)
24 #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
25 #define HW_DPLL_TOD_CTRL_1 (0x089)
26 #define HW_DPLL_TOD_CTRL_2 (0x08A)
27 #define HW_DPLL_TOD_OVR__0 (0x098)
28 #define HW_DPLL_TOD_OUT_0__0 (0x0B0)
30 #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
31 #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
32 #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
33 #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
34 #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
35 #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
36 #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
37 #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
38 #define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
39 #define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
40 #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
41 #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
42 #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
43 #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
44 #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
45 #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
47 #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
48 #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
49 #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
50 #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
52 #define SYNCTRL1_MASTER_SYNC_RST BIT(7)
53 #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
54 #define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
55 #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
56 #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
57 #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
58 #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
60 #define RESET_CTRL 0xc000
61 #define SM_RESET 0x0012
62 #define SM_RESET_CMD 0x5A
64 #define GENERAL_STATUS 0xc014
65 #define HW_REV_ID 0x000A
66 #define BOND_ID 0x000B
67 #define HW_CSR_ID 0x000C
68 #define HW_IRQ_ID 0x000E
70 #define MAJ_REL 0x0010
71 #define MIN_REL 0x0011
72 #define HOTFIX_REL 0x0012
74 #define PIPELINE_ID 0x0014
75 #define BUILD_ID 0x0018
77 #define JTAG_DEVICE_ID 0x001c
78 #define PRODUCT_ID 0x001e
81 #define USER_GPIO0_TO_7_STATUS 0x008a
82 #define USER_GPIO8_TO_15_STATUS 0x008b
84 #define GPIO_USER_CONTROL 0xc160
85 #define GPIO0_TO_7_OUT 0x0000
86 #define GPIO8_TO_15_OUT 0x0001
88 #define STICKY_STATUS_CLEAR 0xc164
90 #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
92 #define ALERT_CFG 0xc188
94 #define SYS_DPLL_XO 0xc194
96 #define SYS_APLL 0xc19c
98 #define INPUT_0 0xc1b0
100 #define INPUT_1 0xc1c0
102 #define INPUT_2 0xc1d0
104 #define INPUT_3 0xc200
106 #define INPUT_4 0xc210
108 #define INPUT_5 0xc220
110 #define INPUT_6 0xc230
112 #define INPUT_7 0xc240
114 #define INPUT_8 0xc250
116 #define INPUT_9 0xc260
118 #define INPUT_10 0xc280
120 #define INPUT_11 0xc290
122 #define INPUT_12 0xc2a0
124 #define INPUT_13 0xc2b0
126 #define INPUT_14 0xc2c0
128 #define INPUT_15 0xc2d0
130 #define REF_MON_0 0xc2e0
132 #define REF_MON_1 0xc2ec
134 #define REF_MON_2 0xc300
136 #define REF_MON_3 0xc30c
138 #define REF_MON_4 0xc318
140 #define REF_MON_5 0xc324
142 #define REF_MON_6 0xc330
144 #define REF_MON_7 0xc33c
146 #define REF_MON_8 0xc348
148 #define REF_MON_9 0xc354
150 #define REF_MON_10 0xc360
152 #define REF_MON_11 0xc36c
154 #define REF_MON_12 0xc380
156 #define REF_MON_13 0xc38c
158 #define REF_MON_14 0xc398
160 #define REF_MON_15 0xc3a4
162 #define DPLL_0 0xc3b0
163 #define DPLL_CTRL_REG_0 0x0002
164 #define DPLL_CTRL_REG_1 0x0003
165 #define DPLL_CTRL_REG_2 0x0004
166 #define DPLL_TOD_SYNC_CFG 0x0031
167 #define DPLL_COMBO_SLAVE_CFG_0 0x0032
168 #define DPLL_COMBO_SLAVE_CFG_1 0x0033
169 #define DPLL_SLAVE_REF_CFG 0x0034
170 #define DPLL_REF_MODE 0x0035
171 #define DPLL_PHASE_MEASUREMENT_CFG 0x0036
172 #define DPLL_MODE 0x0037
174 #define DPLL_1 0xc400
176 #define DPLL_2 0xc438
178 #define DPLL_3 0xc480
180 #define DPLL_4 0xc4b8
182 #define DPLL_5 0xc500
184 #define DPLL_6 0xc538
186 #define DPLL_7 0xc580
188 #define SYS_DPLL 0xc5b8
190 #define DPLL_CTRL_0 0xc600
191 #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
193 #define DPLL_CTRL_1 0xc63c
195 #define DPLL_CTRL_2 0xc680
197 #define DPLL_CTRL_3 0xc6bc
199 #define DPLL_CTRL_4 0xc700
201 #define DPLL_CTRL_5 0xc73c
203 #define DPLL_CTRL_6 0xc780
205 #define DPLL_CTRL_7 0xc7bc
207 #define SYS_DPLL_CTRL 0xc800
209 #define DPLL_PHASE_0 0xc818
211 /* Signed 42-bit FFO in units of 2^(-53) */
212 #define DPLL_WR_PHASE 0x0000
214 #define DPLL_PHASE_1 0xc81c
216 #define DPLL_PHASE_2 0xc820
218 #define DPLL_PHASE_3 0xc824
220 #define DPLL_PHASE_4 0xc828
222 #define DPLL_PHASE_5 0xc82c
224 #define DPLL_PHASE_6 0xc830
226 #define DPLL_PHASE_7 0xc834
228 #define DPLL_FREQ_0 0xc838
230 /* Signed 42-bit FFO in units of 2^(-53) */
231 #define DPLL_WR_FREQ 0x0000
233 #define DPLL_FREQ_1 0xc840
235 #define DPLL_FREQ_2 0xc848
237 #define DPLL_FREQ_3 0xc850
239 #define DPLL_FREQ_4 0xc858
241 #define DPLL_FREQ_5 0xc860
243 #define DPLL_FREQ_6 0xc868
245 #define DPLL_FREQ_7 0xc870
247 #define DPLL_PHASE_PULL_IN_0 0xc880
248 #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
249 #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
250 #define PULL_IN_CTRL 0x0007
252 #define DPLL_PHASE_PULL_IN_1 0xc888
254 #define DPLL_PHASE_PULL_IN_2 0xc890
256 #define DPLL_PHASE_PULL_IN_3 0xc898
258 #define DPLL_PHASE_PULL_IN_4 0xc8a0
260 #define DPLL_PHASE_PULL_IN_5 0xc8a8
262 #define DPLL_PHASE_PULL_IN_6 0xc8b0
264 #define DPLL_PHASE_PULL_IN_7 0xc8b8
266 #define GPIO_CFG 0xc8c0
267 #define GPIO_CFG_GBL 0x0000
269 #define GPIO_0 0xc8c2
270 #define GPIO_DCO_INC_DEC 0x0000
271 #define GPIO_OUT_CTRL_0 0x0001
272 #define GPIO_OUT_CTRL_1 0x0002
273 #define GPIO_TOD_TRIG 0x0003
274 #define GPIO_DPLL_INDICATOR 0x0004
275 #define GPIO_LOS_INDICATOR 0x0005
276 #define GPIO_REF_INPUT_DSQ_0 0x0006
277 #define GPIO_REF_INPUT_DSQ_1 0x0007
278 #define GPIO_REF_INPUT_DSQ_2 0x0008
279 #define GPIO_REF_INPUT_DSQ_3 0x0009
280 #define GPIO_MAN_CLK_SEL_0 0x000a
281 #define GPIO_MAN_CLK_SEL_1 0x000b
282 #define GPIO_MAN_CLK_SEL_2 0x000c
283 #define GPIO_SLAVE 0x000d
284 #define GPIO_ALERT_OUT_CFG 0x000e
285 #define GPIO_TOD_NOTIFICATION_CFG 0x000f
286 #define GPIO_CTRL 0x0010
288 #define GPIO_1 0xc8d4
290 #define GPIO_2 0xc8e6
292 #define GPIO_3 0xc900
294 #define GPIO_4 0xc912
296 #define GPIO_5 0xc924
298 #define GPIO_6 0xc936
300 #define GPIO_7 0xc948
302 #define GPIO_8 0xc95a
304 #define GPIO_9 0xc980
306 #define GPIO_10 0xc992
308 #define GPIO_11 0xc9a4
310 #define GPIO_12 0xc9b6
312 #define GPIO_13 0xc9c8
314 #define GPIO_14 0xc9da
316 #define GPIO_15 0xca00
318 #define OUT_DIV_MUX 0xca12
320 #define OUTPUT_0 0xca14
321 /* FOD frequency output divider value */
322 #define OUT_DIV 0x0000
323 #define OUT_DUTY_CYCLE_HIGH 0x0004
324 #define OUT_CTRL_0 0x0008
325 #define OUT_CTRL_1 0x0009
326 /* Phase adjustment in FOD cycles */
327 #define OUT_PHASE_ADJ 0x000c
329 #define OUTPUT_1 0xca24
331 #define OUTPUT_2 0xca34
333 #define OUTPUT_3 0xca44
335 #define OUTPUT_4 0xca54
337 #define OUTPUT_5 0xca64
339 #define OUTPUT_6 0xca80
341 #define OUTPUT_7 0xca90
343 #define OUTPUT_8 0xcaa0
345 #define OUTPUT_9 0xcab0
347 #define OUTPUT_10 0xcac0
349 #define OUTPUT_11 0xcad0
351 #define SERIAL 0xcae0
353 #define PWM_ENCODER_0 0xcb00
355 #define PWM_ENCODER_1 0xcb08
357 #define PWM_ENCODER_2 0xcb10
359 #define PWM_ENCODER_3 0xcb18
361 #define PWM_ENCODER_4 0xcb20
363 #define PWM_ENCODER_5 0xcb28
365 #define PWM_ENCODER_6 0xcb30
367 #define PWM_ENCODER_7 0xcb38
369 #define PWM_DECODER_0 0xcb40
371 #define PWM_DECODER_1 0xcb48
373 #define PWM_DECODER_2 0xcb50
375 #define PWM_DECODER_3 0xcb58
377 #define PWM_DECODER_4 0xcb60
379 #define PWM_DECODER_5 0xcb68
381 #define PWM_DECODER_6 0xcb70
383 #define PWM_DECODER_7 0xcb80
385 #define PWM_DECODER_8 0xcb88
387 #define PWM_DECODER_9 0xcb90
389 #define PWM_DECODER_10 0xcb98
391 #define PWM_DECODER_11 0xcba0
393 #define PWM_DECODER_12 0xcba8
395 #define PWM_DECODER_13 0xcbb0
397 #define PWM_DECODER_14 0xcbb8
399 #define PWM_DECODER_15 0xcbc0
401 #define PWM_USER_DATA 0xcbc8
405 /* Enable TOD counter, output channel sync and even-PPS mode */
406 #define TOD_CFG 0x0000
415 #define TOD_WRITE_0 0xcc00
416 /* 8-bit subns, 32-bit ns, 48-bit seconds */
417 #define TOD_WRITE 0x0000
418 /* Counter increments after TOD write is completed */
419 #define TOD_WRITE_COUNTER 0x000c
420 /* TOD write trigger configuration */
421 #define TOD_WRITE_SELECT_CFG_0 0x000d
422 /* TOD write trigger selection */
423 #define TOD_WRITE_CMD 0x000f
425 #define TOD_WRITE_1 0xcc10
427 #define TOD_WRITE_2 0xcc20
429 #define TOD_WRITE_3 0xcc30
431 #define TOD_READ_PRIMARY_0 0xcc40
432 /* 8-bit subns, 32-bit ns, 48-bit seconds */
433 #define TOD_READ_PRIMARY 0x0000
434 /* Counter increments after TOD write is completed */
435 #define TOD_READ_PRIMARY_COUNTER 0x000b
436 /* Read trigger configuration */
437 #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
438 /* Read trigger selection */
439 #define TOD_READ_PRIMARY_CMD 0x000e
441 #define TOD_READ_PRIMARY_1 0xcc50
443 #define TOD_READ_PRIMARY_2 0xcc60
445 #define TOD_READ_PRIMARY_3 0xcc80
447 #define TOD_READ_SECONDARY_0 0xcc90
449 #define TOD_READ_SECONDARY_1 0xcca0
451 #define TOD_READ_SECONDARY_2 0xccb0
453 #define TOD_READ_SECONDARY_3 0xccc0
455 #define OUTPUT_TDC_CFG 0xccd0
457 #define OUTPUT_TDC_0 0xcd00
459 #define OUTPUT_TDC_1 0xcd08
461 #define OUTPUT_TDC_2 0xcd10
463 #define OUTPUT_TDC_3 0xcd18
465 #define INPUT_TDC 0xcd20
467 #define SCRATCH 0xcf50
469 #define EEPROM 0xcf68
475 /* Bit definitions for the MAJ_REL register */
476 #define MAJOR_SHIFT (1)
477 #define MAJOR_MASK (0x7f)
478 #define PR_BUILD BIT(0)
480 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
481 #define GPIO0_LEVEL BIT(0)
482 #define GPIO1_LEVEL BIT(1)
483 #define GPIO2_LEVEL BIT(2)
484 #define GPIO3_LEVEL BIT(3)
485 #define GPIO4_LEVEL BIT(4)
486 #define GPIO5_LEVEL BIT(5)
487 #define GPIO6_LEVEL BIT(6)
488 #define GPIO7_LEVEL BIT(7)
490 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
491 #define GPIO8_LEVEL BIT(0)
492 #define GPIO9_LEVEL BIT(1)
493 #define GPIO10_LEVEL BIT(2)
494 #define GPIO11_LEVEL BIT(3)
495 #define GPIO12_LEVEL BIT(4)
496 #define GPIO13_LEVEL BIT(5)
497 #define GPIO14_LEVEL BIT(6)
498 #define GPIO15_LEVEL BIT(7)
500 /* Bit definitions for the GPIO0_TO_7_OUT register */
501 #define GPIO0_DRIVE_LEVEL BIT(0)
502 #define GPIO1_DRIVE_LEVEL BIT(1)
503 #define GPIO2_DRIVE_LEVEL BIT(2)
504 #define GPIO3_DRIVE_LEVEL BIT(3)
505 #define GPIO4_DRIVE_LEVEL BIT(4)
506 #define GPIO5_DRIVE_LEVEL BIT(5)
507 #define GPIO6_DRIVE_LEVEL BIT(6)
508 #define GPIO7_DRIVE_LEVEL BIT(7)
510 /* Bit definitions for the GPIO8_TO_15_OUT register */
511 #define GPIO8_DRIVE_LEVEL BIT(0)
512 #define GPIO9_DRIVE_LEVEL BIT(1)
513 #define GPIO10_DRIVE_LEVEL BIT(2)
514 #define GPIO11_DRIVE_LEVEL BIT(3)
515 #define GPIO12_DRIVE_LEVEL BIT(4)
516 #define GPIO13_DRIVE_LEVEL BIT(5)
517 #define GPIO14_DRIVE_LEVEL BIT(6)
518 #define GPIO15_DRIVE_LEVEL BIT(7)
520 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
521 #define TOD_SYNC_SOURCE_SHIFT (1)
522 #define TOD_SYNC_SOURCE_MASK (0x3)
523 #define TOD_SYNC_EN BIT(0)
525 /* Bit definitions for the DPLL_MODE register */
526 #define WRITE_TIMER_MODE BIT(6)
527 #define PLL_MODE_SHIFT (3)
528 #define PLL_MODE_MASK (0x7)
529 #define STATE_MODE_SHIFT (0)
530 #define STATE_MODE_MASK (0x7)
532 /* Bit definitions for the GPIO_CFG_GBL register */
533 #define SUPPLY_MODE_SHIFT (0)
534 #define SUPPLY_MODE_MASK (0x3)
536 /* Bit definitions for the GPIO_DCO_INC_DEC register */
537 #define INCDEC_DPLL_INDEX_SHIFT (0)
538 #define INCDEC_DPLL_INDEX_MASK (0x7)
540 /* Bit definitions for the GPIO_OUT_CTRL_0 register */
541 #define CTRL_OUT_0 BIT(0)
542 #define CTRL_OUT_1 BIT(1)
543 #define CTRL_OUT_2 BIT(2)
544 #define CTRL_OUT_3 BIT(3)
545 #define CTRL_OUT_4 BIT(4)
546 #define CTRL_OUT_5 BIT(5)
547 #define CTRL_OUT_6 BIT(6)
548 #define CTRL_OUT_7 BIT(7)
550 /* Bit definitions for the GPIO_OUT_CTRL_1 register */
551 #define CTRL_OUT_8 BIT(0)
552 #define CTRL_OUT_9 BIT(1)
553 #define CTRL_OUT_10 BIT(2)
554 #define CTRL_OUT_11 BIT(3)
555 #define CTRL_OUT_12 BIT(4)
556 #define CTRL_OUT_13 BIT(5)
557 #define CTRL_OUT_14 BIT(6)
558 #define CTRL_OUT_15 BIT(7)
560 /* Bit definitions for the GPIO_TOD_TRIG register */
561 #define TOD_TRIG_0 BIT(0)
562 #define TOD_TRIG_1 BIT(1)
563 #define TOD_TRIG_2 BIT(2)
564 #define TOD_TRIG_3 BIT(3)
566 /* Bit definitions for the GPIO_DPLL_INDICATOR register */
567 #define IND_DPLL_INDEX_SHIFT (0)
568 #define IND_DPLL_INDEX_MASK (0x7)
570 /* Bit definitions for the GPIO_LOS_INDICATOR register */
571 #define REFMON_INDEX_SHIFT (0)
572 #define REFMON_INDEX_MASK (0xf)
573 /* Active level of LOS indicator, 0=low 1=high */
574 #define ACTIVE_LEVEL BIT(4)
576 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
577 #define DSQ_INP_0 BIT(0)
578 #define DSQ_INP_1 BIT(1)
579 #define DSQ_INP_2 BIT(2)
580 #define DSQ_INP_3 BIT(3)
581 #define DSQ_INP_4 BIT(4)
582 #define DSQ_INP_5 BIT(5)
583 #define DSQ_INP_6 BIT(6)
584 #define DSQ_INP_7 BIT(7)
586 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
587 #define DSQ_INP_8 BIT(0)
588 #define DSQ_INP_9 BIT(1)
589 #define DSQ_INP_10 BIT(2)
590 #define DSQ_INP_11 BIT(3)
591 #define DSQ_INP_12 BIT(4)
592 #define DSQ_INP_13 BIT(5)
593 #define DSQ_INP_14 BIT(6)
594 #define DSQ_INP_15 BIT(7)
596 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
597 #define DSQ_DPLL_0 BIT(0)
598 #define DSQ_DPLL_1 BIT(1)
599 #define DSQ_DPLL_2 BIT(2)
600 #define DSQ_DPLL_3 BIT(3)
601 #define DSQ_DPLL_4 BIT(4)
602 #define DSQ_DPLL_5 BIT(5)
603 #define DSQ_DPLL_6 BIT(6)
604 #define DSQ_DPLL_7 BIT(7)
606 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
607 #define DSQ_DPLL_SYS BIT(0)
608 #define GPIO_DSQ_LEVEL BIT(1)
610 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
611 #define DPLL_TOD_SHIFT (0)
612 #define DPLL_TOD_MASK (0x3)
613 #define TOD_READ_SECONDARY BIT(2)
614 #define GPIO_ASSERT_LEVEL BIT(3)
616 /* Bit definitions for the GPIO_CTRL register */
617 #define GPIO_FUNCTION_EN BIT(0)
618 #define GPIO_CMOS_OD_MODE BIT(1)
619 #define GPIO_CONTROL_DIR BIT(2)
620 #define GPIO_PU_PD_MODE BIT(3)
621 #define GPIO_FUNCTION_SHIFT (4)
622 #define GPIO_FUNCTION_MASK (0xf)
624 /* Bit definitions for the OUT_CTRL_1 register */
625 #define OUT_SYNC_DISABLE BIT(7)
626 #define SQUELCH_VALUE BIT(6)
627 #define SQUELCH_DISABLE BIT(5)
628 #define PAD_VDDO_SHIFT (2)
629 #define PAD_VDDO_MASK (0x7)
630 #define PAD_CMOSDRV_SHIFT (0)
631 #define PAD_CMOSDRV_MASK (0x3)
633 /* Bit definitions for the TOD_CFG register */
634 #define TOD_EVEN_PPS_MODE BIT(2)
635 #define TOD_OUT_SYNC_ENABLE BIT(1)
636 #define TOD_ENABLE BIT(0)
638 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
639 #define WR_PWM_DECODER_INDEX_SHIFT (4)
640 #define WR_PWM_DECODER_INDEX_MASK (0xf)
641 #define WR_REF_INDEX_SHIFT (0)
642 #define WR_REF_INDEX_MASK (0xf)
644 /* Bit definitions for the TOD_WRITE_CMD register */
645 #define TOD_WRITE_SELECTION_SHIFT (0)
646 #define TOD_WRITE_SELECTION_MASK (0xf)
648 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
649 #define RD_PWM_DECODER_INDEX_SHIFT (4)
650 #define RD_PWM_DECODER_INDEX_MASK (0xf)
651 #define RD_REF_INDEX_SHIFT (0)
652 #define RD_REF_INDEX_MASK (0xf)
654 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
655 #define TOD_READ_TRIGGER_MODE BIT(4)
656 #define TOD_READ_TRIGGER_SHIFT (0)
657 #define TOD_READ_TRIGGER_MASK (0xf)