drivers/platform/x86/intel_pmc_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Core SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   9  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/acpi.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/dmi.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/uaccess.h>
  25
  26 #include <asm/cpu_device_id.h>
  27 #include <asm/intel-family.h>
  28 #include <asm/msr.h>
  29 #include <asm/tsc.h>
  30
  31 #include "intel_pmc_core.h"
  32
  33 static struct pmc_dev pmc;
  34
  35 /* PKGC MSRs are common across Intel Core SoCs */
  36 static const struct pmc_bit_map msr_map[] = {
  37         {"Package C2",                  MSR_PKG_C2_RESIDENCY},
  38         {"Package C3",                  MSR_PKG_C3_RESIDENCY},
  39         {"Package C6",                  MSR_PKG_C6_RESIDENCY},
  40         {"Package C7",                  MSR_PKG_C7_RESIDENCY},
  41         {"Package C8",                  MSR_PKG_C8_RESIDENCY},
  42         {"Package C9",                  MSR_PKG_C9_RESIDENCY},
  43         {"Package C10",                 MSR_PKG_C10_RESIDENCY},
  44         {}
  45 };
  46
  47 static const struct pmc_bit_map spt_pll_map[] = {
  48         {"MIPI PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE0},
  49         {"GEN2 USB2PCIE2 PLL",          SPT_PMC_BIT_MPHY_CMN_LANE1},
  50         {"DMIPCIE3 PLL",                SPT_PMC_BIT_MPHY_CMN_LANE2},
  51         {"SATA PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE3},
  52         {}
  53 };
  54
  55 static const struct pmc_bit_map spt_mphy_map[] = {
  56         {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
  57         {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
  58         {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
  59         {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
  60         {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
  61         {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
  62         {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
  63         {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
  64         {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
  65         {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
  66         {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
  67         {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
  68         {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
  69         {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
  70         {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
  71         {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
  72         {}
  73 };
  74
  75 static const struct pmc_bit_map spt_pfear_map[] = {
  76         {"PMC",                         SPT_PMC_BIT_PMC},
  77         {"OPI-DMI",                     SPT_PMC_BIT_OPI},
  78         {"SPI / eSPI",                  SPT_PMC_BIT_SPI},
  79         {"XHCI",                        SPT_PMC_BIT_XHCI},
  80         {"SPA",                         SPT_PMC_BIT_SPA},
  81         {"SPB",                         SPT_PMC_BIT_SPB},
  82         {"SPC",                         SPT_PMC_BIT_SPC},
  83         {"GBE",                         SPT_PMC_BIT_GBE},
  84         {"SATA",                        SPT_PMC_BIT_SATA},
  85         {"HDA-PGD0",                    SPT_PMC_BIT_HDA_PGD0},
  86         {"HDA-PGD1",                    SPT_PMC_BIT_HDA_PGD1},
  87         {"HDA-PGD2",                    SPT_PMC_BIT_HDA_PGD2},
  88         {"HDA-PGD3",                    SPT_PMC_BIT_HDA_PGD3},
  89         {"RSVD",                        SPT_PMC_BIT_RSVD_0B},
  90         {"LPSS",                        SPT_PMC_BIT_LPSS},
  91         {"LPC",                         SPT_PMC_BIT_LPC},
  92         {"SMB",                         SPT_PMC_BIT_SMB},
  93         {"ISH",                         SPT_PMC_BIT_ISH},
  94         {"P2SB",                        SPT_PMC_BIT_P2SB},
  95         {"DFX",                         SPT_PMC_BIT_DFX},
  96         {"SCC",                         SPT_PMC_BIT_SCC},
  97         {"RSVD",                        SPT_PMC_BIT_RSVD_0C},
  98         {"FUSE",                        SPT_PMC_BIT_FUSE},
  99         {"CAMERA",                      SPT_PMC_BIT_CAMREA},
 100         {"RSVD",                        SPT_PMC_BIT_RSVD_0D},
 101         {"USB3-OTG",                    SPT_PMC_BIT_USB3_OTG},
 102         {"EXI",                         SPT_PMC_BIT_EXI},
 103         {"CSE",                         SPT_PMC_BIT_CSE},
 104         {"CSME_KVM",                    SPT_PMC_BIT_CSME_KVM},
 105         {"CSME_PMT",                    SPT_PMC_BIT_CSME_PMT},
 106         {"CSME_CLINK",                  SPT_PMC_BIT_CSME_CLINK},
 107         {"CSME_PTIO",                   SPT_PMC_BIT_CSME_PTIO},
 108         {"CSME_USBR",                   SPT_PMC_BIT_CSME_USBR},
 109         {"CSME_SUSRAM",                 SPT_PMC_BIT_CSME_SUSRAM},
 110         {"CSME_SMT",                    SPT_PMC_BIT_CSME_SMT},
 111         {"RSVD",                        SPT_PMC_BIT_RSVD_1A},
 112         {"CSME_SMS2",                   SPT_PMC_BIT_CSME_SMS2},
 113         {"CSME_SMS1",                   SPT_PMC_BIT_CSME_SMS1},
 114         {"CSME_RTC",                    SPT_PMC_BIT_CSME_RTC},
 115         {"CSME_PSF",                    SPT_PMC_BIT_CSME_PSF},
 116         {}
 117 };
 118
 119 static const struct pmc_bit_map *ext_spt_pfear_map[] = {
 120         spt_pfear_map,
 121         NULL
 122 };
 123
 124 static const struct pmc_bit_map spt_ltr_show_map[] = {
 125         {"SOUTHPORT_A",         SPT_PMC_LTR_SPA},
 126         {"SOUTHPORT_B",         SPT_PMC_LTR_SPB},
 127         {"SATA",                SPT_PMC_LTR_SATA},
 128         {"GIGABIT_ETHERNET",    SPT_PMC_LTR_GBE},
 129         {"XHCI",                SPT_PMC_LTR_XHCI},
 130         {"Reserved",            SPT_PMC_LTR_RESERVED},
 131         {"ME",                  SPT_PMC_LTR_ME},
 132         /* EVA is Enterprise Value Add, doesn't really exist on PCH */
 133         {"EVA",                 SPT_PMC_LTR_EVA},
 134         {"SOUTHPORT_C",         SPT_PMC_LTR_SPC},
 135         {"HD_AUDIO",            SPT_PMC_LTR_AZ},
 136         {"LPSS",                SPT_PMC_LTR_LPSS},
 137         {"SOUTHPORT_D",         SPT_PMC_LTR_SPD},
 138         {"SOUTHPORT_E",         SPT_PMC_LTR_SPE},
 139         {"CAMERA",              SPT_PMC_LTR_CAM},
 140         {"ESPI",                SPT_PMC_LTR_ESPI},
 141         {"SCC",                 SPT_PMC_LTR_SCC},
 142         {"ISH",                 SPT_PMC_LTR_ISH},
 143         /* Below two cannot be used for LTR_IGNORE */
 144         {"CURRENT_PLATFORM",    SPT_PMC_LTR_CUR_PLT},
 145         {"AGGREGATED_SYSTEM",   SPT_PMC_LTR_CUR_ASLT},
 146         {}
 147 };
 148
 149 static const struct pmc_reg_map spt_reg_map = {
 150         .pfear_sts = ext_spt_pfear_map,
 151         .mphy_sts = spt_mphy_map,
 152         .pll_sts = spt_pll_map,
 153         .ltr_show_sts = spt_ltr_show_map,
 154         .msr_sts = msr_map,
 155         .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
 156         .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
 157         .regmap_length = SPT_PMC_MMIO_REG_LEN,
 158         .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
 159         .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
 160         .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
 161         .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
 162         .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
 163         .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
 164 };
 165
 166 /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
 167 static const struct pmc_bit_map cnp_pfear_map[] = {
 168         /* Reserved for Cannon Lake but valid for Comet Lake */
 169         {"PMC",                 BIT(0)},
 170         {"OPI-DMI",             BIT(1)},
 171         {"SPI/eSPI",            BIT(2)},
 172         {"XHCI",                BIT(3)},
 173         {"SPA",                 BIT(4)},
 174         {"SPB",                 BIT(5)},
 175         {"SPC",                 BIT(6)},
 176         {"GBE",                 BIT(7)},
 177
 178         {"SATA",                BIT(0)},
 179         {"HDA_PGD0",            BIT(1)},
 180         {"HDA_PGD1",            BIT(2)},
 181         {"HDA_PGD2",            BIT(3)},
 182         {"HDA_PGD3",            BIT(4)},
 183         {"SPD",                 BIT(5)},
 184         {"LPSS",                BIT(6)},
 185         {"LPC",                 BIT(7)},
 186
 187         {"SMB",                 BIT(0)},
 188         {"ISH",                 BIT(1)},
 189         {"P2SB",                BIT(2)},
 190         {"NPK_VNN",             BIT(3)},
 191         {"SDX",                 BIT(4)},
 192         {"SPE",                 BIT(5)},
 193         {"Fuse",                BIT(6)},
 194         /*
 195          * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
 196          * Tiger Lake, Elkhart Lake and Jasper Lake.
 197          */
 198         {"SBR8",                BIT(7)},
 199
 200         {"CSME_FSC",            BIT(0)},
 201         {"USB3_OTG",            BIT(1)},
 202         {"EXI",                 BIT(2)},
 203         {"CSE",                 BIT(3)},
 204         {"CSME_KVM",            BIT(4)},
 205         {"CSME_PMT",            BIT(5)},
 206         {"CSME_CLINK",          BIT(6)},
 207         {"CSME_PTIO",           BIT(7)},
 208
 209         {"CSME_USBR",           BIT(0)},
 210         {"CSME_SUSRAM",         BIT(1)},
 211         {"CSME_SMT1",           BIT(2)},
 212         {"CSME_SMT4",           BIT(3)},
 213         {"CSME_SMS2",           BIT(4)},
 214         {"CSME_SMS1",           BIT(5)},
 215         {"CSME_RTC",            BIT(6)},
 216         {"CSME_PSF",            BIT(7)},
 217
 218         {"SBR0",                BIT(0)},
 219         {"SBR1",                BIT(1)},
 220         {"SBR2",                BIT(2)},
 221         {"SBR3",                BIT(3)},
 222         {"SBR4",                BIT(4)},
 223         {"SBR5",                BIT(5)},
 224         {"CSME_PECI",           BIT(6)},
 225         {"PSF1",                BIT(7)},
 226
 227         {"PSF2",                BIT(0)},
 228         {"PSF3",                BIT(1)},
 229         {"PSF4",                BIT(2)},
 230         {"CNVI",                BIT(3)},
 231         {"UFS0",                BIT(4)},
 232         {"EMMC",                BIT(5)},
 233         {"SPF",                 BIT(6)},
 234         {"SBR6",                BIT(7)},
 235
 236         {"SBR7",                BIT(0)},
 237         {"NPK_AON",             BIT(1)},
 238         {"HDA_PGD4",            BIT(2)},
 239         {"HDA_PGD5",            BIT(3)},
 240         {"HDA_PGD6",            BIT(4)},
 241         /*
 242          * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
 243          * Tiger Lake, ELkhart Lake and Jasper Lake.
 244          */
 245         {"PSF6",                BIT(5)},
 246         {"PSF7",                BIT(6)},
 247         {"PSF8",                BIT(7)},
 248         {}
 249 };
 250
 251 static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
 252         cnp_pfear_map,
 253         NULL
 254 };
 255
 256 static const struct pmc_bit_map icl_pfear_map[] = {
 257         /* Ice Lake generation onwards only */
 258         {"RES_65",              BIT(0)},
 259         {"RES_66",              BIT(1)},
 260         {"RES_67",              BIT(2)},
 261         {"TAM",                 BIT(3)},
 262         {"GBETSN",              BIT(4)},
 263         {"TBTLSX",              BIT(5)},
 264         {"RES_71",              BIT(6)},
 265         {"RES_72",              BIT(7)},
 266         {}
 267 };
 268
 269 static const struct pmc_bit_map *ext_icl_pfear_map[] = {
 270         cnp_pfear_map,
 271         icl_pfear_map,
 272         NULL
 273 };
 274
 275 static const struct pmc_bit_map tgl_pfear_map[] = {
 276         /* Tiger Lake, Elkhart Lake and Jasper Lake generation onwards only */
 277         {"PSF9",                BIT(0)},
 278         {"RES_66",              BIT(1)},
 279         {"RES_67",              BIT(2)},
 280         {"RES_68",              BIT(3)},
 281         {"RES_69",              BIT(4)},
 282         {"RES_70",              BIT(5)},
 283         {"TBTLSX",              BIT(6)},
 284         {}
 285 };
 286
 287 static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
 288         cnp_pfear_map,
 289         tgl_pfear_map,
 290         NULL
 291 };
 292
 293 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
 294         {"AUDIO_D3",            BIT(0)},
 295         {"OTG_D3",              BIT(1)},
 296         {"XHCI_D3",             BIT(2)},
 297         {"LPIO_D3",             BIT(3)},
 298         {"SDX_D3",              BIT(4)},
 299         {"SATA_D3",             BIT(5)},
 300         {"UFS0_D3",             BIT(6)},
 301         {"UFS1_D3",             BIT(7)},
 302         {"EMMC_D3",             BIT(8)},
 303         {}
 304 };
 305
 306 static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
 307         {"SDIO_PLL_OFF",        BIT(0)},
 308         {"USB2_PLL_OFF",        BIT(1)},
 309         {"AUDIO_PLL_OFF",       BIT(2)},
 310         {"OC_PLL_OFF",          BIT(3)},
 311         {"MAIN_PLL_OFF",        BIT(4)},
 312         {"XOSC_OFF",            BIT(5)},
 313         {"LPC_CLKS_GATED",      BIT(6)},
 314         {"PCIE_CLKREQS_IDLE",   BIT(7)},
 315         {"AUDIO_ROSC_OFF",      BIT(8)},
 316         {"HPET_XOSC_CLK_REQ",   BIT(9)},
 317         {"PMC_ROSC_SLOW_CLK",   BIT(10)},
 318         {"AON2_ROSC_GATED",     BIT(11)},
 319         {"CLKACKS_DEASSERTED",  BIT(12)},
 320         {}
 321 };
 322
 323 static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
 324         {"MPHY_CORE_GATED",     BIT(0)},
 325         {"CSME_GATED",          BIT(1)},
 326         {"USB2_SUS_GATED",      BIT(2)},
 327         {"DYN_FLEX_IO_IDLE",    BIT(3)},
 328         {"GBE_NO_LINK",         BIT(4)},
 329         {"THERM_SEN_DISABLED",  BIT(5)},
 330         {"PCIE_LOW_POWER",      BIT(6)},
 331         {"ISH_VNNAON_REQ_ACT",  BIT(7)},
 332         {"ISH_VNN_REQ_ACT",     BIT(8)},
 333         {"CNV_VNNAON_REQ_ACT",  BIT(9)},
 334         {"CNV_VNN_REQ_ACT",     BIT(10)},
 335         {"NPK_VNNON_REQ_ACT",   BIT(11)},
 336         {"PMSYNC_STATE_IDLE",   BIT(12)},
 337         {"ALST_GT_THRES",       BIT(13)},
 338         {"PMC_ARC_PG_READY",    BIT(14)},
 339         {}
 340 };
 341
 342 static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
 343         cnp_slps0_dbg0_map,
 344         cnp_slps0_dbg1_map,
 345         cnp_slps0_dbg2_map,
 346         NULL
 347 };
 348
 349 static const struct pmc_bit_map cnp_ltr_show_map[] = {
 350         {"SOUTHPORT_A",         CNP_PMC_LTR_SPA},
 351         {"SOUTHPORT_B",         CNP_PMC_LTR_SPB},
 352         {"SATA",                CNP_PMC_LTR_SATA},
 353         {"GIGABIT_ETHERNET",    CNP_PMC_LTR_GBE},
 354         {"XHCI",                CNP_PMC_LTR_XHCI},
 355         {"Reserved",            CNP_PMC_LTR_RESERVED},
 356         {"ME",                  CNP_PMC_LTR_ME},
 357         /* EVA is Enterprise Value Add, doesn't really exist on PCH */
 358         {"EVA",                 CNP_PMC_LTR_EVA},
 359         {"SOUTHPORT_C",         CNP_PMC_LTR_SPC},
 360         {"HD_AUDIO",            CNP_PMC_LTR_AZ},
 361         {"CNV",                 CNP_PMC_LTR_CNV},
 362         {"LPSS",                CNP_PMC_LTR_LPSS},
 363         {"SOUTHPORT_D",         CNP_PMC_LTR_SPD},
 364         {"SOUTHPORT_E",         CNP_PMC_LTR_SPE},
 365         {"CAMERA",              CNP_PMC_LTR_CAM},
 366         {"ESPI",                CNP_PMC_LTR_ESPI},
 367         {"SCC",                 CNP_PMC_LTR_SCC},
 368         {"ISH",                 CNP_PMC_LTR_ISH},
 369         {"UFSX2",               CNP_PMC_LTR_UFSX2},
 370         {"EMMC",                CNP_PMC_LTR_EMMC},
 371         /* Reserved for Cannon Lake but valid for Ice Lake */
 372         {"WIGIG",               ICL_PMC_LTR_WIGIG},
 373         /* Below two cannot be used for LTR_IGNORE */
 374         {"CURRENT_PLATFORM",    CNP_PMC_LTR_CUR_PLT},
 375         {"AGGREGATED_SYSTEM",   CNP_PMC_LTR_CUR_ASLT},
 376         {}
 377 };
 378
 379 static const struct pmc_reg_map cnp_reg_map = {
 380         .pfear_sts = ext_cnp_pfear_map,
 381         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 382         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 383         .ltr_show_sts = cnp_ltr_show_map,
 384         .msr_sts = msr_map,
 385         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 386         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 387         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 388         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 389         .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 390         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 391         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 392         .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
 393 };
 394
 395 static const struct pmc_reg_map icl_reg_map = {
 396         .pfear_sts = ext_icl_pfear_map,
 397         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 398         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 399         .ltr_show_sts = cnp_ltr_show_map,
 400         .msr_sts = msr_map,
 401         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 402         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 403         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 404         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 405         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
 406         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 407         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 408         .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
 409 };
 410
 411 static const struct pmc_bit_map tgl_lpm0_map[] = {
 412         {"USB2PLL_OFF_STS",                     BIT(18)},
 413         {"PCIe/USB3.1_Gen2PLL_OFF_STS",         BIT(19)},
 414         {"PCIe_Gen3PLL_OFF_STS",                BIT(20)},
 415         {"OPIOPLL_OFF_STS",                     BIT(21)},
 416         {"OCPLL_OFF_STS",                       BIT(22)},
 417         {"AudioPLL_OFF_STS",                    BIT(23)},
 418         {"MIPIPLL_OFF_STS",                     BIT(24)},
 419         {"Fast_XTAL_Osc_OFF_STS",               BIT(25)},
 420         {"AC_Ring_Osc_OFF_STS",                 BIT(26)},
 421         {"MC_Ring_Osc_OFF_STS",                 BIT(27)},
 422         {"SATAPLL_OFF_STS",                     BIT(29)},
 423         {"XTAL_USB2PLL_OFF_STS",                BIT(31)},
 424         {}
 425 };
 426
 427 static const struct pmc_bit_map tgl_lpm1_map[] = {
 428         {"SPI_PG_STS",                          BIT(2)},
 429         {"xHCI_PG_STS",                         BIT(3)},
 430         {"PCIe_Ctrller_A_PG_STS",               BIT(4)},
 431         {"PCIe_Ctrller_B_PG_STS",               BIT(5)},
 432         {"PCIe_Ctrller_C_PG_STS",               BIT(6)},
 433         {"GBE_PG_STS",                          BIT(7)},
 434         {"SATA_PG_STS",                         BIT(8)},
 435         {"HDA0_PG_STS",                         BIT(9)},
 436         {"HDA1_PG_STS",                         BIT(10)},
 437         {"HDA2_PG_STS",                         BIT(11)},
 438         {"HDA3_PG_STS",                         BIT(12)},
 439         {"PCIe_Ctrller_D_PG_STS",               BIT(13)},
 440         {"ISIO_PG_STS",                         BIT(14)},
 441         {"SMB_PG_STS",                          BIT(16)},
 442         {"ISH_PG_STS",                          BIT(17)},
 443         {"ITH_PG_STS",                          BIT(19)},
 444         {"SDX_PG_STS",                          BIT(20)},
 445         {"xDCI_PG_STS",                         BIT(25)},
 446         {"DCI_PG_STS",                          BIT(26)},
 447         {"CSME0_PG_STS",                        BIT(27)},
 448         {"CSME_KVM_PG_STS",                     BIT(28)},
 449         {"CSME1_PG_STS",                        BIT(29)},
 450         {"CSME_CLINK_PG_STS",                   BIT(30)},
 451         {"CSME2_PG_STS",                        BIT(31)},
 452         {}
 453 };
 454
 455 static const struct pmc_bit_map tgl_lpm2_map[] = {
 456         {"ADSP_D3_STS",                         BIT(0)},
 457         {"SATA_D3_STS",                         BIT(1)},
 458         {"xHCI0_D3_STS",                        BIT(2)},
 459         {"xDCI1_D3_STS",                        BIT(5)},
 460         {"SDX_D3_STS",                          BIT(6)},
 461         {"EMMC_D3_STS",                         BIT(7)},
 462         {"IS_D3_STS",                           BIT(8)},
 463         {"THC0_D3_STS",                         BIT(9)},
 464         {"THC1_D3_STS",                         BIT(10)},
 465         {"GBE_D3_STS",                          BIT(11)},
 466         {"GBE_TSN_D3_STS",                      BIT(12)},
 467         {}
 468 };
 469
 470 static const struct pmc_bit_map tgl_lpm3_map[] = {
 471         {"GPIO_COM0_VNN_REQ_STS",               BIT(1)},
 472         {"GPIO_COM1_VNN_REQ_STS",               BIT(2)},
 473         {"GPIO_COM2_VNN_REQ_STS",               BIT(3)},
 474         {"GPIO_COM3_VNN_REQ_STS",               BIT(4)},
 475         {"GPIO_COM4_VNN_REQ_STS",               BIT(5)},
 476         {"GPIO_COM5_VNN_REQ_STS",               BIT(6)},
 477         {"Audio_VNN_REQ_STS",                   BIT(7)},
 478         {"ISH_VNN_REQ_STS",                     BIT(8)},
 479         {"CNVI_VNN_REQ_STS",                    BIT(9)},
 480         {"eSPI_VNN_REQ_STS",                    BIT(10)},
 481         {"Display_VNN_REQ_STS",                 BIT(11)},
 482         {"DTS_VNN_REQ_STS",                     BIT(12)},
 483         {"SMBUS_VNN_REQ_STS",                   BIT(14)},
 484         {"CSME_VNN_REQ_STS",                    BIT(15)},
 485         {"SMLINK0_VNN_REQ_STS",                 BIT(16)},
 486         {"SMLINK1_VNN_REQ_STS",                 BIT(17)},
 487         {"CLINK_VNN_REQ_STS",                   BIT(20)},
 488         {"DCI_VNN_REQ_STS",                     BIT(21)},
 489         {"ITH_VNN_REQ_STS",                     BIT(22)},
 490         {"CSME_VNN_REQ_STS",                    BIT(24)},
 491         {"GBE_VNN_REQ_STS",                     BIT(25)},
 492         {}
 493 };
 494
 495 static const struct pmc_bit_map tgl_lpm4_map[] = {
 496         {"CPU_C10_REQ_STS_0",                   BIT(0)},
 497         {"PCIe_LPM_En_REQ_STS_3",               BIT(3)},
 498         {"ITH_REQ_STS_5",                       BIT(5)},
 499         {"CNVI_REQ_STS_6",                      BIT(6)},
 500         {"ISH_REQ_STS_7",                       BIT(7)},
 501         {"USB2_SUS_PG_Sys_REQ_STS_10",          BIT(10)},
 502         {"PCIe_Clk_REQ_STS_12",                 BIT(12)},
 503         {"MPHY_Core_DL_REQ_STS_16",             BIT(16)},
 504         {"Break-even_En_REQ_STS_17",            BIT(17)},
 505         {"Auto-demo_En_REQ_STS_18",             BIT(18)},
 506         {"MPHY_SUS_REQ_STS_22",                 BIT(22)},
 507         {"xDCI_attached_REQ_STS_24",            BIT(24)},
 508         {}
 509 };
 510
 511 static const struct pmc_bit_map tgl_lpm5_map[] = {
 512         {"LSX_Wake0_En_STS",                    BIT(0)},
 513         {"LSX_Wake0_Pol_STS",                   BIT(1)},
 514         {"LSX_Wake1_En_STS",                    BIT(2)},
 515         {"LSX_Wake1_Pol_STS",                   BIT(3)},
 516         {"LSX_Wake2_En_STS",                    BIT(4)},
 517         {"LSX_Wake2_Pol_STS",                   BIT(5)},
 518         {"LSX_Wake3_En_STS",                    BIT(6)},
 519         {"LSX_Wake3_Pol_STS",                   BIT(7)},
 520         {"LSX_Wake4_En_STS",                    BIT(8)},
 521         {"LSX_Wake4_Pol_STS",                   BIT(9)},
 522         {"LSX_Wake5_En_STS",                    BIT(10)},
 523         {"LSX_Wake5_Pol_STS",                   BIT(11)},
 524         {"LSX_Wake6_En_STS",                    BIT(12)},
 525         {"LSX_Wake6_Pol_STS",                   BIT(13)},
 526         {"LSX_Wake7_En_STS",                    BIT(14)},
 527         {"LSX_Wake7_Pol_STS",                   BIT(15)},
 528         {"Intel_Se_IO_Wake0_En_STS",            BIT(16)},
 529         {"Intel_Se_IO_Wake0_Pol_STS",           BIT(17)},
 530         {"Intel_Se_IO_Wake1_En_STS",            BIT(18)},
 531         {"Intel_Se_IO_Wake1_Pol_STS",           BIT(19)},
 532         {"Int_Timer_SS_Wake0_En_STS",           BIT(20)},
 533         {"Int_Timer_SS_Wake0_Pol_STS",          BIT(21)},
 534         {"Int_Timer_SS_Wake1_En_STS",           BIT(22)},
 535         {"Int_Timer_SS_Wake1_Pol_STS",          BIT(23)},
 536         {"Int_Timer_SS_Wake2_En_STS",           BIT(24)},
 537         {"Int_Timer_SS_Wake2_Pol_STS",          BIT(25)},
 538         {"Int_Timer_SS_Wake3_En_STS",           BIT(26)},
 539         {"Int_Timer_SS_Wake3_Pol_STS",          BIT(27)},
 540         {"Int_Timer_SS_Wake4_En_STS",           BIT(28)},
 541         {"Int_Timer_SS_Wake4_Pol_STS",          BIT(29)},
 542         {"Int_Timer_SS_Wake5_En_STS",           BIT(30)},
 543         {"Int_Timer_SS_Wake5_Pol_STS",          BIT(31)},
 544         {}
 545 };
 546
 547 static const struct pmc_bit_map *tgl_lpm_maps[] = {
 548         tgl_lpm0_map,
 549         tgl_lpm1_map,
 550         tgl_lpm2_map,
 551         tgl_lpm3_map,
 552         tgl_lpm4_map,
 553         tgl_lpm5_map,
 554         NULL
 555 };
 556
 557 static const struct pmc_reg_map tgl_reg_map = {
 558         .pfear_sts = ext_tgl_pfear_map,
 559         .ltr_show_sts = cnp_ltr_show_map,
 560         .msr_sts = msr_map,
 561         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 562         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 563         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 564         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 565         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
 566         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 567         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 568         .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
 569         .lpm_en_offset = TGL_LPM_EN_OFFSET,
 570         .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
 571         .lpm_sts = tgl_lpm_maps,
 572         .lpm_status_offset = TGL_LPM_STATUS_OFFSET,
 573 };
 574
 575 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 576 {
 577         return readl(pmcdev->regbase + reg_offset);
 578 }
 579
 580 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
 581                                       u32 val)
 582 {
 583         writel(val, pmcdev->regbase + reg_offset);
 584 }
 585
 586 static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
 587 {
 588         return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
 589 }
 590
 591 static int pmc_core_dev_state_get(void *data, u64 *val)
 592 {
 593         struct pmc_dev *pmcdev = data;
 594         const struct pmc_reg_map *map = pmcdev->map;
 595         u32 value;
 596
 597         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 598         *val = pmc_core_adjust_slp_s0_step(value);
 599
 600         return 0;
 601 }
 602
 603 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 604
 605 static int pmc_core_check_read_lock_bit(void)
 606 {
 607         struct pmc_dev *pmcdev = &pmc;
 608         u32 value;
 609
 610         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 611         return value & BIT(pmcdev->map->pm_read_disable_bit);
 612 }
 613
 614 #if IS_ENABLED(CONFIG_DEBUG_FS)
 615 static bool slps0_dbg_latch;
 616
 617 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 618 {
 619         return readb(pmcdev->regbase + offset);
 620 }
 621
 622 static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
 623                                  u8 pf_reg, const struct pmc_bit_map **pf_map)
 624 {
 625         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 626                    ip, pf_map[idx][index].name,
 627                    pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
 628 }
 629
 630 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
 631 {
 632         struct pmc_dev *pmcdev = s->private;
 633         const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
 634         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 635         int index, iter, idx, ip = 0;
 636
 637         iter = pmcdev->map->ppfear0_offset;
 638
 639         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 640              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 641                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 642
 643         for (idx = 0; maps[idx]; idx++) {
 644                 for (index = 0; maps[idx][index].name &&
 645                      index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
 646                         pmc_core_display_map(s, index, idx, ip,
 647                                              pf_regs[index / 8], maps);
 648         }
 649
 650         return 0;
 651 }
 652 DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
 653
 654 /* This function should return link status, 0 means ready */
 655 static int pmc_core_mtpmc_link_status(void)
 656 {
 657         struct pmc_dev *pmcdev = &pmc;
 658         u32 value;
 659
 660         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 661         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 662 }
 663
 664 static int pmc_core_send_msg(u32 *addr_xram)
 665 {
 666         struct pmc_dev *pmcdev = &pmc;
 667         u32 dest;
 668         int timeout;
 669
 670         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 671                 if (pmc_core_mtpmc_link_status() == 0)
 672                         break;
 673                 msleep(5);
 674         }
 675
 676         if (timeout <= 0 && pmc_core_mtpmc_link_status())
 677                 return -EBUSY;
 678
 679         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 680         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 681         return 0;
 682 }
 683
 684 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
 685 {
 686         struct pmc_dev *pmcdev = s->private;
 687         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 688         u32 mphy_core_reg_low, mphy_core_reg_high;
 689         u32 val_low, val_high;
 690         int index, err = 0;
 691
 692         if (pmcdev->pmc_xram_read_bit) {
 693                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 694                 return 0;
 695         }
 696
 697         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 698         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 699
 700         mutex_lock(&pmcdev->lock);
 701
 702         if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
 703                 err = -EBUSY;
 704                 goto out_unlock;
 705         }
 706
 707         msleep(10);
 708         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 709
 710         if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
 711                 err = -EBUSY;
 712                 goto out_unlock;
 713         }
 714
 715         msleep(10);
 716         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 717
 718         for (index = 0; map[index].name && index < 8; index++) {
 719                 seq_printf(s, "%-32s\tState: %s\n",
 720                            map[index].name,
 721                            map[index].bit_mask & val_low ? "Not power gated" :
 722                            "Power gated");
 723         }
 724
 725         for (index = 8; map[index].name; index++) {
 726                 seq_printf(s, "%-32s\tState: %s\n",
 727                            map[index].name,
 728                            map[index].bit_mask & val_high ? "Not power gated" :
 729                            "Power gated");
 730         }
 731
 732 out_unlock:
 733         mutex_unlock(&pmcdev->lock);
 734         return err;
 735 }
 736 DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
 737
 738 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 739 {
 740         struct pmc_dev *pmcdev = s->private;
 741         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 742         u32 mphy_common_reg, val;
 743         int index, err = 0;
 744
 745         if (pmcdev->pmc_xram_read_bit) {
 746                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 747                 return 0;
 748         }
 749
 750         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 751         mutex_lock(&pmcdev->lock);
 752
 753         if (pmc_core_send_msg(&mphy_common_reg) != 0) {
 754                 err = -EBUSY;
 755                 goto out_unlock;
 756         }
 757
 758         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 759         msleep(10);
 760         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 761
 762         for (index = 0; map[index].name ; index++) {
 763                 seq_printf(s, "%-32s\tState: %s\n",
 764                            map[index].name,
 765                            map[index].bit_mask & val ? "Active" : "Idle");
 766         }
 767
 768 out_unlock:
 769         mutex_unlock(&pmcdev->lock);
 770         return err;
 771 }
 772 DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
 773
 774 static ssize_t pmc_core_ltr_ignore_write(struct file *file,
 775                                          const char __user *userbuf,
 776                                          size_t count, loff_t *ppos)
 777 {
 778         struct pmc_dev *pmcdev = &pmc;
 779         const struct pmc_reg_map *map = pmcdev->map;
 780         u32 val, buf_size, fd;
 781         int err;
 782
 783         buf_size = count < 64 ? count : 64;
 784
 785         err = kstrtou32_from_user(userbuf, buf_size, 10, &val);
 786         if (err)
 787                 return err;
 788
 789         mutex_lock(&pmcdev->lock);
 790
 791         if (val > map->ltr_ignore_max) {
 792                 err = -EINVAL;
 793                 goto out_unlock;
 794         }
 795
 796         fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
 797         fd |= (1U << val);
 798         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
 799
 800 out_unlock:
 801         mutex_unlock(&pmcdev->lock);
 802         return err == 0 ? count : err;
 803 }
 804
 805 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 806 {
 807         return 0;
 808 }
 809
 810 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
 811 {
 812         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
 813 }
 814
 815 static const struct file_operations pmc_core_ltr_ignore_ops = {
 816         .open           = pmc_core_ltr_ignore_open,
 817         .read           = seq_read,
 818         .write          = pmc_core_ltr_ignore_write,
 819         .llseek         = seq_lseek,
 820         .release        = single_release,
 821 };
 822
 823 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
 824 {
 825         const struct pmc_reg_map *map = pmcdev->map;
 826         u32 fd;
 827
 828         mutex_lock(&pmcdev->lock);
 829
 830         if (!reset && !slps0_dbg_latch)
 831                 goto out_unlock;
 832
 833         fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
 834         if (reset)
 835                 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
 836         else
 837                 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
 838         pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
 839
 840         slps0_dbg_latch = 0;
 841
 842 out_unlock:
 843         mutex_unlock(&pmcdev->lock);
 844 }
 845
 846 static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
 847                                    struct seq_file *s)
 848 {
 849         const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
 850         const struct pmc_bit_map *map;
 851         int offset = pmcdev->map->slps0_dbg_offset;
 852         u32 data;
 853
 854         while (*maps) {
 855                 map = *maps;
 856                 data = pmc_core_reg_read(pmcdev, offset);
 857                 offset += 4;
 858                 while (map->name) {
 859                         if (dev)
 860                                 dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
 861                                         map->name,
 862                                         data & map->bit_mask ? "Yes" : "No");
 863                         if (s)
 864                                 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
 865                                            map->name,
 866                                            data & map->bit_mask ? "Yes" : "No");
 867                         ++map;
 868                 }
 869                 ++maps;
 870         }
 871 }
 872
 873 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
 874 {
 875         struct pmc_dev *pmcdev = s->private;
 876
 877         pmc_core_slps0_dbg_latch(pmcdev, false);
 878         pmc_core_slps0_display(pmcdev, NULL, s);
 879         pmc_core_slps0_dbg_latch(pmcdev, true);
 880
 881         return 0;
 882 }
 883 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
 884
 885 static u32 convert_ltr_scale(u32 val)
 886 {
 887         /*
 888          * As per PCIE specification supporting document
 889          * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
 890          * Tolerance Reporting data payload is encoded in a
 891          * 3 bit scale and 10 bit value fields. Values are
 892          * multiplied by the indicated scale to yield an absolute time
 893          * value, expressible in a range from 1 nanosecond to
 894          * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
 895          *
 896          * scale encoding is as follows:
 897          *
 898          * ----------------------------------------------
 899          * |scale factor        |       Multiplier (ns) |
 900          * ----------------------------------------------
 901          * |    0               |       1               |
 902          * |    1               |       32              |
 903          * |    2               |       1024            |
 904          * |    3               |       32768           |
 905          * |    4               |       1048576         |
 906          * |    5               |       33554432        |
 907          * |    6               |       Invalid         |
 908          * |    7               |       Invalid         |
 909          * ----------------------------------------------
 910          */
 911         if (val > 5) {
 912                 pr_warn("Invalid LTR scale factor.\n");
 913                 return 0;
 914         }
 915
 916         return 1U << (5 * val);
 917 }
 918
 919 static int pmc_core_ltr_show(struct seq_file *s, void *unused)
 920 {
 921         struct pmc_dev *pmcdev = s->private;
 922         const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
 923         u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
 924         u32 ltr_raw_data, scale, val;
 925         u16 snoop_ltr, nonsnoop_ltr;
 926         int index;
 927
 928         for (index = 0; map[index].name ; index++) {
 929                 decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
 930                 ltr_raw_data = pmc_core_reg_read(pmcdev,
 931                                                  map[index].bit_mask);
 932                 snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
 933                 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
 934
 935                 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
 936                         scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
 937                         val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
 938                         decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
 939                 }
 940
 941                 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
 942                         scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
 943                         val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
 944                         decoded_snoop_ltr = val * convert_ltr_scale(scale);
 945                 }
 946
 947                 seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
 948                            map[index].name, ltr_raw_data,
 949                            decoded_non_snoop_ltr,
 950                            decoded_snoop_ltr);
 951         }
 952         return 0;
 953 }
 954 DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
 955
 956 static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
 957 {
 958         struct pmc_dev *pmcdev = s->private;
 959         u32 offset = pmcdev->map->lpm_residency_offset;
 960         u32 lpm_en;
 961         int index;
 962
 963         lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
 964         seq_printf(s, "status substate residency\n");
 965         for (index = 0; lpm_modes[index]; index++) {
 966                 seq_printf(s, "%7s %7s %-15u\n",
 967                            BIT(index) & lpm_en ? "Enabled" : " ",
 968                            lpm_modes[index], pmc_core_reg_read(pmcdev, offset));
 969                 offset += 4;
 970         }
 971
 972         return 0;
 973 }
 974 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
 975
 976 static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
 977                                  struct seq_file *s, u32 offset,
 978                                  const char *str,
 979                                  const struct pmc_bit_map **maps)
 980 {
 981         u32 lpm_regs[ARRAY_SIZE(tgl_lpm_maps)-1];
 982         int index, idx, len = 32, bit_mask;
 983
 984         for (index = 0; tgl_lpm_maps[index]; index++) {
 985                 lpm_regs[index] = pmc_core_reg_read(pmcdev, offset);
 986                 offset += 4;
 987         }
 988
 989         for (idx = 0; maps[idx]; idx++) {
 990                 if (dev)
 991                         dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
 992                                 lpm_regs[idx]);
 993                 if (s)
 994                         seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
 995                                    lpm_regs[idx]);
 996                 for (index = 0; maps[idx][index].name && index < len; index++) {
 997                         bit_mask = maps[idx][index].bit_mask;
 998                         if (dev)
 999                                 dev_dbg(dev, "%-30s %-30d\n",
1000                                         maps[idx][index].name,
1001                                         lpm_regs[idx] & bit_mask ? 1 : 0);
1002                         if (s)
1003                                 seq_printf(s, "%-30s %-30d\n",
1004                                            maps[idx][index].name,
1005                                            lpm_regs[idx] & bit_mask ? 1 : 0);
1006                 }
1007         }
1008 }
1009
1010 static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused)
1011 {
1012         struct pmc_dev *pmcdev = s->private;
1013         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1014         u32 offset = pmcdev->map->lpm_status_offset;
1015
1016         pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps);
1017
1018         return 0;
1019 }
1020 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
1021
1022 static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
1023 {
1024         struct pmc_dev *pmcdev = s->private;
1025         const struct pmc_bit_map *map = pmcdev->map->msr_sts;
1026         u64 pcstate_count;
1027         int index;
1028
1029         for (index = 0; map[index].name ; index++) {
1030                 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
1031                         continue;
1032
1033                 pcstate_count *= 1000;
1034                 do_div(pcstate_count, tsc_khz);
1035                 seq_printf(s, "%-8s : %llu\n", map[index].name,
1036                            pcstate_count);
1037         }
1038
1039         return 0;
1040 }
1041 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
1042
1043 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
1044 {
1045         debugfs_remove_recursive(pmcdev->dbgfs_dir);
1046 }
1047
1048 static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
1049 {
1050         struct dentry *dir;
1051
1052         dir = debugfs_create_dir("pmc_core", NULL);
1053         pmcdev->dbgfs_dir = dir;
1054
1055         debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
1056                             &pmc_core_dev_state);
1057
1058         if (pmcdev->map->pfear_sts)
1059                 debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
1060                                     pmcdev, &pmc_core_ppfear_fops);
1061
1062         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
1063                             &pmc_core_ltr_ignore_ops);
1064
1065         debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
1066
1067         debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
1068                             &pmc_core_pkgc_fops);
1069
1070         if (pmcdev->map->pll_sts)
1071                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
1072                                     &pmc_core_pll_fops);
1073
1074         if (pmcdev->map->mphy_sts)
1075                 debugfs_create_file("mphy_core_lanes_power_gating_status",
1076                                     0444, dir, pmcdev,
1077                                     &pmc_core_mphy_pg_fops);
1078
1079         if (pmcdev->map->slps0_dbg_maps) {
1080                 debugfs_create_file("slp_s0_debug_status", 0444,
1081                                     dir, pmcdev,
1082                                     &pmc_core_slps0_dbg_fops);
1083
1084                 debugfs_create_bool("slp_s0_dbg_latch", 0644,
1085                                     dir, &slps0_dbg_latch);
1086         }
1087
1088         if (pmcdev->map->lpm_en_offset) {
1089                 debugfs_create_file("substate_residencies", 0444,
1090                                     pmcdev->dbgfs_dir, pmcdev,
1091                                     &pmc_core_substate_res_fops);
1092         }
1093
1094         if (pmcdev->map->lpm_status_offset) {
1095                 debugfs_create_file("substate_status_registers", 0444,
1096                                     pmcdev->dbgfs_dir, pmcdev,
1097                                     &pmc_core_substate_sts_regs_fops);
1098         }
1099 }
1100 #else
1101 static inline void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
1102 {
1103 }
1104
1105 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
1106 {
1107 }
1108 #endif /* CONFIG_DEBUG_FS */
1109
1110 static const struct x86_cpu_id intel_pmc_core_ids[] = {
1111         INTEL_CPU_FAM6(SKYLAKE_L, spt_reg_map),
1112         INTEL_CPU_FAM6(SKYLAKE, spt_reg_map),
1113         INTEL_CPU_FAM6(KABYLAKE_L, spt_reg_map),
1114         INTEL_CPU_FAM6(KABYLAKE, spt_reg_map),
1115         INTEL_CPU_FAM6(CANNONLAKE_L, cnp_reg_map),
1116         INTEL_CPU_FAM6(ICELAKE_L, icl_reg_map),
1117         INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
1118         INTEL_CPU_FAM6(COMETLAKE, cnp_reg_map),
1119         INTEL_CPU_FAM6(COMETLAKE_L, cnp_reg_map),
1120         INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
1121         INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
1122         INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map),
1123         INTEL_CPU_FAM6(ATOM_TREMONT_L, tgl_reg_map),
1124         {}
1125 };
1126
1127 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
1128
1129 static const struct pci_device_id pmc_pci_ids[] = {
1130         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
1131         { }
1132 };
1133
1134 /*
1135  * This quirk can be used on those platforms where
1136  * the platform BIOS enforces 24Mhz crystal to shutdown
1137  * before PMC can assert SLP_S0#.
1138  */
1139 static int quirk_xtal_ignore(const struct dmi_system_id *id)
1140 {
1141         struct pmc_dev *pmcdev = &pmc;
1142         u32 value;
1143
1144         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
1145         /* 24MHz Crystal Shutdown Qualification Disable */
1146         value |= SPT_PMC_VRIC1_XTALSDQDIS;
1147         /* Low Voltage Mode Enable */
1148         value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
1149         pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
1150         return 0;
1151 }
1152
1153 static const struct dmi_system_id pmc_core_dmi_table[]  = {
1154         {
1155         .callback = quirk_xtal_ignore,
1156         .ident = "HP Elite x2 1013 G3",
1157         .matches = {
1158                 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1159                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
1160                 },
1161         },
1162         {}
1163 };
1164
1165 static int pmc_core_probe(struct platform_device *pdev)
1166 {
1167         static bool device_initialized;
1168         struct pmc_dev *pmcdev = &pmc;
1169         const struct x86_cpu_id *cpu_id;
1170         u64 slp_s0_addr;
1171
1172         if (device_initialized)
1173                 return -ENODEV;
1174
1175         cpu_id = x86_match_cpu(intel_pmc_core_ids);
1176         if (!cpu_id)
1177                 return -ENODEV;
1178
1179         pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
1180
1181         /*
1182          * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
1183          * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
1184          * in this case.
1185          */
1186         if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
1187                 pmcdev->map = &cnp_reg_map;
1188
1189         if (lpit_read_residency_count_address(&slp_s0_addr)) {
1190                 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
1191
1192                 if (page_is_ram(PHYS_PFN(pmcdev->base_addr)))
1193                         return -ENODEV;
1194         } else {
1195                 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
1196         }
1197
1198         pmcdev->regbase = ioremap(pmcdev->base_addr,
1199                                   pmcdev->map->regmap_length);
1200         if (!pmcdev->regbase)
1201                 return -ENOMEM;
1202
1203         mutex_init(&pmcdev->lock);
1204         platform_set_drvdata(pdev, pmcdev);
1205         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
1206         dmi_check_system(pmc_core_dmi_table);
1207
1208         pmc_core_dbgfs_register(pmcdev);
1209
1210         device_initialized = true;
1211         dev_info(&pdev->dev, " initialized\n");
1212
1213         return 0;
1214 }
1215
1216 static int pmc_core_remove(struct platform_device *pdev)
1217 {
1218         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1219
1220         pmc_core_dbgfs_unregister(pmcdev);
1221         platform_set_drvdata(pdev, NULL);
1222         mutex_destroy(&pmcdev->lock);
1223         iounmap(pmcdev->regbase);
1224         return 0;
1225 }
1226
1227 #ifdef CONFIG_PM_SLEEP
1228
1229 static bool warn_on_s0ix_failures;
1230 module_param(warn_on_s0ix_failures, bool, 0644);
1231 MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
1232
1233 static int pmc_core_suspend(struct device *dev)
1234 {
1235         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1236
1237         pmcdev->check_counters = false;
1238
1239         /* No warnings on S0ix failures */
1240         if (!warn_on_s0ix_failures)
1241                 return 0;
1242
1243         /* Check if the syspend will actually use S0ix */
1244         if (pm_suspend_via_firmware())
1245                 return 0;
1246
1247         /* Save PC10 residency for checking later */
1248         if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
1249                 return -EIO;
1250
1251         /* Save S0ix residency for checking later */
1252         if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
1253                 return -EIO;
1254
1255         pmcdev->check_counters = true;
1256         return 0;
1257 }
1258
1259 static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
1260 {
1261         u64 pc10_counter;
1262
1263         if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
1264                 return false;
1265
1266         if (pc10_counter == pmcdev->pc10_counter)
1267                 return true;
1268
1269         return false;
1270 }
1271
1272 static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
1273 {
1274         u64 s0ix_counter;
1275
1276         if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
1277                 return false;
1278
1279         if (s0ix_counter == pmcdev->s0ix_counter)
1280                 return true;
1281
1282         return false;
1283 }
1284
1285 static int pmc_core_resume(struct device *dev)
1286 {
1287         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1288         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1289         int offset = pmcdev->map->lpm_status_offset;
1290
1291         if (!pmcdev->check_counters)
1292                 return 0;
1293
1294         if (!pmc_core_is_s0ix_failed(pmcdev))
1295                 return 0;
1296
1297         if (pmc_core_is_pc10_failed(pmcdev)) {
1298                 /* S0ix failed because of PC10 entry failure */
1299                 dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
1300                          pmcdev->pc10_counter);
1301                 return 0;
1302         }
1303
1304         /* The real interesting case - S0ix failed - lets ask PMC why. */
1305         dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
1306                  pmcdev->s0ix_counter);
1307         if (pmcdev->map->slps0_dbg_maps)
1308                 pmc_core_slps0_display(pmcdev, dev, NULL);
1309         if (pmcdev->map->lpm_sts)
1310                 pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
1311
1312         return 0;
1313 }
1314
1315 #endif
1316
1317 static const struct dev_pm_ops pmc_core_pm_ops = {
1318         SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
1319 };
1320
1321 static const struct acpi_device_id pmc_core_acpi_ids[] = {
1322         {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
1323         { }
1324 };
1325 MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
1326
1327 static struct platform_driver pmc_core_driver = {
1328         .driver = {
1329                 .name = "intel_pmc_core",
1330                 .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
1331                 .pm = &pmc_core_pm_ops,
1332         },
1333         .probe = pmc_core_probe,
1334         .remove = pmc_core_remove,
1335 };
1336
1337 module_platform_driver(pmc_core_driver);
1338
1339 MODULE_LICENSE("GPL v2");
1340 MODULE_DESCRIPTION("Intel PMC Core Driver");