drivers/platform/x86/intel/pmc/tgl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file contains platform specific structure definitions
   4  * and init function used by Tiger Lake PCH.
   5  *
   6  * Copyright (c) 2022, Intel Corporation.
   7  * All Rights Reserved.
   8  *
   9  */
  10
  11 #include "core.h"
  12
  13 #define ACPI_S0IX_DSM_UUID              "57a6512e-3979-4e9d-9708-ff13b2508972"
  14 #define ACPI_GET_LOW_MODE_REGISTERS     1
  15
  16 const struct pmc_bit_map tgl_pfear_map[] = {
  17         {"PSF9",                BIT(0)},
  18         {"RES_66",              BIT(1)},
  19         {"RES_67",              BIT(2)},
  20         {"RES_68",              BIT(3)},
  21         {"RES_69",              BIT(4)},
  22         {"RES_70",              BIT(5)},
  23         {"TBTLSX",              BIT(6)},
  24         {}
  25 };
  26
  27 const struct pmc_bit_map *ext_tgl_pfear_map[] = {
  28         /*
  29          * Check intel_pmc_core_ids[] users of tgl_reg_map for
  30          * a list of core SoCs using this.
  31          */
  32         cnp_pfear_map,
  33         tgl_pfear_map,
  34         NULL
  35 };
  36
  37 const struct pmc_bit_map tgl_clocksource_status_map[] = {
  38         {"USB2PLL_OFF_STS",                     BIT(18)},
  39         {"PCIe/USB3.1_Gen2PLL_OFF_STS",         BIT(19)},
  40         {"PCIe_Gen3PLL_OFF_STS",                BIT(20)},
  41         {"OPIOPLL_OFF_STS",                     BIT(21)},
  42         {"OCPLL_OFF_STS",                       BIT(22)},
  43         {"MainPLL_OFF_STS",                     BIT(23)},
  44         {"MIPIPLL_OFF_STS",                     BIT(24)},
  45         {"Fast_XTAL_Osc_OFF_STS",               BIT(25)},
  46         {"AC_Ring_Osc_OFF_STS",                 BIT(26)},
  47         {"MC_Ring_Osc_OFF_STS",                 BIT(27)},
  48         {"SATAPLL_OFF_STS",                     BIT(29)},
  49         {"XTAL_USB2PLL_OFF_STS",                BIT(31)},
  50         {}
  51 };
  52
  53 const struct pmc_bit_map tgl_power_gating_status_map[] = {
  54         {"CSME_PG_STS",                         BIT(0)},
  55         {"SATA_PG_STS",                         BIT(1)},
  56         {"xHCI_PG_STS",                         BIT(2)},
  57         {"UFSX2_PG_STS",                        BIT(3)},
  58         {"OTG_PG_STS",                          BIT(5)},
  59         {"SPA_PG_STS",                          BIT(6)},
  60         {"SPB_PG_STS",                          BIT(7)},
  61         {"SPC_PG_STS",                          BIT(8)},
  62         {"SPD_PG_STS",                          BIT(9)},
  63         {"SPE_PG_STS",                          BIT(10)},
  64         {"SPF_PG_STS",                          BIT(11)},
  65         {"LSX_PG_STS",                          BIT(13)},
  66         {"P2SB_PG_STS",                         BIT(14)},
  67         {"PSF_PG_STS",                          BIT(15)},
  68         {"SBR_PG_STS",                          BIT(16)},
  69         {"OPIDMI_PG_STS",                       BIT(17)},
  70         {"THC0_PG_STS",                         BIT(18)},
  71         {"THC1_PG_STS",                         BIT(19)},
  72         {"GBETSN_PG_STS",                       BIT(20)},
  73         {"GBE_PG_STS",                          BIT(21)},
  74         {"LPSS_PG_STS",                         BIT(22)},
  75         {"MMP_UFSX2_PG_STS",                    BIT(23)},
  76         {"MMP_UFSX2B_PG_STS",                   BIT(24)},
  77         {"FIA_PG_STS",                          BIT(25)},
  78         {}
  79 };
  80
  81 const struct pmc_bit_map tgl_d3_status_map[] = {
  82         {"ADSP_D3_STS",                         BIT(0)},
  83         {"SATA_D3_STS",                         BIT(1)},
  84         {"xHCI0_D3_STS",                        BIT(2)},
  85         {"xDCI1_D3_STS",                        BIT(5)},
  86         {"SDX_D3_STS",                          BIT(6)},
  87         {"EMMC_D3_STS",                         BIT(7)},
  88         {"IS_D3_STS",                           BIT(8)},
  89         {"THC0_D3_STS",                         BIT(9)},
  90         {"THC1_D3_STS",                         BIT(10)},
  91         {"GBE_D3_STS",                          BIT(11)},
  92         {"GBE_TSN_D3_STS",                      BIT(12)},
  93         {}
  94 };
  95
  96 const struct pmc_bit_map tgl_vnn_req_status_map[] = {
  97         {"GPIO_COM0_VNN_REQ_STS",               BIT(1)},
  98         {"GPIO_COM1_VNN_REQ_STS",               BIT(2)},
  99         {"GPIO_COM2_VNN_REQ_STS",               BIT(3)},
 100         {"GPIO_COM3_VNN_REQ_STS",               BIT(4)},
 101         {"GPIO_COM4_VNN_REQ_STS",               BIT(5)},
 102         {"GPIO_COM5_VNN_REQ_STS",               BIT(6)},
 103         {"Audio_VNN_REQ_STS",                   BIT(7)},
 104         {"ISH_VNN_REQ_STS",                     BIT(8)},
 105         {"CNVI_VNN_REQ_STS",                    BIT(9)},
 106         {"eSPI_VNN_REQ_STS",                    BIT(10)},
 107         {"Display_VNN_REQ_STS",                 BIT(11)},
 108         {"DTS_VNN_REQ_STS",                     BIT(12)},
 109         {"SMBUS_VNN_REQ_STS",                   BIT(14)},
 110         {"CSME_VNN_REQ_STS",                    BIT(15)},
 111         {"SMLINK0_VNN_REQ_STS",                 BIT(16)},
 112         {"SMLINK1_VNN_REQ_STS",                 BIT(17)},
 113         {"CLINK_VNN_REQ_STS",                   BIT(20)},
 114         {"DCI_VNN_REQ_STS",                     BIT(21)},
 115         {"ITH_VNN_REQ_STS",                     BIT(22)},
 116         {"CSME_VNN_REQ_STS",                    BIT(24)},
 117         {"GBE_VNN_REQ_STS",                     BIT(25)},
 118         {}
 119 };
 120
 121 const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
 122         {"CPU_C10_REQ_STS_0",                   BIT(0)},
 123         {"PCIe_LPM_En_REQ_STS_3",               BIT(3)},
 124         {"ITH_REQ_STS_5",                       BIT(5)},
 125         {"CNVI_REQ_STS_6",                      BIT(6)},
 126         {"ISH_REQ_STS_7",                       BIT(7)},
 127         {"USB2_SUS_PG_Sys_REQ_STS_10",          BIT(10)},
 128         {"PCIe_Clk_REQ_STS_12",                 BIT(12)},
 129         {"MPHY_Core_DL_REQ_STS_16",             BIT(16)},
 130         {"Break-even_En_REQ_STS_17",            BIT(17)},
 131         {"Auto-demo_En_REQ_STS_18",             BIT(18)},
 132         {"MPHY_SUS_REQ_STS_22",                 BIT(22)},
 133         {"xDCI_attached_REQ_STS_24",            BIT(24)},
 134         {}
 135 };
 136
 137 const struct pmc_bit_map tgl_signal_status_map[] = {
 138         {"LSX_Wake0_En_STS",                    BIT(0)},
 139         {"LSX_Wake0_Pol_STS",                   BIT(1)},
 140         {"LSX_Wake1_En_STS",                    BIT(2)},
 141         {"LSX_Wake1_Pol_STS",                   BIT(3)},
 142         {"LSX_Wake2_En_STS",                    BIT(4)},
 143         {"LSX_Wake2_Pol_STS",                   BIT(5)},
 144         {"LSX_Wake3_En_STS",                    BIT(6)},
 145         {"LSX_Wake3_Pol_STS",                   BIT(7)},
 146         {"LSX_Wake4_En_STS",                    BIT(8)},
 147         {"LSX_Wake4_Pol_STS",                   BIT(9)},
 148         {"LSX_Wake5_En_STS",                    BIT(10)},
 149         {"LSX_Wake5_Pol_STS",                   BIT(11)},
 150         {"LSX_Wake6_En_STS",                    BIT(12)},
 151         {"LSX_Wake6_Pol_STS",                   BIT(13)},
 152         {"LSX_Wake7_En_STS",                    BIT(14)},
 153         {"LSX_Wake7_Pol_STS",                   BIT(15)},
 154         {"Intel_Se_IO_Wake0_En_STS",            BIT(16)},
 155         {"Intel_Se_IO_Wake0_Pol_STS",           BIT(17)},
 156         {"Intel_Se_IO_Wake1_En_STS",            BIT(18)},
 157         {"Intel_Se_IO_Wake1_Pol_STS",           BIT(19)},
 158         {"Int_Timer_SS_Wake0_En_STS",           BIT(20)},
 159         {"Int_Timer_SS_Wake0_Pol_STS",          BIT(21)},
 160         {"Int_Timer_SS_Wake1_En_STS",           BIT(22)},
 161         {"Int_Timer_SS_Wake1_Pol_STS",          BIT(23)},
 162         {"Int_Timer_SS_Wake2_En_STS",           BIT(24)},
 163         {"Int_Timer_SS_Wake2_Pol_STS",          BIT(25)},
 164         {"Int_Timer_SS_Wake3_En_STS",           BIT(26)},
 165         {"Int_Timer_SS_Wake3_Pol_STS",          BIT(27)},
 166         {"Int_Timer_SS_Wake4_En_STS",           BIT(28)},
 167         {"Int_Timer_SS_Wake4_Pol_STS",          BIT(29)},
 168         {"Int_Timer_SS_Wake5_En_STS",           BIT(30)},
 169         {"Int_Timer_SS_Wake5_Pol_STS",          BIT(31)},
 170         {}
 171 };
 172
 173 const struct pmc_bit_map *tgl_lpm_maps[] = {
 174         tgl_clocksource_status_map,
 175         tgl_power_gating_status_map,
 176         tgl_d3_status_map,
 177         tgl_vnn_req_status_map,
 178         tgl_vnn_misc_status_map,
 179         tgl_signal_status_map,
 180         NULL
 181 };
 182
 183 const struct pmc_reg_map tgl_reg_map = {
 184         .pfear_sts = ext_tgl_pfear_map,
 185         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 186         .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
 187         .ltr_show_sts = cnp_ltr_show_map,
 188         .msr_sts = msr_map,
 189         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 190         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 191         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 192         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
 193         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 194         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 195         .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
 196         .lpm_num_maps = TGL_LPM_NUM_MAPS,
 197         .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
 198         .lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
 199         .lpm_en_offset = TGL_LPM_EN_OFFSET,
 200         .lpm_priority_offset = TGL_LPM_PRI_OFFSET,
 201         .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
 202         .lpm_sts = tgl_lpm_maps,
 203         .lpm_status_offset = TGL_LPM_STATUS_OFFSET,
 204         .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
 205         .etr3_offset = ETR3_OFFSET,
 206 };
 207
 208 void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
 209 {
 210         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
 211         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 212         const int num_maps = pmc->map->lpm_num_maps;
 213         u32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;
 214         union acpi_object *out_obj;
 215         struct acpi_device *adev;
 216         guid_t s0ix_dsm_guid;
 217         u32 *lpm_req_regs, *addr;
 218
 219         adev = ACPI_COMPANION(&pdev->dev);
 220         if (!adev)
 221                 return;
 222
 223         guid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);
 224
 225         out_obj = acpi_evaluate_dsm_typed(adev->handle, &s0ix_dsm_guid, 0,
 226                                           ACPI_GET_LOW_MODE_REGISTERS, NULL, ACPI_TYPE_BUFFER);
 227         if (out_obj) {
 228                 u32 size = out_obj->buffer.length;
 229
 230                 if (size != lpm_size) {
 231                         acpi_handle_debug(adev->handle,
 232                                 "_DSM returned unexpected buffer size, have %u, expect %u\n",
 233                                 size, lpm_size);
 234                         goto free_acpi_obj;
 235                 }
 236         } else {
 237                 acpi_handle_debug(adev->handle,
 238                                   "_DSM function 0 evaluation failed\n");
 239                 goto free_acpi_obj;
 240         }
 241
 242         addr = (u32 *)out_obj->buffer.pointer;
 243
 244         lpm_req_regs = devm_kzalloc(&pdev->dev, lpm_size * sizeof(u32),
 245                                      GFP_KERNEL);
 246         if (!lpm_req_regs)
 247                 goto free_acpi_obj;
 248
 249         memcpy(lpm_req_regs, addr, lpm_size);
 250         pmc->lpm_req_regs = lpm_req_regs;
 251
 252 free_acpi_obj:
 253         ACPI_FREE(out_obj);
 254 }
 255
 256 int tgl_core_init(struct pmc_dev *pmcdev)
 257 {
 258         struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
 259         int ret;
 260
 261         pmc->map = &tgl_reg_map;
 262         ret = get_primary_reg_base(pmc);
 263         if (ret)
 264                 return ret;
 265
 266         pmc_core_get_tgl_lpm_reqs(pmcdev->pdev);
 267         /* Due to a hardware limitation, the GBE LTR blocks PC10
 268          * when a cable is attached. Tell the PMC to ignore it.
 269          */
 270         dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
 271         pmc_core_send_ltr_ignore(pmcdev, 3);
 272
 273         return 0;
 274 }