drivers/platform/x86/amd-pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/uaccess.h>
  26
  27 /* SMU communication registers */
  28 #define AMD_PMC_REGISTER_MESSAGE        0x538
  29 #define AMD_PMC_REGISTER_RESPONSE       0x980
  30 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  31
  32 /* Base address of SMU for mapping physical address to virtual address */
  33 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  34 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  35 #define AMD_PMC_MAPPING_SIZE            0x01000
  36 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  37 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  38 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  39 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  40 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  41
  42 /* SMU Response Codes */
  43 #define AMD_PMC_RESULT_OK                    0x01
  44 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  45 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  46 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  47 #define AMD_PMC_RESULT_FAILED                0xFF
  48
  49 /* List of supported CPU ids */
  50 #define AMD_CPU_ID_RV                   0x15D0
  51 #define AMD_CPU_ID_RN                   0x1630
  52 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  53 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  54
  55 #define PMC_MSG_DELAY_MIN_US            100
  56 #define RESPONSE_REGISTER_LOOP_MAX      200
  57
  58 enum amd_pmc_def {
  59         MSG_TEST = 0x01,
  60         MSG_OS_HINT_PCO,
  61         MSG_OS_HINT_RN,
  62 };
  63
  64 struct amd_pmc_dev {
  65         void __iomem *regbase;
  66         void __iomem *smu_base;
  67         u32 base_addr;
  68         u32 cpu_id;
  69         struct device *dev;
  70         struct mutex lock; /* generic mutex lock */
  71 #if IS_ENABLED(CONFIG_DEBUG_FS)
  72         struct dentry *dbgfs_dir;
  73 #endif /* CONFIG_DEBUG_FS */
  74 };
  75
  76 static struct amd_pmc_dev pmc;
  77
  78 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
  79 {
  80         return ioread32(dev->regbase + reg_offset);
  81 }
  82
  83 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
  84 {
  85         iowrite32(val, dev->regbase + reg_offset);
  86 }
  87
  88 #ifdef CONFIG_DEBUG_FS
  89 static int smu_fw_info_show(struct seq_file *s, void *unused)
  90 {
  91         return 0;
  92 }
  93 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
  94
  95 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
  96 {
  97         debugfs_remove_recursive(dev->dbgfs_dir);
  98 }
  99
 100 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 101 {
 102         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 103         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 104                             &smu_fw_info_fops);
 105 }
 106 #else
 107 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 108 {
 109 }
 110
 111 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 112 {
 113 }
 114 #endif /* CONFIG_DEBUG_FS */
 115
 116 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 117 {
 118         u32 value;
 119
 120         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
 121         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 122
 123         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 124         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 125
 126         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
 127         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 128 }
 129
 130 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
 131 {
 132         int rc;
 133         u8 msg;
 134         u32 val;
 135
 136         mutex_lock(&dev->lock);
 137         /* Wait until we get a valid response */
 138         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 139                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 140                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 141         if (rc) {
 142                 dev_err(dev->dev, "failed to talk to SMU\n");
 143                 return rc;
 144         }
 145
 146         /* Write zero to response register */
 147         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
 148
 149         /* Write argument into response register */
 150         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
 151
 152         /* Write message ID to message ID register */
 153         msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
 154         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
 155         /* Wait until we get a valid response */
 156         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 157                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 158                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 159         if (rc) {
 160                 dev_err(dev->dev, "SMU response timed out\n");
 161                 goto out_unlock;
 162         }
 163
 164         switch (val) {
 165         case AMD_PMC_RESULT_OK:
 166                 break;
 167         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 168                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 169                 rc = -EBUSY;
 170                 goto out_unlock;
 171         case AMD_PMC_RESULT_CMD_UNKNOWN:
 172                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 173                 rc = -EINVAL;
 174                 goto out_unlock;
 175         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 176         case AMD_PMC_RESULT_FAILED:
 177         default:
 178                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 179                 rc = -EIO;
 180                 goto out_unlock;
 181         }
 182
 183 out_unlock:
 184         mutex_unlock(&dev->lock);
 185         amd_pmc_dump_registers(dev);
 186         return rc;
 187 }
 188
 189 static int __maybe_unused amd_pmc_suspend(struct device *dev)
 190 {
 191         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 192         int rc;
 193
 194         rc = amd_pmc_send_cmd(pdev, 1);
 195         if (rc)
 196                 dev_err(pdev->dev, "suspend failed\n");
 197
 198         return 0;
 199 }
 200
 201 static int __maybe_unused amd_pmc_resume(struct device *dev)
 202 {
 203         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 204         int rc;
 205
 206         rc = amd_pmc_send_cmd(pdev, 0);
 207         if (rc)
 208                 dev_err(pdev->dev, "resume failed\n");
 209
 210         return 0;
 211 }
 212
 213 static const struct dev_pm_ops amd_pmc_pm_ops = {
 214         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(amd_pmc_suspend, amd_pmc_resume)
 215 };
 216
 217 static const struct pci_device_id pmc_pci_ids[] = {
 218         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 219         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 220         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 221         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 222         { }
 223 };
 224
 225 static int amd_pmc_probe(struct platform_device *pdev)
 226 {
 227         struct amd_pmc_dev *dev = &pmc;
 228         struct pci_dev *rdev;
 229         u32 base_addr_lo;
 230         u32 base_addr_hi;
 231         u64 base_addr;
 232         int err;
 233         u32 val;
 234
 235         dev->dev = &pdev->dev;
 236
 237         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 238         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 239                 pci_dev_put(rdev);
 240                 return -ENODEV;
 241         }
 242
 243         dev->cpu_id = rdev->device;
 244         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 245         if (err) {
 246                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 247                 pci_dev_put(rdev);
 248                 return pcibios_err_to_errno(err);
 249         }
 250
 251         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 252         if (err) {
 253                 pci_dev_put(rdev);
 254                 return pcibios_err_to_errno(err);
 255         }
 256
 257         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 258
 259         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 260         if (err) {
 261                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 262                 pci_dev_put(rdev);
 263                 return pcibios_err_to_errno(err);
 264         }
 265
 266         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 267         if (err) {
 268                 pci_dev_put(rdev);
 269                 return pcibios_err_to_errno(err);
 270         }
 271
 272         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 273         pci_dev_put(rdev);
 274         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 275
 276         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 277                                     AMD_PMC_MAPPING_SIZE);
 278         if (!dev->regbase)
 279                 return -ENOMEM;
 280
 281         mutex_init(&dev->lock);
 282         platform_set_drvdata(pdev, dev);
 283         amd_pmc_dbgfs_register(dev);
 284         return 0;
 285 }
 286
 287 static int amd_pmc_remove(struct platform_device *pdev)
 288 {
 289         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 290
 291         amd_pmc_dbgfs_unregister(dev);
 292         mutex_destroy(&dev->lock);
 293         return 0;
 294 }
 295
 296 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 297         {"AMDI0005", 0},
 298         {"AMD0004", 0},
 299         { }
 300 };
 301 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 302
 303 static struct platform_driver amd_pmc_driver = {
 304         .driver = {
 305                 .name = "amd_pmc",
 306                 .acpi_match_table = amd_pmc_acpi_ids,
 307                 .pm = &amd_pmc_pm_ops,
 308         },
 309         .probe = amd_pmc_probe,
 310         .remove = amd_pmc_remove,
 311 };
 312 module_platform_driver(amd_pmc_driver);
 313
 314 MODULE_LICENSE("GPL v2");
 315 MODULE_DESCRIPTION("AMD PMC Driver");