drivers/platform/x86/amd-pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/uaccess.h>
  26
  27 /* SMU communication registers */
  28 #define AMD_PMC_REGISTER_MESSAGE        0x538
  29 #define AMD_PMC_REGISTER_RESPONSE       0x980
  30 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  31
  32 /* Base address of SMU for mapping physical address to virtual address */
  33 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  34 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  35 #define AMD_PMC_MAPPING_SIZE            0x01000
  36 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  37 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  38 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  39 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  40 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  41
  42 /* SMU Response Codes */
  43 #define AMD_PMC_RESULT_OK                    0x01
  44 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  45 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  46 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  47 #define AMD_PMC_RESULT_FAILED                0xFF
  48
  49 /* SMU Message Definations */
  50 #define SMU_MSG_GETSMUVERSION           0x02
  51 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  52 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  53 #define SMU_MSG_LOG_START               0x06
  54 #define SMU_MSG_LOG_RESET               0x07
  55 #define SMU_MSG_LOG_DUMP_DATA           0x08
  56 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  57 /* List of supported CPU ids */
  58 #define AMD_CPU_ID_RV                   0x15D0
  59 #define AMD_CPU_ID_RN                   0x1630
  60 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  61 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  62
  63 #define PMC_MSG_DELAY_MIN_US            100
  64 #define RESPONSE_REGISTER_LOOP_MAX      200
  65
  66 #define SOC_SUBSYSTEM_IP_MAX    12
  67 #define DELAY_MIN_US            2000
  68 #define DELAY_MAX_US            3000
  69 enum amd_pmc_def {
  70         MSG_TEST = 0x01,
  71         MSG_OS_HINT_PCO,
  72         MSG_OS_HINT_RN,
  73 };
  74
  75 struct amd_pmc_bit_map {
  76         const char *name;
  77         u32 bit_mask;
  78 };
  79
  80 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
  81         {"DISPLAY",     BIT(0)},
  82         {"CPU",         BIT(1)},
  83         {"GFX",         BIT(2)},
  84         {"VDD",         BIT(3)},
  85         {"ACP",         BIT(4)},
  86         {"VCN",         BIT(5)},
  87         {"ISP",         BIT(6)},
  88         {"NBIO",        BIT(7)},
  89         {"DF",          BIT(8)},
  90         {"USB0",        BIT(9)},
  91         {"USB1",        BIT(10)},
  92         {"LAPIC",       BIT(11)},
  93         {}
  94 };
  95
  96 struct amd_pmc_dev {
  97         void __iomem *regbase;
  98         void __iomem *smu_virt_addr;
  99         u32 base_addr;
 100         u32 cpu_id;
 101         u32 active_ips;
 102         struct device *dev;
 103         struct mutex lock; /* generic mutex lock */
 104 #if IS_ENABLED(CONFIG_DEBUG_FS)
 105         struct dentry *dbgfs_dir;
 106 #endif /* CONFIG_DEBUG_FS */
 107 };
 108
 109 static struct amd_pmc_dev pmc;
 110 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret);
 111
 112 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 113 {
 114         return ioread32(dev->regbase + reg_offset);
 115 }
 116
 117 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 118 {
 119         iowrite32(val, dev->regbase + reg_offset);
 120 }
 121
 122 struct smu_metrics {
 123         u32 table_version;
 124         u32 hint_count;
 125         u32 s0i3_cyclecount;
 126         u32 timein_s0i2;
 127         u64 timeentering_s0i3_lastcapture;
 128         u64 timeentering_s0i3_totaltime;
 129         u64 timeto_resume_to_os_lastcapture;
 130         u64 timeto_resume_to_os_totaltime;
 131         u64 timein_s0i3_lastcapture;
 132         u64 timein_s0i3_totaltime;
 133         u64 timein_swdrips_lastcapture;
 134         u64 timein_swdrips_totaltime;
 135         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 136         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 137 } __packed;
 138
 139 #ifdef CONFIG_DEBUG_FS
 140 static int smu_fw_info_show(struct seq_file *s, void *unused)
 141 {
 142         struct amd_pmc_dev *dev = s->private;
 143         struct smu_metrics table;
 144         int idx;
 145
 146         if (dev->cpu_id == AMD_CPU_ID_PCO)
 147                 return -EINVAL;
 148
 149         memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
 150
 151         seq_puts(s, "\n=== SMU Statistics ===\n");
 152         seq_printf(s, "Table Version: %d\n", table.table_version);
 153         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 154         seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount);
 155         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 156         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 157
 158         seq_puts(s, "\n=== Active time (in us) ===\n");
 159         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 160                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 161                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 162                                    table.timecondition_notmet_lastcapture[idx]);
 163         }
 164
 165         return 0;
 166 }
 167 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 168
 169 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 170 {
 171         debugfs_remove_recursive(dev->dbgfs_dir);
 172 }
 173
 174 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 175 {
 176         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 177         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 178                             &smu_fw_info_fops);
 179 }
 180 #else
 181 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 182 {
 183 }
 184
 185 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 186 {
 187 }
 188 #endif /* CONFIG_DEBUG_FS */
 189
 190 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 191 {
 192         u32 phys_addr_low, phys_addr_hi;
 193         u64 smu_phys_addr;
 194
 195         if (dev->cpu_id == AMD_CPU_ID_PCO)
 196                 return -EINVAL;
 197
 198         /* Get Active devices list from SMU */
 199         amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 200
 201         /* Get dram address */
 202         amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 203         amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 204         smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 205
 206         dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
 207         if (!dev->smu_virt_addr)
 208                 return -ENOMEM;
 209
 210         /* Start the logging */
 211         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 212
 213         return 0;
 214 }
 215
 216 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 217 {
 218         u32 value;
 219
 220         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
 221         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 222
 223         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 224         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 225
 226         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
 227         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 228 }
 229
 230 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret)
 231 {
 232         int rc;
 233         u32 val;
 234
 235         mutex_lock(&dev->lock);
 236         /* Wait until we get a valid response */
 237         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 238                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 239                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 240         if (rc) {
 241                 dev_err(dev->dev, "failed to talk to SMU\n");
 242                 return rc;
 243         }
 244
 245         /* Write zero to response register */
 246         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
 247
 248         /* Write argument into response register */
 249         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
 250
 251         /* Write message ID to message ID register */
 252         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
 253
 254         /* Wait until we get a valid response */
 255         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 256                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 257                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 258         if (rc) {
 259                 dev_err(dev->dev, "SMU response timed out\n");
 260                 goto out_unlock;
 261         }
 262
 263         switch (val) {
 264         case AMD_PMC_RESULT_OK:
 265                 if (ret) {
 266                         /* PMFW may take longer time to return back the data */
 267                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 268                         *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 269                 }
 270                 break;
 271         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 272                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 273                 rc = -EBUSY;
 274                 goto out_unlock;
 275         case AMD_PMC_RESULT_CMD_UNKNOWN:
 276                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 277                 rc = -EINVAL;
 278                 goto out_unlock;
 279         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 280         case AMD_PMC_RESULT_FAILED:
 281         default:
 282                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 283                 rc = -EIO;
 284                 goto out_unlock;
 285         }
 286
 287 out_unlock:
 288         mutex_unlock(&dev->lock);
 289         amd_pmc_dump_registers(dev);
 290         return rc;
 291 }
 292
 293 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 294 {
 295         switch (dev->cpu_id) {
 296         case AMD_CPU_ID_PCO:
 297                 return MSG_OS_HINT_PCO;
 298         case AMD_CPU_ID_RN:
 299                 return MSG_OS_HINT_RN;
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int __maybe_unused amd_pmc_suspend(struct device *dev)
 305 {
 306         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 307         int rc;
 308         u8 msg;
 309
 310         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 311         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 312         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
 313
 314         msg = amd_pmc_get_os_hint(pdev);
 315         rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0);
 316         if (rc)
 317                 dev_err(pdev->dev, "suspend failed\n");
 318
 319         return 0;
 320 }
 321
 322 static int __maybe_unused amd_pmc_resume(struct device *dev)
 323 {
 324         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 325         int rc;
 326         u8 msg;
 327
 328         /* Let SMU know that we are looking for stats */
 329         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 330
 331         msg = amd_pmc_get_os_hint(pdev);
 332         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 333         if (rc)
 334                 dev_err(pdev->dev, "resume failed\n");
 335
 336         return 0;
 337 }
 338
 339 static const struct dev_pm_ops amd_pmc_pm_ops = {
 340         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(amd_pmc_suspend, amd_pmc_resume)
 341 };
 342
 343 static const struct pci_device_id pmc_pci_ids[] = {
 344         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 345         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 346         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 347         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 348         { }
 349 };
 350
 351 static int amd_pmc_probe(struct platform_device *pdev)
 352 {
 353         struct amd_pmc_dev *dev = &pmc;
 354         struct pci_dev *rdev;
 355         u32 base_addr_lo, base_addr_hi;
 356         u64 base_addr;
 357         int err;
 358         u32 val;
 359
 360         dev->dev = &pdev->dev;
 361
 362         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 363         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 364                 pci_dev_put(rdev);
 365                 return -ENODEV;
 366         }
 367
 368         dev->cpu_id = rdev->device;
 369         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 370         if (err) {
 371                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 372                 pci_dev_put(rdev);
 373                 return pcibios_err_to_errno(err);
 374         }
 375
 376         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 377         if (err) {
 378                 pci_dev_put(rdev);
 379                 return pcibios_err_to_errno(err);
 380         }
 381
 382         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 383
 384         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 385         if (err) {
 386                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 387                 pci_dev_put(rdev);
 388                 return pcibios_err_to_errno(err);
 389         }
 390
 391         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 392         if (err) {
 393                 pci_dev_put(rdev);
 394                 return pcibios_err_to_errno(err);
 395         }
 396
 397         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 398         pci_dev_put(rdev);
 399         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 400
 401         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 402                                     AMD_PMC_MAPPING_SIZE);
 403         if (!dev->regbase)
 404                 return -ENOMEM;
 405
 406         mutex_init(&dev->lock);
 407
 408         /* Use SMU to get the s0i3 debug stats */
 409         err = amd_pmc_setup_smu_logging(dev);
 410         if (err)
 411                 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
 412
 413         platform_set_drvdata(pdev, dev);
 414         amd_pmc_dbgfs_register(dev);
 415         return 0;
 416 }
 417
 418 static int amd_pmc_remove(struct platform_device *pdev)
 419 {
 420         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 421
 422         amd_pmc_dbgfs_unregister(dev);
 423         mutex_destroy(&dev->lock);
 424         return 0;
 425 }
 426
 427 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 428         {"AMDI0005", 0},
 429         {"AMD0004", 0},
 430         { }
 431 };
 432 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 433
 434 static struct platform_driver amd_pmc_driver = {
 435         .driver = {
 436                 .name = "amd_pmc",
 437                 .acpi_match_table = amd_pmc_acpi_ids,
 438                 .pm = &amd_pmc_pm_ops,
 439         },
 440         .probe = amd_pmc_probe,
 441         .remove = amd_pmc_remove,
 442 };
 443 module_platform_driver(amd_pmc_driver);
 444
 445 MODULE_LICENSE("GPL v2");
 446 MODULE_DESCRIPTION("AMD PMC Driver");