1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
4 // Copyright (C) 2012 Google, Inc
6 #include <linux/delay.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/mfd/cros_ec.h>
10 #include <linux/mfd/cros_ec_commands.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 #include <linux/spi/spi.h>
17 /* The header byte, which follows the preamble */
18 #define EC_MSG_HEADER 0xec
21 * Number of EC preamble bytes we read at a time. Since it takes
22 * about 400-500us for the EC to respond there is not a lot of
23 * point in tuning this. If the EC could respond faster then
24 * we could increase this so that might expect the preamble and
25 * message to occur in a single transaction. However, the maximum
26 * SPI transfer size is 256 bytes, so at 5MHz we need a response
27 * time of perhaps <320us (200 bytes / 1600 bits).
29 #define EC_MSG_PREAMBLE_COUNT 32
32 * Allow for a long time for the EC to respond. We support i2c
33 * tunneling and support fairly long messages for the tunnel (249
34 * bytes long at the moment). If we're talking to a 100 kHz device
35 * on the other end and need to transfer ~256 bytes, then we need:
36 * 10 us/bit * ~10 bits/byte * ~256 bytes = ~25ms
38 * We'll wait 8 times that to handle clock stretching and other
39 * paranoia. Note that some battery gas gauge ICs claim to have a
40 * clock stretch of 144ms in rare situations. That's incentive for
41 * not directly passing i2c through, but it's too late for that for
44 * It's pretty unlikely that we'll really see a 249 byte tunnel in
45 * anything other than testing. If this was more common we might
46 * consider having slow commands like this require a GET_STATUS
47 * wait loop. The 'flash write' command would be another candidate
48 * for this, clocking in at 2-3ms.
50 #define EC_MSG_DEADLINE_MS 200
53 * Time between raising the SPI chip select (for the end of a
54 * transaction) and dropping it again (for the next transaction).
55 * If we go too fast, the EC will miss the transaction. We know that we
56 * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
59 #define EC_SPI_RECOVERY_TIME_NS (200 * 1000)
62 * struct cros_ec_spi - information about a SPI-connected EC
64 * @spi: SPI device we are connected to
65 * @last_transfer_ns: time that we last finished a transfer.
66 * @start_of_msg_delay: used to set the delay_usecs on the spi_transfer that
67 * is sent when we want to turn on CS at the start of a transaction.
68 * @end_of_msg_delay: used to set the delay_usecs on the spi_transfer that
69 * is sent when we want to turn off CS at the end of a transaction.
72 struct spi_device *spi;
74 unsigned int start_of_msg_delay;
75 unsigned int end_of_msg_delay;
78 typedef int (*cros_ec_xfer_fn_t) (struct cros_ec_device *ec_dev,
79 struct cros_ec_command *ec_msg);
82 * struct cros_ec_xfer_work_params - params for our high priority workers
84 * @work: The work_struct needed to queue work
85 * @fn: The function to use to transfer
86 * @ec_dev: ChromeOS EC device
87 * @ec_msg: Message to transfer
88 * @ret: The return value of the function
91 struct cros_ec_xfer_work_params {
92 struct work_struct work;
94 struct cros_ec_device *ec_dev;
95 struct cros_ec_command *ec_msg;
99 static void debug_packet(struct device *dev, const char *name, u8 *ptr,
105 dev_dbg(dev, "%s: ", name);
106 for (i = 0; i < len; i++)
107 pr_cont(" %02x", ptr[i]);
113 static int terminate_request(struct cros_ec_device *ec_dev)
115 struct cros_ec_spi *ec_spi = ec_dev->priv;
116 struct spi_message msg;
117 struct spi_transfer trans;
121 * Turn off CS, possibly adding a delay to ensure the rising edge
122 * doesn't come too soon after the end of the data.
124 spi_message_init(&msg);
125 memset(&trans, 0, sizeof(trans));
126 trans.delay_usecs = ec_spi->end_of_msg_delay;
127 spi_message_add_tail(&trans, &msg);
129 ret = spi_sync_locked(ec_spi->spi, &msg);
131 /* Reset end-of-response timer */
132 ec_spi->last_transfer_ns = ktime_get_ns();
135 "cs-deassert spi transfer failed: %d\n",
143 * receive_n_bytes - receive n bytes from the EC.
145 * Assumes buf is a pointer into the ec_dev->din buffer
147 static int receive_n_bytes(struct cros_ec_device *ec_dev, u8 *buf, int n)
149 struct cros_ec_spi *ec_spi = ec_dev->priv;
150 struct spi_transfer trans;
151 struct spi_message msg;
154 BUG_ON(buf - ec_dev->din + n > ec_dev->din_size);
156 memset(&trans, 0, sizeof(trans));
161 spi_message_init(&msg);
162 spi_message_add_tail(&trans, &msg);
163 ret = spi_sync_locked(ec_spi->spi, &msg);
165 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
171 * cros_ec_spi_receive_packet - Receive a packet from the EC.
173 * This function has two phases: reading the preamble bytes (since if we read
174 * data from the EC before it is ready to send, we just get preamble) and
175 * reading the actual message.
177 * The received data is placed into ec_dev->din.
179 * @ec_dev: ChromeOS EC device
180 * @need_len: Number of message bytes we need to read
182 static int cros_ec_spi_receive_packet(struct cros_ec_device *ec_dev,
185 struct ec_host_response *response;
188 unsigned long deadline;
191 BUG_ON(ec_dev->din_size < EC_MSG_PREAMBLE_COUNT);
193 /* Receive data until we see the header byte */
194 deadline = jiffies + msecs_to_jiffies(EC_MSG_DEADLINE_MS);
196 unsigned long start_jiffies = jiffies;
198 ret = receive_n_bytes(ec_dev,
200 EC_MSG_PREAMBLE_COUNT);
205 for (end = ptr + EC_MSG_PREAMBLE_COUNT; ptr != end; ptr++) {
206 if (*ptr == EC_SPI_FRAME_START) {
207 dev_dbg(ec_dev->dev, "msg found at %zd\n",
216 * Use the time at the start of the loop as a timeout. This
217 * gives us one last shot at getting the transfer and is useful
218 * in case we got context switched out for a while.
220 if (time_after(start_jiffies, deadline)) {
221 dev_warn(ec_dev->dev, "EC failed to respond in time\n");
227 * ptr now points to the header byte. Copy any valid data to the
228 * start of our buffer
231 BUG_ON(todo < 0 || todo > ec_dev->din_size);
232 todo = min(todo, need_len);
233 memmove(ec_dev->din, ptr, todo);
234 ptr = ec_dev->din + todo;
235 dev_dbg(ec_dev->dev, "need %d, got %d bytes from preamble\n",
239 /* If the entire response struct wasn't read, get the rest of it. */
240 if (todo < sizeof(*response)) {
241 ret = receive_n_bytes(ec_dev, ptr, sizeof(*response) - todo);
244 ptr += (sizeof(*response) - todo);
245 todo = sizeof(*response);
248 response = (struct ec_host_response *)ec_dev->din;
250 /* Abort if data_len is too large. */
251 if (response->data_len > ec_dev->din_size)
254 /* Receive data until we have it all */
255 while (need_len > 0) {
257 * We can't support transfers larger than the SPI FIFO size
258 * unless we have DMA. We don't have DMA on the ISP SPI ports
259 * for Exynos. We need a way of asking SPI driver for
260 * maximum-supported transfer size.
262 todo = min(need_len, 256);
263 dev_dbg(ec_dev->dev, "loop, todo=%d, need_len=%d, ptr=%zd\n",
264 todo, need_len, ptr - ec_dev->din);
266 ret = receive_n_bytes(ec_dev, ptr, todo);
274 dev_dbg(ec_dev->dev, "loop done, ptr=%zd\n", ptr - ec_dev->din);
280 * cros_ec_spi_receive_response - Receive a response from the EC.
282 * This function has two phases: reading the preamble bytes (since if we read
283 * data from the EC before it is ready to send, we just get preamble) and
284 * reading the actual message.
286 * The received data is placed into ec_dev->din.
288 * @ec_dev: ChromeOS EC device
289 * @need_len: Number of message bytes we need to read
291 static int cros_ec_spi_receive_response(struct cros_ec_device *ec_dev,
296 unsigned long deadline;
299 BUG_ON(ec_dev->din_size < EC_MSG_PREAMBLE_COUNT);
301 /* Receive data until we see the header byte */
302 deadline = jiffies + msecs_to_jiffies(EC_MSG_DEADLINE_MS);
304 unsigned long start_jiffies = jiffies;
306 ret = receive_n_bytes(ec_dev,
308 EC_MSG_PREAMBLE_COUNT);
313 for (end = ptr + EC_MSG_PREAMBLE_COUNT; ptr != end; ptr++) {
314 if (*ptr == EC_SPI_FRAME_START) {
315 dev_dbg(ec_dev->dev, "msg found at %zd\n",
324 * Use the time at the start of the loop as a timeout. This
325 * gives us one last shot at getting the transfer and is useful
326 * in case we got context switched out for a while.
328 if (time_after(start_jiffies, deadline)) {
329 dev_warn(ec_dev->dev, "EC failed to respond in time\n");
335 * ptr now points to the header byte. Copy any valid data to the
336 * start of our buffer
339 BUG_ON(todo < 0 || todo > ec_dev->din_size);
340 todo = min(todo, need_len);
341 memmove(ec_dev->din, ptr, todo);
342 ptr = ec_dev->din + todo;
343 dev_dbg(ec_dev->dev, "need %d, got %d bytes from preamble\n",
347 /* Receive data until we have it all */
348 while (need_len > 0) {
350 * We can't support transfers larger than the SPI FIFO size
351 * unless we have DMA. We don't have DMA on the ISP SPI ports
352 * for Exynos. We need a way of asking SPI driver for
353 * maximum-supported transfer size.
355 todo = min(need_len, 256);
356 dev_dbg(ec_dev->dev, "loop, todo=%d, need_len=%d, ptr=%zd\n",
357 todo, need_len, ptr - ec_dev->din);
359 ret = receive_n_bytes(ec_dev, ptr, todo);
363 debug_packet(ec_dev->dev, "interim", ptr, todo);
368 dev_dbg(ec_dev->dev, "loop done, ptr=%zd\n", ptr - ec_dev->din);
374 * do_cros_ec_pkt_xfer_spi - Transfer a packet over SPI and receive the reply
376 * @ec_dev: ChromeOS EC device
377 * @ec_msg: Message to transfer
379 static int do_cros_ec_pkt_xfer_spi(struct cros_ec_device *ec_dev,
380 struct cros_ec_command *ec_msg)
382 struct ec_host_response *response;
383 struct cros_ec_spi *ec_spi = ec_dev->priv;
384 struct spi_transfer trans, trans_delay;
385 struct spi_message msg;
391 int ret = 0, final_ret;
394 len = cros_ec_prepare_tx(ec_dev, ec_msg);
395 dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
397 /* If it's too soon to do another transaction, wait */
398 delay = ktime_get_ns() - ec_spi->last_transfer_ns;
399 if (delay < EC_SPI_RECOVERY_TIME_NS)
400 ndelay(EC_SPI_RECOVERY_TIME_NS - delay);
402 rx_buf = kzalloc(len, GFP_KERNEL);
406 spi_bus_lock(ec_spi->spi->master);
409 * Leave a gap between CS assertion and clocking of data to allow the
412 spi_message_init(&msg);
413 if (ec_spi->start_of_msg_delay) {
414 memset(&trans_delay, 0, sizeof(trans_delay));
415 trans_delay.delay_usecs = ec_spi->start_of_msg_delay;
416 spi_message_add_tail(&trans_delay, &msg);
419 /* Transmit phase - send our message */
420 memset(&trans, 0, sizeof(trans));
421 trans.tx_buf = ec_dev->dout;
422 trans.rx_buf = rx_buf;
425 spi_message_add_tail(&trans, &msg);
426 ret = spi_sync_locked(ec_spi->spi, &msg);
428 /* Get the response */
430 /* Verify that EC can process command */
431 for (i = 0; i < len; i++) {
434 * Seeing the PAST_END, RX_BAD_DATA, or NOT_READY
435 * markers are all signs that the EC didn't fully
436 * receive our command. e.g., if the EC is flashing
437 * itself, it can't respond to any commands and instead
438 * clocks out EC_SPI_PAST_END from its SPI hardware
439 * buffer. Similar occurrences can happen if the AP is
440 * too slow to clock out data after asserting CS -- the
441 * EC will abort and fill its buffer with
442 * EC_SPI_RX_BAD_DATA.
444 * In all cases, these errors should be safe to retry.
445 * Report -EAGAIN and let the caller decide what to do
448 if (rx_byte == EC_SPI_PAST_END ||
449 rx_byte == EC_SPI_RX_BAD_DATA ||
450 rx_byte == EC_SPI_NOT_READY) {
458 ret = cros_ec_spi_receive_packet(ec_dev,
459 ec_msg->insize + sizeof(*response));
460 else if (ret != -EAGAIN)
461 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
463 final_ret = terminate_request(ec_dev);
465 spi_bus_unlock(ec_spi->spi->master);
474 /* check response error code */
475 response = (struct ec_host_response *)ptr;
476 ec_msg->result = response->result;
478 ret = cros_ec_check_result(ec_dev, ec_msg);
482 len = response->data_len;
484 if (len > ec_msg->insize) {
485 dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
486 len, ec_msg->insize);
491 for (i = 0; i < sizeof(*response); i++)
494 /* copy response packet payload and compute checksum */
495 memcpy(ec_msg->data, ptr + sizeof(*response), len);
496 for (i = 0; i < len; i++)
497 sum += ec_msg->data[i];
501 "bad packet checksum, calculated %x\n",
510 if (ec_msg->command == EC_CMD_REBOOT_EC)
511 msleep(EC_REBOOT_DELAY_MS);
517 * do_cros_ec_cmd_xfer_spi - Transfer a message over SPI and receive the reply
519 * @ec_dev: ChromeOS EC device
520 * @ec_msg: Message to transfer
522 static int do_cros_ec_cmd_xfer_spi(struct cros_ec_device *ec_dev,
523 struct cros_ec_command *ec_msg)
525 struct cros_ec_spi *ec_spi = ec_dev->priv;
526 struct spi_transfer trans;
527 struct spi_message msg;
533 int ret = 0, final_ret;
536 len = cros_ec_prepare_tx(ec_dev, ec_msg);
537 dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
539 /* If it's too soon to do another transaction, wait */
540 delay = ktime_get_ns() - ec_spi->last_transfer_ns;
541 if (delay < EC_SPI_RECOVERY_TIME_NS)
542 ndelay(EC_SPI_RECOVERY_TIME_NS - delay);
544 rx_buf = kzalloc(len, GFP_KERNEL);
548 spi_bus_lock(ec_spi->spi->master);
550 /* Transmit phase - send our message */
551 debug_packet(ec_dev->dev, "out", ec_dev->dout, len);
552 memset(&trans, 0, sizeof(trans));
553 trans.tx_buf = ec_dev->dout;
554 trans.rx_buf = rx_buf;
557 spi_message_init(&msg);
558 spi_message_add_tail(&trans, &msg);
559 ret = spi_sync_locked(ec_spi->spi, &msg);
561 /* Get the response */
563 /* Verify that EC can process command */
564 for (i = 0; i < len; i++) {
566 /* See comments in cros_ec_pkt_xfer_spi() */
567 if (rx_byte == EC_SPI_PAST_END ||
568 rx_byte == EC_SPI_RX_BAD_DATA ||
569 rx_byte == EC_SPI_NOT_READY) {
577 ret = cros_ec_spi_receive_response(ec_dev,
578 ec_msg->insize + EC_MSG_TX_PROTO_BYTES);
579 else if (ret != -EAGAIN)
580 dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
582 final_ret = terminate_request(ec_dev);
584 spi_bus_unlock(ec_spi->spi->master);
593 /* check response error code */
594 ec_msg->result = ptr[0];
595 ret = cros_ec_check_result(ec_dev, ec_msg);
600 sum = ptr[0] + ptr[1];
601 if (len > ec_msg->insize) {
602 dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
603 len, ec_msg->insize);
608 /* copy response packet payload and compute checksum */
609 for (i = 0; i < len; i++) {
612 ec_msg->data[i] = ptr[i + 2];
616 debug_packet(ec_dev->dev, "in", ptr, len + 3);
618 if (sum != ptr[len + 2]) {
620 "bad packet checksum, expected %02x, got %02x\n",
629 if (ec_msg->command == EC_CMD_REBOOT_EC)
630 msleep(EC_REBOOT_DELAY_MS);
635 static void cros_ec_xfer_high_pri_work(struct work_struct *work)
637 struct cros_ec_xfer_work_params *params;
639 params = container_of(work, struct cros_ec_xfer_work_params, work);
640 params->ret = params->fn(params->ec_dev, params->ec_msg);
643 static int cros_ec_xfer_high_pri(struct cros_ec_device *ec_dev,
644 struct cros_ec_command *ec_msg,
645 cros_ec_xfer_fn_t fn)
647 struct cros_ec_xfer_work_params params;
649 INIT_WORK_ONSTACK(¶ms.work, cros_ec_xfer_high_pri_work);
650 params.ec_dev = ec_dev;
651 params.ec_msg = ec_msg;
655 * This looks a bit ridiculous. Why do the work on a
656 * different thread if we're just going to block waiting for
657 * the thread to finish? The key here is that the thread is
658 * running at high priority but the calling context might not
659 * be. We need to be at high priority to avoid getting
660 * context switched out for too long and the EC giving up on
663 queue_work(system_highpri_wq, ¶ms.work);
664 flush_work(¶ms.work);
665 destroy_work_on_stack(¶ms.work);
670 static int cros_ec_pkt_xfer_spi(struct cros_ec_device *ec_dev,
671 struct cros_ec_command *ec_msg)
673 return cros_ec_xfer_high_pri(ec_dev, ec_msg, do_cros_ec_pkt_xfer_spi);
676 static int cros_ec_cmd_xfer_spi(struct cros_ec_device *ec_dev,
677 struct cros_ec_command *ec_msg)
679 return cros_ec_xfer_high_pri(ec_dev, ec_msg, do_cros_ec_cmd_xfer_spi);
682 static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev)
684 struct device_node *np = dev->of_node;
688 ret = of_property_read_u32(np, "google,cros-ec-spi-pre-delay", &val);
690 ec_spi->start_of_msg_delay = val;
692 ret = of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val);
694 ec_spi->end_of_msg_delay = val;
697 static int cros_ec_spi_probe(struct spi_device *spi)
699 struct device *dev = &spi->dev;
700 struct cros_ec_device *ec_dev;
701 struct cros_ec_spi *ec_spi;
704 spi->bits_per_word = 8;
705 spi->mode = SPI_MODE_0;
706 err = spi_setup(spi);
710 ec_spi = devm_kzalloc(dev, sizeof(*ec_spi), GFP_KERNEL);
714 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
718 /* Check for any DT properties */
719 cros_ec_spi_dt_probe(ec_spi, dev);
721 spi_set_drvdata(spi, ec_dev);
723 ec_dev->priv = ec_spi;
724 ec_dev->irq = spi->irq;
725 ec_dev->cmd_xfer = cros_ec_cmd_xfer_spi;
726 ec_dev->pkt_xfer = cros_ec_pkt_xfer_spi;
727 ec_dev->phys_name = dev_name(&ec_spi->spi->dev);
728 ec_dev->din_size = EC_MSG_PREAMBLE_COUNT +
729 sizeof(struct ec_host_response) +
730 sizeof(struct ec_response_get_protocol_info);
731 ec_dev->dout_size = sizeof(struct ec_host_request);
733 ec_spi->last_transfer_ns = ktime_get_ns();
735 err = cros_ec_register(ec_dev);
737 dev_err(dev, "cannot register EC\n");
741 device_init_wakeup(&spi->dev, true);
746 #ifdef CONFIG_PM_SLEEP
747 static int cros_ec_spi_suspend(struct device *dev)
749 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
751 return cros_ec_suspend(ec_dev);
754 static int cros_ec_spi_resume(struct device *dev)
756 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
758 return cros_ec_resume(ec_dev);
762 static SIMPLE_DEV_PM_OPS(cros_ec_spi_pm_ops, cros_ec_spi_suspend,
765 static const struct of_device_id cros_ec_spi_of_match[] = {
766 { .compatible = "google,cros-ec-spi", },
769 MODULE_DEVICE_TABLE(of, cros_ec_spi_of_match);
771 static const struct spi_device_id cros_ec_spi_id[] = {
772 { "cros-ec-spi", 0 },
775 MODULE_DEVICE_TABLE(spi, cros_ec_spi_id);
777 static struct spi_driver cros_ec_driver_spi = {
779 .name = "cros-ec-spi",
780 .of_match_table = of_match_ptr(cros_ec_spi_of_match),
781 .pm = &cros_ec_spi_pm_ops,
783 .probe = cros_ec_spi_probe,
784 .id_table = cros_ec_spi_id,
787 module_spi_driver(cros_ec_driver_spi);
789 MODULE_LICENSE("GPL v2");
790 MODULE_DESCRIPTION("SPI interface for ChromeOS Embedded Controller");