1 // SPDX-License-Identifier: GPL-2.0
2 // LPC interface for ChromeOS Embedded Controller
4 // Copyright (C) 2012-2015 Google, Inc
6 // This driver uses the ChromeOS EC byte-level message-based protocol for
7 // communicating the keyboard state (which keys are pressed) from a keyboard EC
8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing,
9 // but everything else (including deghosting) is done here. The main
10 // motivation for this is to keep the EC firmware as simple as possible, since
11 // it cannot be easily upgraded and EC flash/IRAM space is relatively
14 #include <linux/acpi.h>
15 #include <linux/dmi.h>
16 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/kobject.h>
20 #include <linux/module.h>
21 #include <linux/platform_data/cros_ec_commands.h>
22 #include <linux/platform_data/cros_ec_proto.h>
23 #include <linux/platform_device.h>
24 #include <linux/printk.h>
25 #include <linux/reboot.h>
26 #include <linux/suspend.h>
29 #include "cros_ec_lpc_mec.h"
31 #define DRV_NAME "cros_ec_lpcs"
32 #define ACPI_DRV_NAME "GOOG0004"
34 /* True if ACPI device is present */
35 static bool cros_ec_lpc_acpi_device_found;
38 * Indicates that lpc_driver_data.quirk_mmio_memory_base should
39 * be used as the base port for EC mapped memory.
41 #define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0)
43 * Indicates that lpc_driver_data.quirk_acpi_id should be used to find
46 #define CROS_EC_LPC_QUIRK_ACPI_ID BIT(1)
48 * Indicates that lpc_driver_data.quirk_aml_mutex_name should be used
49 * to find an AML mutex to protect access to Microchip EC.
51 #define CROS_EC_LPC_QUIRK_AML_MUTEX BIT(2)
54 * struct lpc_driver_data - driver data attached to a DMI device ID to indicate
56 * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_*
57 * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used
58 * when quirk ...REMAP_MEMORY is set.)
59 * @quirk_acpi_id: An ACPI HID to be used to find the ACPI device.
60 * @quirk_aml_mutex_name: The name of an AML mutex to be used to protect access
63 struct lpc_driver_data {
65 u16 quirk_mmio_memory_base;
66 const char *quirk_acpi_id;
67 const char *quirk_aml_mutex_name;
71 * struct cros_ec_lpc - LPC device-specific data
72 * @mmio_memory_base: The first I/O port addressing EC mapped memory.
79 * struct lpc_driver_ops - LPC driver operations
80 * @read: Copy length bytes from EC address offset into buffer dest.
81 * Returns a negative error code on error, or the 8-bit checksum
83 * @write: Copy length bytes from buffer msg into EC address offset.
84 * Returns a negative error code on error, or the 8-bit checksum
85 * of all bytes written.
87 struct lpc_driver_ops {
88 int (*read)(unsigned int offset, unsigned int length, u8 *dest);
89 int (*write)(unsigned int offset, unsigned int length, const u8 *msg);
92 static struct lpc_driver_ops cros_ec_lpc_ops = { };
95 * A generic instance of the read function of struct lpc_driver_ops, used for
98 static int cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length,
104 for (i = 0; i < length; ++i) {
105 dest[i] = inb(offset + i);
109 /* Return checksum of all bytes read */
114 * A generic instance of the write function of struct lpc_driver_ops, used for
117 static int cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length,
123 for (i = 0; i < length; ++i) {
124 outb(msg[i], offset + i);
128 /* Return checksum of all bytes written */
133 * An instance of the read function of struct lpc_driver_ops, used for the
134 * MEC variant of LPC EC.
136 static int cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length,
139 int in_range = cros_ec_lpc_mec_in_range(offset, length);
145 cros_ec_lpc_io_bytes_mec(MEC_IO_READ,
146 offset - EC_HOST_CMD_REGION0,
148 cros_ec_lpc_read_bytes(offset, length, dest);
152 * An instance of the write function of struct lpc_driver_ops, used for the
153 * MEC variant of LPC EC.
155 static int cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length,
158 int in_range = cros_ec_lpc_mec_in_range(offset, length);
164 cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE,
165 offset - EC_HOST_CMD_REGION0,
167 cros_ec_lpc_write_bytes(offset, length, msg);
170 static int ec_response_timed_out(void)
172 unsigned long one_second = jiffies + HZ;
176 usleep_range(200, 300);
178 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data);
181 if (!(data & EC_LPC_STATUS_BUSY_MASK))
183 usleep_range(100, 200);
184 } while (time_before(jiffies, one_second));
189 static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec,
190 struct cros_ec_command *msg)
192 struct ec_host_response response;
197 ret = cros_ec_prepare_tx(ec, msg);
202 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout);
207 sum = EC_COMMAND_PROTOCOL_3;
208 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum);
212 ret = ec_response_timed_out();
216 dev_warn(ec->dev, "EC response timed out\n");
222 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum);
226 ret = cros_ec_check_result(ec, msg);
230 /* Read back response */
231 dout = (u8 *)&response;
232 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response),
238 msg->result = response.result;
240 if (response.data_len > msg->insize) {
242 "packet too long (%d bytes, expected %d)",
243 response.data_len, msg->insize);
248 /* Read response and process checksum */
249 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET +
250 sizeof(response), response.data_len,
258 "bad packet checksum %02x\n",
264 /* Return actual amount of data received */
265 ret = response.data_len;
270 static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec,
271 struct cros_ec_command *msg)
273 struct ec_lpc_host_args args;
277 if (msg->outsize > EC_PROTO2_MAX_PARAM_SIZE ||
278 msg->insize > EC_PROTO2_MAX_PARAM_SIZE) {
280 "invalid buffer sizes (out %d, in %d)\n",
281 msg->outsize, msg->insize);
285 /* Now actually send the command to the EC and get the result */
286 args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
287 args.command_version = msg->version;
288 args.data_size = msg->outsize;
290 /* Initialize checksum */
291 sum = msg->command + args.flags + args.command_version + args.data_size;
293 /* Copy data and update checksum */
294 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize,
300 /* Finalize checksum and write args */
302 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args),
309 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum);
313 ret = ec_response_timed_out();
317 dev_warn(ec->dev, "EC response timed out\n");
323 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum);
327 ret = cros_ec_check_result(ec, msg);
332 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args);
336 if (args.data_size > msg->insize) {
338 "packet too long (%d bytes, expected %d)",
339 args.data_size, msg->insize);
344 /* Start calculating response checksum */
345 sum = msg->command + args.flags + args.command_version + args.data_size;
347 /* Read response and update checksum */
348 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size,
354 /* Verify checksum */
355 if (args.checksum != sum) {
357 "bad packet checksum, expected %02x, got %02x\n",
363 /* Return actual amount of data received */
364 ret = args.data_size;
369 /* Returns num bytes read, or negative on error. Doesn't need locking. */
370 static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset,
371 unsigned int bytes, void *dest)
373 struct cros_ec_lpc *ec_lpc = ec->priv;
379 if (offset >= EC_MEMMAP_SIZE - bytes)
384 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s);
391 for (; i < EC_MEMMAP_SIZE; i++, s++) {
392 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s);
403 static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data)
405 static const char *env[] = { "ERROR=PANIC", NULL };
406 struct cros_ec_device *ec_dev = data;
407 bool ec_has_more_events;
410 ec_dev->last_event_time = cros_ec_get_time_ns();
412 if (value == ACPI_NOTIFY_CROS_EC_PANIC) {
413 dev_emerg(ec_dev->dev, "CrOS EC Panic Reported. Shutdown is imminent!");
414 blocking_notifier_call_chain(&ec_dev->panic_notifier, 0, ec_dev);
415 kobject_uevent_env(&ec_dev->dev->kobj, KOBJ_CHANGE, (char **)env);
416 /* Begin orderly shutdown. EC will force reset after a short period. */
417 hw_protection_shutdown("CrOS EC Panic", -1);
418 /* Do not query for other events after a panic is reported */
422 if (ec_dev->mkbp_event_supported)
424 ret = cros_ec_get_next_event(ec_dev, NULL,
425 &ec_has_more_events);
427 blocking_notifier_call_chain(
428 &ec_dev->event_notifier, 0,
430 } while (ec_has_more_events);
432 if (value == ACPI_NOTIFY_DEVICE_WAKE)
436 static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level,
437 void *context, void **retval)
439 *(struct acpi_device **)context = acpi_fetch_acpi_dev(handle);
440 return AE_CTRL_TERMINATE;
443 static struct acpi_device *cros_ec_lpc_get_device(const char *id)
445 struct acpi_device *adev = NULL;
446 acpi_status status = acpi_get_devices(id, cros_ec_lpc_parse_device,
448 if (ACPI_FAILURE(status)) {
449 pr_warn(DRV_NAME ": Looking for %s failed\n", id);
456 static int cros_ec_lpc_probe(struct platform_device *pdev)
458 struct device *dev = &pdev->dev;
459 struct acpi_device *adev;
461 struct cros_ec_device *ec_dev;
462 struct cros_ec_lpc *ec_lpc;
463 struct lpc_driver_data *driver_data;
468 ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL);
472 ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP;
474 driver_data = platform_get_drvdata(pdev);
476 quirks = driver_data->quirks;
479 dev_info(dev, "loaded with quirks %8.08x\n", quirks);
481 if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY)
482 ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base;
484 if (quirks & CROS_EC_LPC_QUIRK_ACPI_ID) {
485 adev = cros_ec_lpc_get_device(driver_data->quirk_acpi_id);
487 dev_err(dev, "failed to get ACPI device '%s'",
488 driver_data->quirk_acpi_id);
491 ACPI_COMPANION_SET(dev, adev);
494 if (quirks & CROS_EC_LPC_QUIRK_AML_MUTEX) {
496 = driver_data->quirk_aml_mutex_name;
497 ret = cros_ec_lpc_mec_acpi_mutex(ACPI_COMPANION(dev), name);
499 dev_err(dev, "failed to get AML mutex '%s'", name);
502 dev_info(dev, "got AML mutex '%s'", name);
507 * The Framework Laptop (and possibly other non-ChromeOS devices)
508 * only exposes the eight I/O ports that are required for the Microchip EC.
509 * Requesting a larger reservation will fail.
511 if (!devm_request_region(dev, EC_HOST_CMD_REGION0,
512 EC_HOST_CMD_MEC_REGION_SIZE, dev_name(dev))) {
513 dev_err(dev, "couldn't reserve MEC region\n");
517 cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0,
518 EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE);
521 * Read the mapped ID twice, the first one is assuming the
522 * EC is a Microchip Embedded Controller (MEC) variant, if the
523 * protocol fails, fallback to the non MEC variant and try to
526 cros_ec_lpc_ops.read = cros_ec_lpc_mec_read_bytes;
527 cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes;
528 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf);
531 if (buf[0] != 'E' || buf[1] != 'C') {
532 if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE,
534 dev_err(dev, "couldn't reserve memmap region\n");
538 /* Re-assign read/write operations for the non MEC variant */
539 cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes;
540 cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes;
541 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2,
545 if (buf[0] != 'E' || buf[1] != 'C') {
546 dev_err(dev, "EC ID not detected\n");
550 /* Reserve the remaining I/O ports required by the non-MEC protocol. */
551 if (!devm_request_region(dev, EC_HOST_CMD_REGION0 + EC_HOST_CMD_MEC_REGION_SIZE,
552 EC_HOST_CMD_REGION_SIZE - EC_HOST_CMD_MEC_REGION_SIZE,
554 dev_err(dev, "couldn't reserve remainder of region0\n");
557 if (!devm_request_region(dev, EC_HOST_CMD_REGION1,
558 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) {
559 dev_err(dev, "couldn't reserve region1\n");
564 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
568 platform_set_drvdata(pdev, ec_dev);
570 ec_dev->phys_name = dev_name(dev);
571 ec_dev->cmd_xfer = cros_ec_cmd_xfer_lpc;
572 ec_dev->pkt_xfer = cros_ec_pkt_xfer_lpc;
573 ec_dev->cmd_readmem = cros_ec_lpc_readmem;
574 ec_dev->din_size = sizeof(struct ec_host_response) +
575 sizeof(struct ec_response_get_protocol_info);
576 ec_dev->dout_size = sizeof(struct ec_host_request);
577 ec_dev->priv = ec_lpc;
580 * Some boards do not have an IRQ allotted for cros_ec_lpc,
581 * which makes ENXIO an expected (and safe) scenario.
583 irq = platform_get_irq_optional(pdev, 0);
586 else if (irq != -ENXIO) {
587 dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq);
591 ret = cros_ec_register(ec_dev);
593 dev_err(dev, "couldn't register ec_dev (%d)\n", ret);
598 * Connect a notify handler to process MKBP messages if we have a
599 * companion ACPI device.
601 adev = ACPI_COMPANION(dev);
603 status = acpi_install_notify_handler(adev->handle,
605 cros_ec_lpc_acpi_notify,
607 if (ACPI_FAILURE(status))
608 dev_warn(dev, "Failed to register notifier %08x\n",
615 static void cros_ec_lpc_remove(struct platform_device *pdev)
617 struct cros_ec_device *ec_dev = platform_get_drvdata(pdev);
618 struct acpi_device *adev;
620 adev = ACPI_COMPANION(&pdev->dev);
622 acpi_remove_notify_handler(adev->handle, ACPI_ALL_NOTIFY,
623 cros_ec_lpc_acpi_notify);
625 cros_ec_unregister(ec_dev);
628 static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = {
629 { ACPI_DRV_NAME, 0 },
632 MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids);
634 static const struct lpc_driver_data framework_laptop_amd_lpc_driver_data __initconst = {
635 .quirks = CROS_EC_LPC_QUIRK_REMAP_MEMORY,
636 .quirk_mmio_memory_base = 0xE00,
639 static const struct lpc_driver_data framework_laptop_11_lpc_driver_data __initconst = {
640 .quirks = CROS_EC_LPC_QUIRK_ACPI_ID|CROS_EC_LPC_QUIRK_AML_MUTEX,
641 .quirk_acpi_id = "PNP0C09",
642 .quirk_aml_mutex_name = "ECMT",
645 static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = {
648 * Today all Chromebooks/boxes ship with Google_* as version and
649 * coreboot as bios vendor. No other systems with this
650 * combination are known to date.
653 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
654 DMI_MATCH(DMI_BIOS_VERSION, "Google_"),
659 * If the box is running custom coreboot firmware then the
660 * DMI BIOS version string will not be matched by "Google_",
661 * but the system vendor string will still be matched by
665 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
666 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
670 /* x86-link, the Chromebook Pixel. */
672 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
673 DMI_MATCH(DMI_PRODUCT_NAME, "Link"),
677 /* x86-samus, the Chromebook Pixel 2. */
679 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
680 DMI_MATCH(DMI_PRODUCT_NAME, "Samus"),
684 /* x86-peppy, the Acer C720 Chromebook. */
686 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
687 DMI_MATCH(DMI_PRODUCT_NAME, "Peppy"),
691 /* x86-glimmer, the Lenovo Thinkpad Yoga 11e. */
693 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
694 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"),
697 /* A small number of non-Chromebook/box machines also use the ChromeOS EC */
699 /* the Framework Laptop 13 (AMD Ryzen) and 16 (AMD Ryzen) */
701 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
702 DMI_MATCH(DMI_PRODUCT_NAME, "AMD Ryzen"),
703 DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"),
705 .driver_data = (void *)&framework_laptop_amd_lpc_driver_data,
708 /* the Framework Laptop (Intel 11th, 12th, 13th Generation) */
710 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
711 DMI_MATCH(DMI_PRODUCT_NAME, "Laptop"),
713 .driver_data = (void *)&framework_laptop_11_lpc_driver_data,
717 MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table);
719 #ifdef CONFIG_PM_SLEEP
720 static int cros_ec_lpc_prepare(struct device *dev)
722 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
723 return cros_ec_suspend_prepare(ec_dev);
726 static void cros_ec_lpc_complete(struct device *dev)
728 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
729 cros_ec_resume_complete(ec_dev);
732 static int cros_ec_lpc_suspend_late(struct device *dev)
734 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
736 return cros_ec_suspend_late(ec_dev);
739 static int cros_ec_lpc_resume_early(struct device *dev)
741 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
743 return cros_ec_resume_early(ec_dev);
747 static const struct dev_pm_ops cros_ec_lpc_pm_ops = {
748 #ifdef CONFIG_PM_SLEEP
749 .prepare = cros_ec_lpc_prepare,
750 .complete = cros_ec_lpc_complete,
752 SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend_late, cros_ec_lpc_resume_early)
755 static struct platform_driver cros_ec_lpc_driver = {
758 .acpi_match_table = cros_ec_lpc_acpi_device_ids,
759 .pm = &cros_ec_lpc_pm_ops,
761 * ACPI child devices may probe before us, and they racily
762 * check our drvdata pointer. Force synchronous probe until
763 * those races are resolved.
765 .probe_type = PROBE_FORCE_SYNCHRONOUS,
767 .probe = cros_ec_lpc_probe,
768 .remove_new = cros_ec_lpc_remove,
771 static struct platform_device cros_ec_lpc_device = {
775 static int __init cros_ec_lpc_init(void)
778 const struct dmi_system_id *dmi_match;
780 cros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME);
782 dmi_match = dmi_first_match(cros_ec_lpc_dmi_table);
784 if (!cros_ec_lpc_acpi_device_found && !dmi_match) {
785 pr_err(DRV_NAME ": unsupported system.\n");
789 /* Register the driver */
790 ret = platform_driver_register(&cros_ec_lpc_driver);
792 pr_err(DRV_NAME ": can't register driver: %d\n", ret);
796 if (!cros_ec_lpc_acpi_device_found) {
797 /* Pass the DMI match's driver data down to the platform device */
798 platform_set_drvdata(&cros_ec_lpc_device, dmi_match->driver_data);
800 /* Register the device, and it'll get hooked up automatically */
801 ret = platform_device_register(&cros_ec_lpc_device);
803 pr_err(DRV_NAME ": can't register device: %d\n", ret);
804 platform_driver_unregister(&cros_ec_lpc_driver);
811 static void __exit cros_ec_lpc_exit(void)
813 if (!cros_ec_lpc_acpi_device_found)
814 platform_device_unregister(&cros_ec_lpc_device);
815 platform_driver_unregister(&cros_ec_lpc_driver);
818 module_init(cros_ec_lpc_init);
819 module_exit(cros_ec_lpc_exit);
821 MODULE_LICENSE("GPL");
822 MODULE_DESCRIPTION("ChromeOS EC LPC driver");