1 // SPDX-License-Identifier: GPL-2.0
2 // LPC interface for ChromeOS Embedded Controller
4 // Copyright (C) 2012-2015 Google, Inc
6 // This driver uses the ChromeOS EC byte-level message-based protocol for
7 // communicating the keyboard state (which keys are pressed) from a keyboard EC
8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing,
9 // but everything else (including deghosting) is done here. The main
10 // motivation for this is to keep the EC firmware as simple as possible, since
11 // it cannot be easily upgraded and EC flash/IRAM space is relatively
14 #include <linux/acpi.h>
15 #include <linux/dmi.h>
16 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/platform_data/cros_ec_commands.h>
21 #include <linux/platform_data/cros_ec_proto.h>
22 #include <linux/platform_device.h>
23 #include <linux/printk.h>
24 #include <linux/suspend.h>
27 #include "cros_ec_lpc_mec.h"
29 #define DRV_NAME "cros_ec_lpcs"
30 #define ACPI_DRV_NAME "GOOG0004"
32 /* True if ACPI device is present */
33 static bool cros_ec_lpc_acpi_device_found;
36 * struct lpc_driver_ops - LPC driver operations
37 * @read: Copy length bytes from EC address offset into buffer dest. Returns
38 * the 8-bit checksum of all bytes read.
39 * @write: Copy length bytes from buffer msg into EC address offset. Returns
40 * the 8-bit checksum of all bytes written.
42 struct lpc_driver_ops {
43 u8 (*read)(unsigned int offset, unsigned int length, u8 *dest);
44 u8 (*write)(unsigned int offset, unsigned int length, const u8 *msg);
47 static struct lpc_driver_ops cros_ec_lpc_ops = { };
50 * A generic instance of the read function of struct lpc_driver_ops, used for
53 static u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length,
59 for (i = 0; i < length; ++i) {
60 dest[i] = inb(offset + i);
64 /* Return checksum of all bytes read */
69 * A generic instance of the write function of struct lpc_driver_ops, used for
72 static u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length,
78 for (i = 0; i < length; ++i) {
79 outb(msg[i], offset + i);
83 /* Return checksum of all bytes written */
88 * An instance of the read function of struct lpc_driver_ops, used for the
89 * MEC variant of LPC EC.
91 static u8 cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length,
94 int in_range = cros_ec_lpc_mec_in_range(offset, length);
100 cros_ec_lpc_io_bytes_mec(MEC_IO_READ,
101 offset - EC_HOST_CMD_REGION0,
103 cros_ec_lpc_read_bytes(offset, length, dest);
107 * An instance of the write function of struct lpc_driver_ops, used for the
108 * MEC variant of LPC EC.
110 static u8 cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length,
113 int in_range = cros_ec_lpc_mec_in_range(offset, length);
119 cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE,
120 offset - EC_HOST_CMD_REGION0,
122 cros_ec_lpc_write_bytes(offset, length, msg);
125 static int ec_response_timed_out(void)
127 unsigned long one_second = jiffies + HZ;
130 usleep_range(200, 300);
132 if (!(cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data) &
133 EC_LPC_STATUS_BUSY_MASK))
135 usleep_range(100, 200);
136 } while (time_before(jiffies, one_second));
141 static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec,
142 struct cros_ec_command *msg)
144 struct ec_host_response response;
149 ret = cros_ec_prepare_tx(ec, msg);
154 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout);
157 sum = EC_COMMAND_PROTOCOL_3;
158 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum);
160 if (ec_response_timed_out()) {
161 dev_warn(ec->dev, "EC response timed out\n");
167 msg->result = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum);
168 ret = cros_ec_check_result(ec, msg);
172 /* Read back response */
173 dout = (u8 *)&response;
174 sum = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response),
177 msg->result = response.result;
179 if (response.data_len > msg->insize) {
181 "packet too long (%d bytes, expected %d)",
182 response.data_len, msg->insize);
187 /* Read response and process checksum */
188 sum += cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET +
189 sizeof(response), response.data_len,
194 "bad packet checksum %02x\n",
200 /* Return actual amount of data received */
201 ret = response.data_len;
206 static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec,
207 struct cros_ec_command *msg)
209 struct ec_lpc_host_args args;
213 if (msg->outsize > EC_PROTO2_MAX_PARAM_SIZE ||
214 msg->insize > EC_PROTO2_MAX_PARAM_SIZE) {
216 "invalid buffer sizes (out %d, in %d)\n",
217 msg->outsize, msg->insize);
221 /* Now actually send the command to the EC and get the result */
222 args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
223 args.command_version = msg->version;
224 args.data_size = msg->outsize;
226 /* Initialize checksum */
227 sum = msg->command + args.flags + args.command_version + args.data_size;
229 /* Copy data and update checksum */
230 sum += cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize,
233 /* Finalize checksum and write args */
235 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args),
240 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum);
242 if (ec_response_timed_out()) {
243 dev_warn(ec->dev, "EC response timed out\n");
249 msg->result = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum);
250 ret = cros_ec_check_result(ec, msg);
255 cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args);
257 if (args.data_size > msg->insize) {
259 "packet too long (%d bytes, expected %d)",
260 args.data_size, msg->insize);
265 /* Start calculating response checksum */
266 sum = msg->command + args.flags + args.command_version + args.data_size;
268 /* Read response and update checksum */
269 sum += cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size,
272 /* Verify checksum */
273 if (args.checksum != sum) {
275 "bad packet checksum, expected %02x, got %02x\n",
281 /* Return actual amount of data received */
282 ret = args.data_size;
287 /* Returns num bytes read, or negative on error. Doesn't need locking. */
288 static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset,
289 unsigned int bytes, void *dest)
295 if (offset >= EC_MEMMAP_SIZE - bytes)
300 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + offset, bytes, s);
305 for (; i < EC_MEMMAP_SIZE; i++, s++) {
306 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + i, 1, s);
315 static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data)
317 struct cros_ec_device *ec_dev = data;
318 bool ec_has_more_events;
321 ec_dev->last_event_time = cros_ec_get_time_ns();
323 if (ec_dev->mkbp_event_supported)
325 ret = cros_ec_get_next_event(ec_dev, NULL,
326 &ec_has_more_events);
328 blocking_notifier_call_chain(
329 &ec_dev->event_notifier, 0,
331 } while (ec_has_more_events);
333 if (value == ACPI_NOTIFY_DEVICE_WAKE)
337 static int cros_ec_lpc_probe(struct platform_device *pdev)
339 struct device *dev = &pdev->dev;
340 struct acpi_device *adev;
342 struct cros_ec_device *ec_dev;
347 * The Framework Laptop (and possibly other non-ChromeOS devices)
348 * only exposes the eight I/O ports that are required for the Microchip EC.
349 * Requesting a larger reservation will fail.
351 if (!devm_request_region(dev, EC_HOST_CMD_REGION0,
352 EC_HOST_CMD_MEC_REGION_SIZE, dev_name(dev))) {
353 dev_err(dev, "couldn't reserve MEC region\n");
358 * Read the mapped ID twice, the first one is assuming the
359 * EC is a Microchip Embedded Controller (MEC) variant, if the
360 * protocol fails, fallback to the non MEC variant and try to
363 cros_ec_lpc_ops.read = cros_ec_lpc_mec_read_bytes;
364 cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes;
365 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf);
366 if (buf[0] != 'E' || buf[1] != 'C') {
367 if (!devm_request_region(dev, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE,
369 dev_err(dev, "couldn't reserve memmap region\n");
373 /* Re-assign read/write operations for the non MEC variant */
374 cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes;
375 cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes;
376 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2,
378 if (buf[0] != 'E' || buf[1] != 'C') {
379 dev_err(dev, "EC ID not detected\n");
383 /* Reserve the remaining I/O ports required by the non-MEC protocol. */
384 if (!devm_request_region(dev, EC_HOST_CMD_REGION0 + EC_HOST_CMD_MEC_REGION_SIZE,
385 EC_HOST_CMD_REGION_SIZE - EC_HOST_CMD_MEC_REGION_SIZE,
387 dev_err(dev, "couldn't reserve remainder of region0\n");
390 if (!devm_request_region(dev, EC_HOST_CMD_REGION1,
391 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) {
392 dev_err(dev, "couldn't reserve region1\n");
397 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
401 platform_set_drvdata(pdev, ec_dev);
403 ec_dev->phys_name = dev_name(dev);
404 ec_dev->cmd_xfer = cros_ec_cmd_xfer_lpc;
405 ec_dev->pkt_xfer = cros_ec_pkt_xfer_lpc;
406 ec_dev->cmd_readmem = cros_ec_lpc_readmem;
407 ec_dev->din_size = sizeof(struct ec_host_response) +
408 sizeof(struct ec_response_get_protocol_info);
409 ec_dev->dout_size = sizeof(struct ec_host_request);
412 * Some boards do not have an IRQ allotted for cros_ec_lpc,
413 * which makes ENXIO an expected (and safe) scenario.
415 irq = platform_get_irq_optional(pdev, 0);
418 else if (irq != -ENXIO) {
419 dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq);
423 ret = cros_ec_register(ec_dev);
425 dev_err(dev, "couldn't register ec_dev (%d)\n", ret);
430 * Connect a notify handler to process MKBP messages if we have a
431 * companion ACPI device.
433 adev = ACPI_COMPANION(dev);
435 status = acpi_install_notify_handler(adev->handle,
437 cros_ec_lpc_acpi_notify,
439 if (ACPI_FAILURE(status))
440 dev_warn(dev, "Failed to register notifier %08x\n",
447 static int cros_ec_lpc_remove(struct platform_device *pdev)
449 struct cros_ec_device *ec_dev = platform_get_drvdata(pdev);
450 struct acpi_device *adev;
452 adev = ACPI_COMPANION(&pdev->dev);
454 acpi_remove_notify_handler(adev->handle, ACPI_ALL_NOTIFY,
455 cros_ec_lpc_acpi_notify);
457 cros_ec_unregister(ec_dev);
462 static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = {
463 { ACPI_DRV_NAME, 0 },
466 MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids);
468 static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = {
471 * Today all Chromebooks/boxes ship with Google_* as version and
472 * coreboot as bios vendor. No other systems with this
473 * combination are known to date.
476 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
477 DMI_MATCH(DMI_BIOS_VERSION, "Google_"),
482 * If the box is running custom coreboot firmware then the
483 * DMI BIOS version string will not be matched by "Google_",
484 * but the system vendor string will still be matched by
488 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
489 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
493 /* x86-link, the Chromebook Pixel. */
495 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
496 DMI_MATCH(DMI_PRODUCT_NAME, "Link"),
500 /* x86-samus, the Chromebook Pixel 2. */
502 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
503 DMI_MATCH(DMI_PRODUCT_NAME, "Samus"),
507 /* x86-peppy, the Acer C720 Chromebook. */
509 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
510 DMI_MATCH(DMI_PRODUCT_NAME, "Peppy"),
514 /* x86-glimmer, the Lenovo Thinkpad Yoga 11e. */
516 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
517 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"),
520 /* A small number of non-Chromebook/box machines also use the ChromeOS EC */
522 /* the Framework Laptop */
524 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
525 DMI_MATCH(DMI_PRODUCT_NAME, "Laptop"),
530 MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table);
532 #ifdef CONFIG_PM_SLEEP
533 static int cros_ec_lpc_suspend(struct device *dev)
535 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
537 return cros_ec_suspend(ec_dev);
540 static int cros_ec_lpc_resume(struct device *dev)
542 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
544 return cros_ec_resume(ec_dev);
548 static const struct dev_pm_ops cros_ec_lpc_pm_ops = {
549 SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend, cros_ec_lpc_resume)
552 static struct platform_driver cros_ec_lpc_driver = {
555 .acpi_match_table = cros_ec_lpc_acpi_device_ids,
556 .pm = &cros_ec_lpc_pm_ops,
558 .probe = cros_ec_lpc_probe,
559 .remove = cros_ec_lpc_remove,
562 static struct platform_device cros_ec_lpc_device = {
566 static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level,
567 void *context, void **retval)
569 *(bool *)context = true;
570 return AE_CTRL_TERMINATE;
573 static int __init cros_ec_lpc_init(void)
578 status = acpi_get_devices(ACPI_DRV_NAME, cros_ec_lpc_parse_device,
579 &cros_ec_lpc_acpi_device_found, NULL);
580 if (ACPI_FAILURE(status))
581 pr_warn(DRV_NAME ": Looking for %s failed\n", ACPI_DRV_NAME);
583 if (!cros_ec_lpc_acpi_device_found &&
584 !dmi_check_system(cros_ec_lpc_dmi_table)) {
585 pr_err(DRV_NAME ": unsupported system.\n");
589 cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0,
590 EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE);
592 /* Register the driver */
593 ret = platform_driver_register(&cros_ec_lpc_driver);
595 pr_err(DRV_NAME ": can't register driver: %d\n", ret);
596 cros_ec_lpc_mec_destroy();
600 if (!cros_ec_lpc_acpi_device_found) {
601 /* Register the device, and it'll get hooked up automatically */
602 ret = platform_device_register(&cros_ec_lpc_device);
604 pr_err(DRV_NAME ": can't register device: %d\n", ret);
605 platform_driver_unregister(&cros_ec_lpc_driver);
606 cros_ec_lpc_mec_destroy();
613 static void __exit cros_ec_lpc_exit(void)
615 if (!cros_ec_lpc_acpi_device_found)
616 platform_device_unregister(&cros_ec_lpc_device);
617 platform_driver_unregister(&cros_ec_lpc_driver);
618 cros_ec_lpc_mec_destroy();
621 module_init(cros_ec_lpc_init);
622 module_exit(cros_ec_lpc_exit);
624 MODULE_LICENSE("GPL");
625 MODULE_DESCRIPTION("ChromeOS EC LPC driver");