2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/export.h>
20 #include <linux/of_clk.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
33 #include <dt-bindings/pinctrl/sun4i-a10.h>
36 #include "pinctrl-sunxi.h"
38 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
39 static struct irq_chip sunxi_pinctrl_level_irq_chip;
41 static struct sunxi_pinctrl_group *
42 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
46 for (i = 0; i < pctl->ngroups; i++) {
47 struct sunxi_pinctrl_group *grp = pctl->groups + i;
49 if (!strcmp(grp->name, group))
56 static struct sunxi_pinctrl_function *
57 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
60 struct sunxi_pinctrl_function *func = pctl->functions;
63 for (i = 0; i < pctl->nfunctions; i++) {
67 if (!strcmp(func[i].name, name))
74 static struct sunxi_desc_function *
75 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
77 const char *func_name)
81 for (i = 0; i < pctl->desc->npins; i++) {
82 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
84 if (!strcmp(pin->pin.name, pin_name)) {
85 struct sunxi_desc_function *func = pin->functions;
88 if (!strcmp(func->name, func_name) &&
90 func->variant & pctl->variant))
101 static struct sunxi_desc_function *
102 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
104 const char *func_name)
108 for (i = 0; i < pctl->desc->npins; i++) {
109 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
111 if (pin->pin.number == pin_num) {
112 struct sunxi_desc_function *func = pin->functions;
115 if (!strcmp(func->name, func_name))
126 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
128 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
130 return pctl->ngroups;
133 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138 return pctl->groups[group].name;
141 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
143 const unsigned **pins,
146 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
148 *pins = (unsigned *)&pctl->groups[group].pin;
154 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
156 return of_find_property(node, "bias-pull-up", NULL) ||
157 of_find_property(node, "bias-pull-down", NULL) ||
158 of_find_property(node, "bias-disable", NULL) ||
159 of_find_property(node, "allwinner,pull", NULL);
162 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
164 return of_find_property(node, "drive-strength", NULL) ||
165 of_find_property(node, "allwinner,drive", NULL);
168 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
172 /* Try the new style binding */
173 if (of_find_property(node, "bias-pull-up", NULL))
174 return PIN_CONFIG_BIAS_PULL_UP;
176 if (of_find_property(node, "bias-pull-down", NULL))
177 return PIN_CONFIG_BIAS_PULL_DOWN;
179 if (of_find_property(node, "bias-disable", NULL))
180 return PIN_CONFIG_BIAS_DISABLE;
182 /* And fall back to the old binding */
183 if (of_property_read_u32(node, "allwinner,pull", &val))
187 case SUN4I_PINCTRL_NO_PULL:
188 return PIN_CONFIG_BIAS_DISABLE;
189 case SUN4I_PINCTRL_PULL_UP:
190 return PIN_CONFIG_BIAS_PULL_UP;
191 case SUN4I_PINCTRL_PULL_DOWN:
192 return PIN_CONFIG_BIAS_PULL_DOWN;
198 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
202 /* Try the new style binding */
203 if (!of_property_read_u32(node, "drive-strength", &val)) {
204 /* We can't go below 10mA ... */
208 /* ... and only up to 40 mA ... */
212 /* by steps of 10 mA */
213 return rounddown(val, 10);
216 /* And then fall back to the old binding */
217 if (of_property_read_u32(node, "allwinner,drive", &val))
220 return (val + 1) * 10;
223 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
225 const char *function;
228 /* Try the generic binding */
229 ret = of_property_read_string(node, "function", &function);
233 /* And fall back to our legacy one */
234 ret = of_property_read_string(node, "allwinner,function", &function);
241 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
246 /* Try the generic binding */
247 count = of_property_count_strings(node, "pins");
253 /* And fall back to our legacy one */
254 count = of_property_count_strings(node, "allwinner,pins");
257 return "allwinner,pins";
263 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
266 unsigned long *pinconfig;
267 unsigned int configlen = 0, idx = 0;
270 if (sunxi_pctrl_has_drive_prop(node))
272 if (sunxi_pctrl_has_bias_prop(node))
276 * If we don't have any configuration, bail out
281 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
283 return ERR_PTR(-ENOMEM);
285 if (sunxi_pctrl_has_drive_prop(node)) {
286 int drive = sunxi_pctrl_parse_drive_prop(node);
292 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
296 if (sunxi_pctrl_has_bias_prop(node)) {
297 int pull = sunxi_pctrl_parse_bias_prop(node);
304 if (pull != PIN_CONFIG_BIAS_DISABLE)
305 arg = 1; /* hardware uses weak pull resistors */
307 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
319 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
320 struct device_node *node,
321 struct pinctrl_map **map,
324 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
325 unsigned long *pinconfig;
326 struct property *prop;
327 const char *function, *pin_prop;
329 int ret, npins, nmaps, configlen = 0, i = 0;
334 function = sunxi_pctrl_parse_function_prop(node);
336 dev_err(pctl->dev, "missing function property in node %pOFn\n",
341 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
343 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
349 * We have two maps for each pin: one for the function, one
350 * for the configuration (bias, strength, etc).
352 * We might be slightly overshooting, since we might not have
356 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
360 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
361 if (IS_ERR(pinconfig)) {
362 ret = PTR_ERR(pinconfig);
366 of_property_for_each_string(node, pin_prop, prop, group) {
367 struct sunxi_pinctrl_group *grp =
368 sunxi_pinctrl_find_group_by_name(pctl, group);
371 dev_err(pctl->dev, "unknown pin %s", group);
375 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
378 dev_err(pctl->dev, "unsupported function %s on pin %s",
383 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
384 (*map)[i].data.mux.group = group;
385 (*map)[i].data.mux.function = function;
390 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
391 (*map)[i].data.configs.group_or_pin = group;
392 (*map)[i].data.configs.configs = pinconfig;
393 (*map)[i].data.configs.num_configs = configlen;
401 * We know have the number of maps we need, we can resize our
404 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
416 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
417 struct pinctrl_map *map,
422 /* pin config is never in the first map */
423 for (i = 1; i < num_maps; i++) {
424 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
428 * All the maps share the same pin config,
429 * free only the first one we find.
431 kfree(map[i].data.configs.configs);
438 static const struct pinctrl_ops sunxi_pctrl_ops = {
439 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
440 .dt_free_map = sunxi_pctrl_dt_free_map,
441 .get_groups_count = sunxi_pctrl_get_groups_count,
442 .get_group_name = sunxi_pctrl_get_group_name,
443 .get_group_pins = sunxi_pctrl_get_group_pins,
446 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
447 u32 *offset, u32 *shift, u32 *mask)
450 case PIN_CONFIG_DRIVE_STRENGTH:
451 *offset = sunxi_dlevel_reg(pin);
452 *shift = sunxi_dlevel_offset(pin);
453 *mask = DLEVEL_PINS_MASK;
456 case PIN_CONFIG_BIAS_PULL_UP:
457 case PIN_CONFIG_BIAS_PULL_DOWN:
458 case PIN_CONFIG_BIAS_DISABLE:
459 *offset = sunxi_pull_reg(pin);
460 *shift = sunxi_pull_offset(pin);
461 *mask = PULL_PINS_MASK;
471 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
472 unsigned long *config)
474 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
475 enum pin_config_param param = pinconf_to_config_param(*config);
476 u32 offset, shift, mask, val;
480 pin -= pctl->desc->pin_base;
482 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
486 val = (readl(pctl->membase + offset) >> shift) & mask;
488 switch (pinconf_to_config_param(*config)) {
489 case PIN_CONFIG_DRIVE_STRENGTH:
490 arg = (val + 1) * 10;
493 case PIN_CONFIG_BIAS_PULL_UP:
494 if (val != SUN4I_PINCTRL_PULL_UP)
496 arg = 1; /* hardware is weak pull-up */
499 case PIN_CONFIG_BIAS_PULL_DOWN:
500 if (val != SUN4I_PINCTRL_PULL_DOWN)
502 arg = 1; /* hardware is weak pull-down */
505 case PIN_CONFIG_BIAS_DISABLE:
506 if (val != SUN4I_PINCTRL_NO_PULL)
512 /* sunxi_pconf_reg should catch anything unsupported */
517 *config = pinconf_to_config_packed(param, arg);
522 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
524 unsigned long *config)
526 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
527 struct sunxi_pinctrl_group *g = &pctl->groups[group];
529 /* We only support 1 pin per group. Chain it to the pin callback */
530 return sunxi_pconf_get(pctldev, g->pin, config);
533 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
535 unsigned long *configs,
536 unsigned num_configs)
538 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
539 struct sunxi_pinctrl_group *g = &pctl->groups[group];
540 unsigned pin = g->pin - pctl->desc->pin_base;
543 for (i = 0; i < num_configs; i++) {
544 enum pin_config_param param;
546 u32 offset, shift, mask, reg;
550 param = pinconf_to_config_param(configs[i]);
551 arg = pinconf_to_config_argument(configs[i]);
553 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
558 case PIN_CONFIG_DRIVE_STRENGTH:
559 if (arg < 10 || arg > 40)
562 * We convert from mA to what the register expects:
570 case PIN_CONFIG_BIAS_DISABLE:
573 case PIN_CONFIG_BIAS_PULL_UP:
578 case PIN_CONFIG_BIAS_PULL_DOWN:
584 /* sunxi_pconf_reg should catch anything unsupported */
589 raw_spin_lock_irqsave(&pctl->lock, flags);
590 reg = readl(pctl->membase + offset);
591 reg &= ~(mask << shift);
592 writel(reg | val << shift, pctl->membase + offset);
593 raw_spin_unlock_irqrestore(&pctl->lock, flags);
594 } /* for each config */
599 static const struct pinconf_ops sunxi_pconf_ops = {
601 .pin_config_get = sunxi_pconf_get,
602 .pin_config_group_get = sunxi_pconf_group_get,
603 .pin_config_group_set = sunxi_pconf_group_set,
606 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
608 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
610 return pctl->nfunctions;
613 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
616 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
618 return pctl->functions[function].name;
621 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
623 const char * const **groups,
624 unsigned * const num_groups)
626 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
628 *groups = pctl->functions[function].groups;
629 *num_groups = pctl->functions[function].ngroups;
634 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
638 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
642 raw_spin_lock_irqsave(&pctl->lock, flags);
644 pin -= pctl->desc->pin_base;
645 val = readl(pctl->membase + sunxi_mux_reg(pin));
646 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
647 writel((val & ~mask) | config << sunxi_mux_offset(pin),
648 pctl->membase + sunxi_mux_reg(pin));
650 raw_spin_unlock_irqrestore(&pctl->lock, flags);
653 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
657 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
658 struct sunxi_pinctrl_group *g = pctl->groups + group;
659 struct sunxi_pinctrl_function *func = pctl->functions + function;
660 struct sunxi_desc_function *desc =
661 sunxi_pinctrl_desc_find_function_by_name(pctl,
668 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
674 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
675 struct pinctrl_gpio_range *range,
679 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
680 struct sunxi_desc_function *desc;
688 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
692 sunxi_pmx_set(pctldev, offset, desc->muxval);
697 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
699 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
700 unsigned short bank = offset / PINS_PER_BANK;
701 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank];
702 struct regulator *reg;
705 reg = s_reg->regulator;
709 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
710 reg = regulator_get(pctl->dev, supply);
712 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
717 s_reg->regulator = reg;
718 refcount_set(&s_reg->refcount, 1);
720 refcount_inc(&s_reg->refcount);
723 ret = regulator_enable(reg);
726 "Couldn't enable bank P%c regulator\n", 'A' + bank);
733 if (refcount_dec_and_test(&s_reg->refcount)) {
734 regulator_put(s_reg->regulator);
735 s_reg->regulator = NULL;
741 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
743 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
744 unsigned short bank = offset / PINS_PER_BANK;
745 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank];
747 if (!refcount_dec_and_test(&s_reg->refcount))
750 regulator_disable(s_reg->regulator);
751 regulator_put(s_reg->regulator);
752 s_reg->regulator = NULL;
757 static const struct pinmux_ops sunxi_pmx_ops = {
758 .get_functions_count = sunxi_pmx_get_funcs_cnt,
759 .get_function_name = sunxi_pmx_get_func_name,
760 .get_function_groups = sunxi_pmx_get_func_groups,
761 .set_mux = sunxi_pmx_set_mux,
762 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
763 .request = sunxi_pmx_request,
764 .free = sunxi_pmx_free,
768 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
771 return pinctrl_gpio_direction_input(chip->base + offset);
774 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
776 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
777 u32 reg = sunxi_data_reg(offset);
778 u8 index = sunxi_data_offset(offset);
779 bool set_mux = pctl->desc->irq_read_needs_mux &&
780 gpiochip_line_is_irq(chip, offset);
781 u32 pin = offset + chip->base;
785 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
787 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
790 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
795 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
796 unsigned offset, int value)
798 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
799 u32 reg = sunxi_data_reg(offset);
800 u8 index = sunxi_data_offset(offset);
804 raw_spin_lock_irqsave(&pctl->lock, flags);
806 regval = readl(pctl->membase + reg);
809 regval |= BIT(index);
811 regval &= ~(BIT(index));
813 writel(regval, pctl->membase + reg);
815 raw_spin_unlock_irqrestore(&pctl->lock, flags);
818 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
819 unsigned offset, int value)
821 sunxi_pinctrl_gpio_set(chip, offset, value);
822 return pinctrl_gpio_direction_output(chip->base + offset);
825 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
826 const struct of_phandle_args *gpiospec,
831 base = PINS_PER_BANK * gpiospec->args[0];
832 pin = base + gpiospec->args[1];
838 *flags = gpiospec->args[2];
843 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
845 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
846 struct sunxi_desc_function *desc;
847 unsigned pinnum = pctl->desc->pin_base + offset;
850 if (offset >= chip->ngpio)
853 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
857 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
859 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
860 chip->label, offset + chip->base, irqnum);
862 return irq_find_mapping(pctl->domain, irqnum);
865 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
867 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
868 struct sunxi_desc_function *func;
871 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
872 pctl->irq_array[d->hwirq], "irq");
876 ret = gpiochip_lock_as_irq(pctl->chip,
877 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
879 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
884 /* Change muxing to INT mode */
885 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
890 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
892 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
894 gpiochip_unlock_as_irq(pctl->chip,
895 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
898 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
900 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
901 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
902 u8 index = sunxi_irq_cfg_offset(d->hwirq);
908 case IRQ_TYPE_EDGE_RISING:
909 mode = IRQ_EDGE_RISING;
911 case IRQ_TYPE_EDGE_FALLING:
912 mode = IRQ_EDGE_FALLING;
914 case IRQ_TYPE_EDGE_BOTH:
915 mode = IRQ_EDGE_BOTH;
917 case IRQ_TYPE_LEVEL_HIGH:
918 mode = IRQ_LEVEL_HIGH;
920 case IRQ_TYPE_LEVEL_LOW:
921 mode = IRQ_LEVEL_LOW;
927 raw_spin_lock_irqsave(&pctl->lock, flags);
929 if (type & IRQ_TYPE_LEVEL_MASK)
930 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
931 handle_fasteoi_irq, NULL);
933 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
934 handle_edge_irq, NULL);
936 regval = readl(pctl->membase + reg);
937 regval &= ~(IRQ_CFG_IRQ_MASK << index);
938 writel(regval | (mode << index), pctl->membase + reg);
940 raw_spin_unlock_irqrestore(&pctl->lock, flags);
945 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
947 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
948 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
949 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
952 writel(1 << status_idx, pctl->membase + status_reg);
955 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
957 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
958 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
959 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
963 raw_spin_lock_irqsave(&pctl->lock, flags);
966 val = readl(pctl->membase + reg);
967 writel(val & ~(1 << idx), pctl->membase + reg);
969 raw_spin_unlock_irqrestore(&pctl->lock, flags);
972 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
974 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
975 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
976 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
980 raw_spin_lock_irqsave(&pctl->lock, flags);
983 val = readl(pctl->membase + reg);
984 writel(val | (1 << idx), pctl->membase + reg);
986 raw_spin_unlock_irqrestore(&pctl->lock, flags);
989 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
991 sunxi_pinctrl_irq_ack(d);
992 sunxi_pinctrl_irq_unmask(d);
995 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
996 .name = "sunxi_pio_edge",
997 .irq_ack = sunxi_pinctrl_irq_ack,
998 .irq_mask = sunxi_pinctrl_irq_mask,
999 .irq_unmask = sunxi_pinctrl_irq_unmask,
1000 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1001 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1002 .irq_set_type = sunxi_pinctrl_irq_set_type,
1003 .flags = IRQCHIP_SKIP_SET_WAKE,
1006 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1007 .name = "sunxi_pio_level",
1008 .irq_eoi = sunxi_pinctrl_irq_ack,
1009 .irq_mask = sunxi_pinctrl_irq_mask,
1010 .irq_unmask = sunxi_pinctrl_irq_unmask,
1011 /* Define irq_enable / disable to avoid spurious irqs for drivers
1012 * using these to suppress irqs while they clear the irq source */
1013 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
1014 .irq_disable = sunxi_pinctrl_irq_mask,
1015 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1016 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1017 .irq_set_type = sunxi_pinctrl_irq_set_type,
1018 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
1019 IRQCHIP_EOI_IF_HANDLED,
1022 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1023 struct device_node *node,
1025 unsigned int intsize,
1026 unsigned long *out_hwirq,
1027 unsigned int *out_type)
1029 struct sunxi_pinctrl *pctl = d->host_data;
1030 struct sunxi_desc_function *desc;
1036 base = PINS_PER_BANK * intspec[0];
1037 pin = pctl->desc->pin_base + base + intspec[1];
1039 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1043 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1044 *out_type = intspec[2];
1049 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1050 .xlate = sunxi_pinctrl_irq_of_xlate,
1053 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1055 unsigned int irq = irq_desc_get_irq(desc);
1056 struct irq_chip *chip = irq_desc_get_chip(desc);
1057 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1058 unsigned long bank, reg, val;
1060 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1061 if (irq == pctl->irq[bank])
1064 if (bank == pctl->desc->irq_banks)
1067 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1068 val = readl(pctl->membase + reg);
1073 chained_irq_enter(chip, desc);
1074 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1075 int pin_irq = irq_find_mapping(pctl->domain,
1076 bank * IRQ_PER_BANK + irqoffset);
1077 generic_handle_irq(pin_irq);
1079 chained_irq_exit(chip, desc);
1083 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1086 struct sunxi_pinctrl_function *func = pctl->functions;
1088 while (func->name) {
1089 /* function already there */
1090 if (strcmp(func->name, name) == 0) {
1105 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1107 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1114 * We assume that the number of groups is the number of pins
1115 * given in the data array.
1117 * This will not always be true, since some pins might not be
1118 * available in the current variant, but fortunately for us,
1119 * this means that the number of pins is the maximum group
1120 * number we will ever see.
1122 pctl->groups = devm_kcalloc(&pdev->dev,
1123 pctl->desc->npins, sizeof(*pctl->groups),
1128 for (i = 0; i < pctl->desc->npins; i++) {
1129 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1130 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1132 if (pin->variant && !(pctl->variant & pin->variant))
1135 group->name = pin->pin.name;
1136 group->pin = pin->pin.number;
1138 /* And now we count the actual number of pins / groups */
1143 * We suppose that we won't have any more functions than pins,
1144 * we'll reallocate that later anyway
1146 pctl->functions = kcalloc(pctl->ngroups,
1147 sizeof(*pctl->functions),
1149 if (!pctl->functions)
1152 /* Count functions and their associated groups */
1153 for (i = 0; i < pctl->desc->npins; i++) {
1154 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1155 struct sunxi_desc_function *func;
1157 if (pin->variant && !(pctl->variant & pin->variant))
1160 for (func = pin->functions; func->name; func++) {
1161 if (func->variant && !(pctl->variant & func->variant))
1164 /* Create interrupt mapping while we're at it */
1165 if (!strcmp(func->name, "irq")) {
1166 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1167 pctl->irq_array[irqnum] = pin->pin.number;
1170 sunxi_pinctrl_add_function(pctl, func->name);
1174 /* And now allocated and fill the array for real */
1175 ptr = krealloc(pctl->functions,
1176 pctl->nfunctions * sizeof(*pctl->functions),
1179 kfree(pctl->functions);
1180 pctl->functions = NULL;
1183 pctl->functions = ptr;
1185 for (i = 0; i < pctl->desc->npins; i++) {
1186 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1187 struct sunxi_desc_function *func;
1189 if (pin->variant && !(pctl->variant & pin->variant))
1192 for (func = pin->functions; func->name; func++) {
1193 struct sunxi_pinctrl_function *func_item;
1194 const char **func_grp;
1196 if (func->variant && !(pctl->variant & func->variant))
1199 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1202 kfree(pctl->functions);
1206 if (!func_item->groups) {
1208 devm_kcalloc(&pdev->dev,
1210 sizeof(*func_item->groups),
1212 if (!func_item->groups) {
1213 kfree(pctl->functions);
1218 func_grp = func_item->groups;
1222 *func_grp = pin->pin.name;
1229 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1231 unsigned long clock = clk_get_rate(clk);
1232 unsigned int best_diff, best_div;
1235 best_diff = abs(freq - clock);
1238 for (i = 1; i < 8; i++) {
1239 int cur_diff = abs(freq - (clock >> i));
1241 if (cur_diff < best_diff) {
1242 best_diff = cur_diff;
1251 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1252 struct device_node *node)
1254 unsigned int hosc_diff, losc_diff;
1255 unsigned int hosc_div, losc_div;
1256 struct clk *hosc, *losc;
1260 /* Deal with old DTs that didn't have the oscillators */
1261 if (of_clk_get_parent_count(node) != 3)
1264 /* If we don't have any setup, bail out */
1265 if (!of_find_property(node, "input-debounce", NULL))
1268 losc = devm_clk_get(pctl->dev, "losc");
1270 return PTR_ERR(losc);
1272 hosc = devm_clk_get(pctl->dev, "hosc");
1274 return PTR_ERR(hosc);
1276 for (i = 0; i < pctl->desc->irq_banks; i++) {
1277 unsigned long debounce_freq;
1280 ret = of_property_read_u32_index(node, "input-debounce",
1288 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1289 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1293 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1297 if (hosc_diff < losc_diff) {
1305 writel(src | div << 4,
1307 sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1313 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1314 const struct sunxi_pinctrl_desc *desc,
1315 unsigned long variant)
1317 struct device_node *node = pdev->dev.of_node;
1318 struct pinctrl_desc *pctrl_desc;
1319 struct pinctrl_pin_desc *pins;
1320 struct sunxi_pinctrl *pctl;
1321 struct pinmux_ops *pmxops;
1322 struct resource *res;
1323 int i, ret, last_pin, pin_idx;
1326 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1329 platform_set_drvdata(pdev, pctl);
1331 raw_spin_lock_init(&pctl->lock);
1333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1334 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
1335 if (IS_ERR(pctl->membase))
1336 return PTR_ERR(pctl->membase);
1338 pctl->dev = &pdev->dev;
1340 pctl->variant = variant;
1342 pctl->irq_array = devm_kcalloc(&pdev->dev,
1343 IRQ_PER_BANK * pctl->desc->irq_banks,
1344 sizeof(*pctl->irq_array),
1346 if (!pctl->irq_array)
1349 ret = sunxi_pinctrl_build_state(pdev);
1351 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1355 pins = devm_kcalloc(&pdev->dev,
1356 pctl->desc->npins, sizeof(*pins),
1361 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1362 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1364 if (pin->variant && !(pctl->variant & pin->variant))
1367 pins[pin_idx++] = pin->pin;
1370 pctrl_desc = devm_kzalloc(&pdev->dev,
1371 sizeof(*pctrl_desc),
1376 pctrl_desc->name = dev_name(&pdev->dev);
1377 pctrl_desc->owner = THIS_MODULE;
1378 pctrl_desc->pins = pins;
1379 pctrl_desc->npins = pctl->ngroups;
1380 pctrl_desc->confops = &sunxi_pconf_ops;
1381 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1383 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1388 if (desc->disable_strict_mode)
1389 pmxops->strict = false;
1391 pctrl_desc->pmxops = pmxops;
1393 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1394 if (IS_ERR(pctl->pctl_dev)) {
1395 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1396 return PTR_ERR(pctl->pctl_dev);
1399 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1403 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1404 pctl->chip->owner = THIS_MODULE;
1405 pctl->chip->request = gpiochip_generic_request,
1406 pctl->chip->free = gpiochip_generic_free,
1407 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
1408 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
1409 pctl->chip->get = sunxi_pinctrl_gpio_get,
1410 pctl->chip->set = sunxi_pinctrl_gpio_set,
1411 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
1412 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
1413 pctl->chip->of_gpio_n_cells = 3,
1414 pctl->chip->can_sleep = false,
1415 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1416 pctl->desc->pin_base;
1417 pctl->chip->label = dev_name(&pdev->dev);
1418 pctl->chip->parent = &pdev->dev;
1419 pctl->chip->base = pctl->desc->pin_base;
1421 ret = gpiochip_add_data(pctl->chip, pctl);
1425 for (i = 0; i < pctl->desc->npins; i++) {
1426 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1428 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1429 pin->pin.number - pctl->desc->pin_base,
1430 pin->pin.number, 1);
1432 goto gpiochip_error;
1435 ret = of_clk_get_parent_count(node);
1436 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1439 goto gpiochip_error;
1442 ret = clk_prepare_enable(clk);
1444 goto gpiochip_error;
1446 pctl->irq = devm_kcalloc(&pdev->dev,
1447 pctl->desc->irq_banks,
1455 for (i = 0; i < pctl->desc->irq_banks; i++) {
1456 pctl->irq[i] = platform_get_irq(pdev, i);
1457 if (pctl->irq[i] < 0) {
1463 pctl->domain = irq_domain_add_linear(node,
1464 pctl->desc->irq_banks * IRQ_PER_BANK,
1465 &sunxi_pinctrl_irq_domain_ops,
1467 if (!pctl->domain) {
1468 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1473 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1474 int irqno = irq_create_mapping(pctl->domain, i);
1476 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1478 irq_set_chip_data(irqno, pctl);
1481 for (i = 0; i < pctl->desc->irq_banks; i++) {
1482 /* Mask and clear all IRQs before registering a handler */
1483 writel(0, pctl->membase +
1484 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1487 sunxi_irq_status_reg_from_bank(pctl->desc, i));
1489 irq_set_chained_handler_and_data(pctl->irq[i],
1490 sunxi_pinctrl_irq_handler,
1494 sunxi_pinctrl_setup_debounce(pctl, node);
1496 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1501 clk_disable_unprepare(clk);
1503 gpiochip_remove(pctl->chip);