Merge tag 'sound-5.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[linux-2.6-microblaze.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.c
1 /*
2  * Allwinner A1X SoCs pinctrl driver.
3  *
4  * Copyright (C) 2012 Maxime Ripard
5  *
6  * Maxime Ripard <maxime.ripard@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12
13 #include <linux/io.h>
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqdomain.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/export.h>
20 #include <linux/of.h>
21 #include <linux/of_clk.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33
34 #include <dt-bindings/pinctrl/sun4i-a10.h>
35
36 #include "../core.h"
37 #include "pinctrl-sunxi.h"
38
39 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
40 static struct irq_chip sunxi_pinctrl_level_irq_chip;
41
42 static struct sunxi_pinctrl_group *
43 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
44 {
45         int i;
46
47         for (i = 0; i < pctl->ngroups; i++) {
48                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
49
50                 if (!strcmp(grp->name, group))
51                         return grp;
52         }
53
54         return NULL;
55 }
56
57 static struct sunxi_pinctrl_function *
58 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
59                                     const char *name)
60 {
61         struct sunxi_pinctrl_function *func = pctl->functions;
62         int i;
63
64         for (i = 0; i < pctl->nfunctions; i++) {
65                 if (!func[i].name)
66                         break;
67
68                 if (!strcmp(func[i].name, name))
69                         return func + i;
70         }
71
72         return NULL;
73 }
74
75 static struct sunxi_desc_function *
76 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
77                                          const char *pin_name,
78                                          const char *func_name)
79 {
80         int i;
81
82         for (i = 0; i < pctl->desc->npins; i++) {
83                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
84
85                 if (!strcmp(pin->pin.name, pin_name)) {
86                         struct sunxi_desc_function *func = pin->functions;
87
88                         while (func->name) {
89                                 if (!strcmp(func->name, func_name) &&
90                                         (!func->variant ||
91                                         func->variant & pctl->variant))
92                                         return func;
93
94                                 func++;
95                         }
96                 }
97         }
98
99         return NULL;
100 }
101
102 static struct sunxi_desc_function *
103 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
104                                         const u16 pin_num,
105                                         const char *func_name)
106 {
107         int i;
108
109         for (i = 0; i < pctl->desc->npins; i++) {
110                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
111
112                 if (pin->pin.number == pin_num) {
113                         struct sunxi_desc_function *func = pin->functions;
114
115                         while (func->name) {
116                                 if (!strcmp(func->name, func_name))
117                                         return func;
118
119                                 func++;
120                         }
121                 }
122         }
123
124         return NULL;
125 }
126
127 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
128 {
129         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
130
131         return pctl->ngroups;
132 }
133
134 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
135                                               unsigned group)
136 {
137         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138
139         return pctl->groups[group].name;
140 }
141
142 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
143                                       unsigned group,
144                                       const unsigned **pins,
145                                       unsigned *num_pins)
146 {
147         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
148
149         *pins = (unsigned *)&pctl->groups[group].pin;
150         *num_pins = 1;
151
152         return 0;
153 }
154
155 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
156 {
157         return of_find_property(node, "bias-pull-up", NULL) ||
158                 of_find_property(node, "bias-pull-down", NULL) ||
159                 of_find_property(node, "bias-disable", NULL) ||
160                 of_find_property(node, "allwinner,pull", NULL);
161 }
162
163 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
164 {
165         return of_find_property(node, "drive-strength", NULL) ||
166                 of_find_property(node, "allwinner,drive", NULL);
167 }
168
169 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
170 {
171         u32 val;
172
173         /* Try the new style binding */
174         if (of_find_property(node, "bias-pull-up", NULL))
175                 return PIN_CONFIG_BIAS_PULL_UP;
176
177         if (of_find_property(node, "bias-pull-down", NULL))
178                 return PIN_CONFIG_BIAS_PULL_DOWN;
179
180         if (of_find_property(node, "bias-disable", NULL))
181                 return PIN_CONFIG_BIAS_DISABLE;
182
183         /* And fall back to the old binding */
184         if (of_property_read_u32(node, "allwinner,pull", &val))
185                 return -EINVAL;
186
187         switch (val) {
188         case SUN4I_PINCTRL_NO_PULL:
189                 return PIN_CONFIG_BIAS_DISABLE;
190         case SUN4I_PINCTRL_PULL_UP:
191                 return PIN_CONFIG_BIAS_PULL_UP;
192         case SUN4I_PINCTRL_PULL_DOWN:
193                 return PIN_CONFIG_BIAS_PULL_DOWN;
194         }
195
196         return -EINVAL;
197 }
198
199 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
200 {
201         u32 val;
202
203         /* Try the new style binding */
204         if (!of_property_read_u32(node, "drive-strength", &val)) {
205                 /* We can't go below 10mA ... */
206                 if (val < 10)
207                         return -EINVAL;
208
209                 /* ... and only up to 40 mA ... */
210                 if (val > 40)
211                         val = 40;
212
213                 /* by steps of 10 mA */
214                 return rounddown(val, 10);
215         }
216
217         /* And then fall back to the old binding */
218         if (of_property_read_u32(node, "allwinner,drive", &val))
219                 return -EINVAL;
220
221         return (val + 1) * 10;
222 }
223
224 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
225 {
226         const char *function;
227         int ret;
228
229         /* Try the generic binding */
230         ret = of_property_read_string(node, "function", &function);
231         if (!ret)
232                 return function;
233
234         /* And fall back to our legacy one */
235         ret = of_property_read_string(node, "allwinner,function", &function);
236         if (!ret)
237                 return function;
238
239         return NULL;
240 }
241
242 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
243                                               int *npins)
244 {
245         int count;
246
247         /* Try the generic binding */
248         count = of_property_count_strings(node, "pins");
249         if (count > 0) {
250                 *npins = count;
251                 return "pins";
252         }
253
254         /* And fall back to our legacy one */
255         count = of_property_count_strings(node, "allwinner,pins");
256         if (count > 0) {
257                 *npins = count;
258                 return "allwinner,pins";
259         }
260
261         return NULL;
262 }
263
264 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
265                                                    unsigned int *len)
266 {
267         unsigned long *pinconfig;
268         unsigned int configlen = 0, idx = 0;
269         int ret;
270
271         if (sunxi_pctrl_has_drive_prop(node))
272                 configlen++;
273         if (sunxi_pctrl_has_bias_prop(node))
274                 configlen++;
275
276         /*
277          * If we don't have any configuration, bail out
278          */
279         if (!configlen)
280                 return NULL;
281
282         pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
283         if (!pinconfig)
284                 return ERR_PTR(-ENOMEM);
285
286         if (sunxi_pctrl_has_drive_prop(node)) {
287                 int drive = sunxi_pctrl_parse_drive_prop(node);
288                 if (drive < 0) {
289                         ret = drive;
290                         goto err_free;
291                 }
292
293                 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
294                                                           drive);
295         }
296
297         if (sunxi_pctrl_has_bias_prop(node)) {
298                 int pull = sunxi_pctrl_parse_bias_prop(node);
299                 int arg = 0;
300                 if (pull < 0) {
301                         ret = pull;
302                         goto err_free;
303                 }
304
305                 if (pull != PIN_CONFIG_BIAS_DISABLE)
306                         arg = 1; /* hardware uses weak pull resistors */
307
308                 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
309         }
310
311
312         *len = configlen;
313         return pinconfig;
314
315 err_free:
316         kfree(pinconfig);
317         return ERR_PTR(ret);
318 }
319
320 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
321                                       struct device_node *node,
322                                       struct pinctrl_map **map,
323                                       unsigned *num_maps)
324 {
325         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
326         unsigned long *pinconfig;
327         struct property *prop;
328         const char *function, *pin_prop;
329         const char *group;
330         int ret, npins, nmaps, configlen = 0, i = 0;
331
332         *map = NULL;
333         *num_maps = 0;
334
335         function = sunxi_pctrl_parse_function_prop(node);
336         if (!function) {
337                 dev_err(pctl->dev, "missing function property in node %pOFn\n",
338                         node);
339                 return -EINVAL;
340         }
341
342         pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
343         if (!pin_prop) {
344                 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
345                         node);
346                 return -EINVAL;
347         }
348
349         /*
350          * We have two maps for each pin: one for the function, one
351          * for the configuration (bias, strength, etc).
352          *
353          * We might be slightly overshooting, since we might not have
354          * any configuration.
355          */
356         nmaps = npins * 2;
357         *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
358         if (!*map)
359                 return -ENOMEM;
360
361         pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
362         if (IS_ERR(pinconfig)) {
363                 ret = PTR_ERR(pinconfig);
364                 goto err_free_map;
365         }
366
367         of_property_for_each_string(node, pin_prop, prop, group) {
368                 struct sunxi_pinctrl_group *grp =
369                         sunxi_pinctrl_find_group_by_name(pctl, group);
370
371                 if (!grp) {
372                         dev_err(pctl->dev, "unknown pin %s", group);
373                         continue;
374                 }
375
376                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
377                                                               grp->name,
378                                                               function)) {
379                         dev_err(pctl->dev, "unsupported function %s on pin %s",
380                                 function, group);
381                         continue;
382                 }
383
384                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
385                 (*map)[i].data.mux.group = group;
386                 (*map)[i].data.mux.function = function;
387
388                 i++;
389
390                 if (pinconfig) {
391                         (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
392                         (*map)[i].data.configs.group_or_pin = group;
393                         (*map)[i].data.configs.configs = pinconfig;
394                         (*map)[i].data.configs.num_configs = configlen;
395                         i++;
396                 }
397         }
398
399         *num_maps = i;
400
401         /*
402          * We know have the number of maps we need, we can resize our
403          * map array
404          */
405         *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
406         if (!*map)
407                 return -ENOMEM;
408
409         return 0;
410
411 err_free_map:
412         kfree(*map);
413         *map = NULL;
414         return ret;
415 }
416
417 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
418                                     struct pinctrl_map *map,
419                                     unsigned num_maps)
420 {
421         int i;
422
423         /* pin config is never in the first map */
424         for (i = 1; i < num_maps; i++) {
425                 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
426                         continue;
427
428                 /*
429                  * All the maps share the same pin config,
430                  * free only the first one we find.
431                  */
432                 kfree(map[i].data.configs.configs);
433                 break;
434         }
435
436         kfree(map);
437 }
438
439 static const struct pinctrl_ops sunxi_pctrl_ops = {
440         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
441         .dt_free_map            = sunxi_pctrl_dt_free_map,
442         .get_groups_count       = sunxi_pctrl_get_groups_count,
443         .get_group_name         = sunxi_pctrl_get_group_name,
444         .get_group_pins         = sunxi_pctrl_get_group_pins,
445 };
446
447 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
448                            u32 *offset, u32 *shift, u32 *mask)
449 {
450         switch (param) {
451         case PIN_CONFIG_DRIVE_STRENGTH:
452                 *offset = sunxi_dlevel_reg(pin);
453                 *shift = sunxi_dlevel_offset(pin);
454                 *mask = DLEVEL_PINS_MASK;
455                 break;
456
457         case PIN_CONFIG_BIAS_PULL_UP:
458         case PIN_CONFIG_BIAS_PULL_DOWN:
459         case PIN_CONFIG_BIAS_DISABLE:
460                 *offset = sunxi_pull_reg(pin);
461                 *shift = sunxi_pull_offset(pin);
462                 *mask = PULL_PINS_MASK;
463                 break;
464
465         default:
466                 return -ENOTSUPP;
467         }
468
469         return 0;
470 }
471
472 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
473                            unsigned long *config)
474 {
475         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
476         enum pin_config_param param = pinconf_to_config_param(*config);
477         u32 offset, shift, mask, val;
478         u16 arg;
479         int ret;
480
481         pin -= pctl->desc->pin_base;
482
483         ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
484         if (ret < 0)
485                 return ret;
486
487         val = (readl(pctl->membase + offset) >> shift) & mask;
488
489         switch (pinconf_to_config_param(*config)) {
490         case PIN_CONFIG_DRIVE_STRENGTH:
491                 arg = (val + 1) * 10;
492                 break;
493
494         case PIN_CONFIG_BIAS_PULL_UP:
495                 if (val != SUN4I_PINCTRL_PULL_UP)
496                         return -EINVAL;
497                 arg = 1; /* hardware is weak pull-up */
498                 break;
499
500         case PIN_CONFIG_BIAS_PULL_DOWN:
501                 if (val != SUN4I_PINCTRL_PULL_DOWN)
502                         return -EINVAL;
503                 arg = 1; /* hardware is weak pull-down */
504                 break;
505
506         case PIN_CONFIG_BIAS_DISABLE:
507                 if (val != SUN4I_PINCTRL_NO_PULL)
508                         return -EINVAL;
509                 arg = 0;
510                 break;
511
512         default:
513                 /* sunxi_pconf_reg should catch anything unsupported */
514                 WARN_ON(1);
515                 return -ENOTSUPP;
516         }
517
518         *config = pinconf_to_config_packed(param, arg);
519
520         return 0;
521 }
522
523 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
524                                  unsigned group,
525                                  unsigned long *config)
526 {
527         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
528         struct sunxi_pinctrl_group *g = &pctl->groups[group];
529
530         /* We only support 1 pin per group. Chain it to the pin callback */
531         return sunxi_pconf_get(pctldev, g->pin, config);
532 }
533
534 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
535                            unsigned long *configs, unsigned num_configs)
536 {
537         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
538         int i;
539
540         for (i = 0; i < num_configs; i++) {
541                 enum pin_config_param param;
542                 unsigned long flags;
543                 u32 offset, shift, mask, reg;
544                 u32 arg, val;
545                 int ret;
546
547                 param = pinconf_to_config_param(configs[i]);
548                 arg = pinconf_to_config_argument(configs[i]);
549
550                 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
551                 if (ret < 0)
552                         return ret;
553
554                 switch (param) {
555                 case PIN_CONFIG_DRIVE_STRENGTH:
556                         if (arg < 10 || arg > 40)
557                                 return -EINVAL;
558                         /*
559                          * We convert from mA to what the register expects:
560                          *   0: 10mA
561                          *   1: 20mA
562                          *   2: 30mA
563                          *   3: 40mA
564                          */
565                         val = arg / 10 - 1;
566                         break;
567                 case PIN_CONFIG_BIAS_DISABLE:
568                         val = 0;
569                         break;
570                 case PIN_CONFIG_BIAS_PULL_UP:
571                         if (arg == 0)
572                                 return -EINVAL;
573                         val = 1;
574                         break;
575                 case PIN_CONFIG_BIAS_PULL_DOWN:
576                         if (arg == 0)
577                                 return -EINVAL;
578                         val = 2;
579                         break;
580                 default:
581                         /* sunxi_pconf_reg should catch anything unsupported */
582                         WARN_ON(1);
583                         return -ENOTSUPP;
584                 }
585
586                 raw_spin_lock_irqsave(&pctl->lock, flags);
587                 reg = readl(pctl->membase + offset);
588                 reg &= ~(mask << shift);
589                 writel(reg | val << shift, pctl->membase + offset);
590                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
591         } /* for each config */
592
593         return 0;
594 }
595
596 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
597                                  unsigned long *configs, unsigned num_configs)
598 {
599         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
600         struct sunxi_pinctrl_group *g = &pctl->groups[group];
601
602         /* We only support 1 pin per group. Chain it to the pin callback */
603         return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
604 }
605
606 static const struct pinconf_ops sunxi_pconf_ops = {
607         .is_generic             = true,
608         .pin_config_get         = sunxi_pconf_get,
609         .pin_config_set         = sunxi_pconf_set,
610         .pin_config_group_get   = sunxi_pconf_group_get,
611         .pin_config_group_set   = sunxi_pconf_group_set,
612 };
613
614 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
615                                          unsigned pin,
616                                          struct regulator *supply)
617 {
618         unsigned short bank = pin / PINS_PER_BANK;
619         unsigned long flags;
620         u32 val, reg;
621         int uV;
622
623         if (!pctl->desc->io_bias_cfg_variant)
624                 return 0;
625
626         uV = regulator_get_voltage(supply);
627         if (uV < 0)
628                 return uV;
629
630         /* Might be dummy regulator with no voltage set */
631         if (uV == 0)
632                 return 0;
633
634         switch (pctl->desc->io_bias_cfg_variant) {
635         case BIAS_VOLTAGE_GRP_CONFIG:
636                 /*
637                  * Configured value must be equal or greater to actual
638                  * voltage.
639                  */
640                 if (uV <= 1800000)
641                         val = 0x0; /* 1.8V */
642                 else if (uV <= 2500000)
643                         val = 0x6; /* 2.5V */
644                 else if (uV <= 2800000)
645                         val = 0x9; /* 2.8V */
646                 else if (uV <= 3000000)
647                         val = 0xA; /* 3.0V */
648                 else
649                         val = 0xD; /* 3.3V */
650
651                 pin -= pctl->desc->pin_base;
652
653                 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
654                 reg &= ~IO_BIAS_MASK;
655                 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
656                 return 0;
657         case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
658                 val = uV <= 1800000 ? 1 : 0;
659
660                 raw_spin_lock_irqsave(&pctl->lock, flags);
661                 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
662                 reg &= ~(1 << bank);
663                 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
664                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
665                 return 0;
666         default:
667                 return -EINVAL;
668         }
669 }
670
671 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
672 {
673         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
674
675         return pctl->nfunctions;
676 }
677
678 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
679                                            unsigned function)
680 {
681         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
682
683         return pctl->functions[function].name;
684 }
685
686 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
687                                      unsigned function,
688                                      const char * const **groups,
689                                      unsigned * const num_groups)
690 {
691         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
692
693         *groups = pctl->functions[function].groups;
694         *num_groups = pctl->functions[function].ngroups;
695
696         return 0;
697 }
698
699 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
700                                  unsigned pin,
701                                  u8 config)
702 {
703         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
704         unsigned long flags;
705         u32 val, mask;
706
707         raw_spin_lock_irqsave(&pctl->lock, flags);
708
709         pin -= pctl->desc->pin_base;
710         val = readl(pctl->membase + sunxi_mux_reg(pin));
711         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
712         writel((val & ~mask) | config << sunxi_mux_offset(pin),
713                 pctl->membase + sunxi_mux_reg(pin));
714
715         raw_spin_unlock_irqrestore(&pctl->lock, flags);
716 }
717
718 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
719                              unsigned function,
720                              unsigned group)
721 {
722         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
723         struct sunxi_pinctrl_group *g = pctl->groups + group;
724         struct sunxi_pinctrl_function *func = pctl->functions + function;
725         struct sunxi_desc_function *desc =
726                 sunxi_pinctrl_desc_find_function_by_name(pctl,
727                                                          g->name,
728                                                          func->name);
729
730         if (!desc)
731                 return -EINVAL;
732
733         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
734
735         return 0;
736 }
737
738 static int
739 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
740                         struct pinctrl_gpio_range *range,
741                         unsigned offset,
742                         bool input)
743 {
744         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
745         struct sunxi_desc_function *desc;
746         const char *func;
747
748         if (input)
749                 func = "gpio_in";
750         else
751                 func = "gpio_out";
752
753         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
754         if (!desc)
755                 return -EINVAL;
756
757         sunxi_pmx_set(pctldev, offset, desc->muxval);
758
759         return 0;
760 }
761
762 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
763 {
764         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
765         unsigned short bank = offset / PINS_PER_BANK;
766         unsigned short bank_offset = bank - pctl->desc->pin_base /
767                                             PINS_PER_BANK;
768         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
769         struct regulator *reg = s_reg->regulator;
770         char supply[16];
771         int ret;
772
773         if (reg) {
774                 refcount_inc(&s_reg->refcount);
775                 return 0;
776         }
777
778         snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
779         reg = regulator_get(pctl->dev, supply);
780         if (IS_ERR(reg)) {
781                 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
782                         'A' + bank);
783                 return PTR_ERR(reg);
784         }
785
786         ret = regulator_enable(reg);
787         if (ret) {
788                 dev_err(pctl->dev,
789                         "Couldn't enable bank P%c regulator\n", 'A' + bank);
790                 goto out;
791         }
792
793         sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
794
795         s_reg->regulator = reg;
796         refcount_set(&s_reg->refcount, 1);
797
798         return 0;
799
800 out:
801         regulator_put(s_reg->regulator);
802
803         return ret;
804 }
805
806 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
807 {
808         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
809         unsigned short bank = offset / PINS_PER_BANK;
810         unsigned short bank_offset = bank - pctl->desc->pin_base /
811                                             PINS_PER_BANK;
812         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
813
814         if (!refcount_dec_and_test(&s_reg->refcount))
815                 return 0;
816
817         regulator_disable(s_reg->regulator);
818         regulator_put(s_reg->regulator);
819         s_reg->regulator = NULL;
820
821         return 0;
822 }
823
824 static const struct pinmux_ops sunxi_pmx_ops = {
825         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
826         .get_function_name      = sunxi_pmx_get_func_name,
827         .get_function_groups    = sunxi_pmx_get_func_groups,
828         .set_mux                = sunxi_pmx_set_mux,
829         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
830         .request                = sunxi_pmx_request,
831         .free                   = sunxi_pmx_free,
832         .strict                 = true,
833 };
834
835 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
836                                         unsigned offset)
837 {
838         return pinctrl_gpio_direction_input(chip->base + offset);
839 }
840
841 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
842 {
843         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
844         u32 reg = sunxi_data_reg(offset);
845         u8 index = sunxi_data_offset(offset);
846         bool set_mux = pctl->desc->irq_read_needs_mux &&
847                 gpiochip_line_is_irq(chip, offset);
848         u32 pin = offset + chip->base;
849         u32 val;
850
851         if (set_mux)
852                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
853
854         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
855
856         if (set_mux)
857                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
858
859         return !!val;
860 }
861
862 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
863                                 unsigned offset, int value)
864 {
865         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
866         u32 reg = sunxi_data_reg(offset);
867         u8 index = sunxi_data_offset(offset);
868         unsigned long flags;
869         u32 regval;
870
871         raw_spin_lock_irqsave(&pctl->lock, flags);
872
873         regval = readl(pctl->membase + reg);
874
875         if (value)
876                 regval |= BIT(index);
877         else
878                 regval &= ~(BIT(index));
879
880         writel(regval, pctl->membase + reg);
881
882         raw_spin_unlock_irqrestore(&pctl->lock, flags);
883 }
884
885 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
886                                         unsigned offset, int value)
887 {
888         sunxi_pinctrl_gpio_set(chip, offset, value);
889         return pinctrl_gpio_direction_output(chip->base + offset);
890 }
891
892 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
893                                 const struct of_phandle_args *gpiospec,
894                                 u32 *flags)
895 {
896         int pin, base;
897
898         base = PINS_PER_BANK * gpiospec->args[0];
899         pin = base + gpiospec->args[1];
900
901         if (pin > gc->ngpio)
902                 return -EINVAL;
903
904         if (flags)
905                 *flags = gpiospec->args[2];
906
907         return pin;
908 }
909
910 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
911 {
912         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
913         struct sunxi_desc_function *desc;
914         unsigned pinnum = pctl->desc->pin_base + offset;
915         unsigned irqnum;
916
917         if (offset >= chip->ngpio)
918                 return -ENXIO;
919
920         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
921         if (!desc)
922                 return -EINVAL;
923
924         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
925
926         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
927                 chip->label, offset + chip->base, irqnum);
928
929         return irq_find_mapping(pctl->domain, irqnum);
930 }
931
932 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
933 {
934         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
935         struct sunxi_desc_function *func;
936         int ret;
937
938         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
939                                         pctl->irq_array[d->hwirq], "irq");
940         if (!func)
941                 return -EINVAL;
942
943         ret = gpiochip_lock_as_irq(pctl->chip,
944                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
945         if (ret) {
946                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
947                         irqd_to_hwirq(d));
948                 return ret;
949         }
950
951         /* Change muxing to INT mode */
952         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
953
954         return 0;
955 }
956
957 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
958 {
959         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
960
961         gpiochip_unlock_as_irq(pctl->chip,
962                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
963 }
964
965 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
966 {
967         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
968         u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
969         u8 index = sunxi_irq_cfg_offset(d->hwirq);
970         unsigned long flags;
971         u32 regval;
972         u8 mode;
973
974         switch (type) {
975         case IRQ_TYPE_EDGE_RISING:
976                 mode = IRQ_EDGE_RISING;
977                 break;
978         case IRQ_TYPE_EDGE_FALLING:
979                 mode = IRQ_EDGE_FALLING;
980                 break;
981         case IRQ_TYPE_EDGE_BOTH:
982                 mode = IRQ_EDGE_BOTH;
983                 break;
984         case IRQ_TYPE_LEVEL_HIGH:
985                 mode = IRQ_LEVEL_HIGH;
986                 break;
987         case IRQ_TYPE_LEVEL_LOW:
988                 mode = IRQ_LEVEL_LOW;
989                 break;
990         default:
991                 return -EINVAL;
992         }
993
994         raw_spin_lock_irqsave(&pctl->lock, flags);
995
996         if (type & IRQ_TYPE_LEVEL_MASK)
997                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
998                                                  handle_fasteoi_irq, NULL);
999         else
1000                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1001                                                  handle_edge_irq, NULL);
1002
1003         regval = readl(pctl->membase + reg);
1004         regval &= ~(IRQ_CFG_IRQ_MASK << index);
1005         writel(regval | (mode << index), pctl->membase + reg);
1006
1007         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1008
1009         return 0;
1010 }
1011
1012 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1013 {
1014         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1015         u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1016         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1017
1018         /* Clear the IRQ */
1019         writel(1 << status_idx, pctl->membase + status_reg);
1020 }
1021
1022 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1023 {
1024         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1025         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1026         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1027         unsigned long flags;
1028         u32 val;
1029
1030         raw_spin_lock_irqsave(&pctl->lock, flags);
1031
1032         /* Mask the IRQ */
1033         val = readl(pctl->membase + reg);
1034         writel(val & ~(1 << idx), pctl->membase + reg);
1035
1036         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1037 }
1038
1039 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1040 {
1041         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1042         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1043         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1044         unsigned long flags;
1045         u32 val;
1046
1047         raw_spin_lock_irqsave(&pctl->lock, flags);
1048
1049         /* Unmask the IRQ */
1050         val = readl(pctl->membase + reg);
1051         writel(val | (1 << idx), pctl->membase + reg);
1052
1053         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1054 }
1055
1056 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1057 {
1058         sunxi_pinctrl_irq_ack(d);
1059         sunxi_pinctrl_irq_unmask(d);
1060 }
1061
1062 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1063 {
1064         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1065         u8 bank = d->hwirq / IRQ_PER_BANK;
1066
1067         return irq_set_irq_wake(pctl->irq[bank], on);
1068 }
1069
1070 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1071         .name           = "sunxi_pio_edge",
1072         .irq_ack        = sunxi_pinctrl_irq_ack,
1073         .irq_mask       = sunxi_pinctrl_irq_mask,
1074         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1075         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1076         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1077         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1078         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1079         .flags          = IRQCHIP_MASK_ON_SUSPEND,
1080 };
1081
1082 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1083         .name           = "sunxi_pio_level",
1084         .irq_eoi        = sunxi_pinctrl_irq_ack,
1085         .irq_mask       = sunxi_pinctrl_irq_mask,
1086         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1087         /* Define irq_enable / disable to avoid spurious irqs for drivers
1088          * using these to suppress irqs while they clear the irq source */
1089         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
1090         .irq_disable    = sunxi_pinctrl_irq_mask,
1091         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1092         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1093         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1094         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1095         .flags          = IRQCHIP_EOI_THREADED |
1096                           IRQCHIP_MASK_ON_SUSPEND |
1097                           IRQCHIP_EOI_IF_HANDLED,
1098 };
1099
1100 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1101                                       struct device_node *node,
1102                                       const u32 *intspec,
1103                                       unsigned int intsize,
1104                                       unsigned long *out_hwirq,
1105                                       unsigned int *out_type)
1106 {
1107         struct sunxi_pinctrl *pctl = d->host_data;
1108         struct sunxi_desc_function *desc;
1109         int pin, base;
1110
1111         if (intsize < 3)
1112                 return -EINVAL;
1113
1114         base = PINS_PER_BANK * intspec[0];
1115         pin = pctl->desc->pin_base + base + intspec[1];
1116
1117         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1118         if (!desc)
1119                 return -EINVAL;
1120
1121         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1122         *out_type = intspec[2];
1123
1124         return 0;
1125 }
1126
1127 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1128         .xlate          = sunxi_pinctrl_irq_of_xlate,
1129 };
1130
1131 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1132 {
1133         unsigned int irq = irq_desc_get_irq(desc);
1134         struct irq_chip *chip = irq_desc_get_chip(desc);
1135         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1136         unsigned long bank, reg, val;
1137
1138         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1139                 if (irq == pctl->irq[bank])
1140                         break;
1141
1142         if (bank == pctl->desc->irq_banks)
1143                 return;
1144
1145         reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1146         val = readl(pctl->membase + reg);
1147
1148         if (val) {
1149                 int irqoffset;
1150
1151                 chained_irq_enter(chip, desc);
1152                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1153                         int pin_irq = irq_find_mapping(pctl->domain,
1154                                                        bank * IRQ_PER_BANK + irqoffset);
1155                         generic_handle_irq(pin_irq);
1156                 }
1157                 chained_irq_exit(chip, desc);
1158         }
1159 }
1160
1161 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1162                                         const char *name)
1163 {
1164         struct sunxi_pinctrl_function *func = pctl->functions;
1165
1166         while (func->name) {
1167                 /* function already there */
1168                 if (strcmp(func->name, name) == 0) {
1169                         func->ngroups++;
1170                         return -EEXIST;
1171                 }
1172                 func++;
1173         }
1174
1175         func->name = name;
1176         func->ngroups = 1;
1177
1178         pctl->nfunctions++;
1179
1180         return 0;
1181 }
1182
1183 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1184 {
1185         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1186         void *ptr;
1187         int i;
1188
1189         /*
1190          * Allocate groups
1191          *
1192          * We assume that the number of groups is the number of pins
1193          * given in the data array.
1194
1195          * This will not always be true, since some pins might not be
1196          * available in the current variant, but fortunately for us,
1197          * this means that the number of pins is the maximum group
1198          * number we will ever see.
1199          */
1200         pctl->groups = devm_kcalloc(&pdev->dev,
1201                                     pctl->desc->npins, sizeof(*pctl->groups),
1202                                     GFP_KERNEL);
1203         if (!pctl->groups)
1204                 return -ENOMEM;
1205
1206         for (i = 0; i < pctl->desc->npins; i++) {
1207                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1208                 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1209
1210                 if (pin->variant && !(pctl->variant & pin->variant))
1211                         continue;
1212
1213                 group->name = pin->pin.name;
1214                 group->pin = pin->pin.number;
1215
1216                 /* And now we count the actual number of pins / groups */
1217                 pctl->ngroups++;
1218         }
1219
1220         /*
1221          * We suppose that we won't have any more functions than pins,
1222          * we'll reallocate that later anyway
1223          */
1224         pctl->functions = kcalloc(pctl->ngroups,
1225                                   sizeof(*pctl->functions),
1226                                   GFP_KERNEL);
1227         if (!pctl->functions)
1228                 return -ENOMEM;
1229
1230         /* Count functions and their associated groups */
1231         for (i = 0; i < pctl->desc->npins; i++) {
1232                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1233                 struct sunxi_desc_function *func;
1234
1235                 if (pin->variant && !(pctl->variant & pin->variant))
1236                         continue;
1237
1238                 for (func = pin->functions; func->name; func++) {
1239                         if (func->variant && !(pctl->variant & func->variant))
1240                                 continue;
1241
1242                         /* Create interrupt mapping while we're at it */
1243                         if (!strcmp(func->name, "irq")) {
1244                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1245                                 pctl->irq_array[irqnum] = pin->pin.number;
1246                         }
1247
1248                         sunxi_pinctrl_add_function(pctl, func->name);
1249                 }
1250         }
1251
1252         /* And now allocated and fill the array for real */
1253         ptr = krealloc(pctl->functions,
1254                        pctl->nfunctions * sizeof(*pctl->functions),
1255                        GFP_KERNEL);
1256         if (!ptr) {
1257                 kfree(pctl->functions);
1258                 pctl->functions = NULL;
1259                 return -ENOMEM;
1260         }
1261         pctl->functions = ptr;
1262
1263         for (i = 0; i < pctl->desc->npins; i++) {
1264                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1265                 struct sunxi_desc_function *func;
1266
1267                 if (pin->variant && !(pctl->variant & pin->variant))
1268                         continue;
1269
1270                 for (func = pin->functions; func->name; func++) {
1271                         struct sunxi_pinctrl_function *func_item;
1272                         const char **func_grp;
1273
1274                         if (func->variant && !(pctl->variant & func->variant))
1275                                 continue;
1276
1277                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
1278                                                                         func->name);
1279                         if (!func_item) {
1280                                 kfree(pctl->functions);
1281                                 return -EINVAL;
1282                         }
1283
1284                         if (!func_item->groups) {
1285                                 func_item->groups =
1286                                         devm_kcalloc(&pdev->dev,
1287                                                      func_item->ngroups,
1288                                                      sizeof(*func_item->groups),
1289                                                      GFP_KERNEL);
1290                                 if (!func_item->groups) {
1291                                         kfree(pctl->functions);
1292                                         return -ENOMEM;
1293                                 }
1294                         }
1295
1296                         func_grp = func_item->groups;
1297                         while (*func_grp)
1298                                 func_grp++;
1299
1300                         *func_grp = pin->pin.name;
1301                 }
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1308 {
1309         unsigned long clock = clk_get_rate(clk);
1310         unsigned int best_diff, best_div;
1311         int i;
1312
1313         best_diff = abs(freq - clock);
1314         best_div = 0;
1315
1316         for (i = 1; i < 8; i++) {
1317                 int cur_diff = abs(freq - (clock >> i));
1318
1319                 if (cur_diff < best_diff) {
1320                         best_diff = cur_diff;
1321                         best_div = i;
1322                 }
1323         }
1324
1325         *diff = best_diff;
1326         return best_div;
1327 }
1328
1329 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1330                                         struct device_node *node)
1331 {
1332         unsigned int hosc_diff, losc_diff;
1333         unsigned int hosc_div, losc_div;
1334         struct clk *hosc, *losc;
1335         u8 div, src;
1336         int i, ret;
1337
1338         /* Deal with old DTs that didn't have the oscillators */
1339         if (of_clk_get_parent_count(node) != 3)
1340                 return 0;
1341
1342         /* If we don't have any setup, bail out */
1343         if (!of_find_property(node, "input-debounce", NULL))
1344                 return 0;
1345
1346         losc = devm_clk_get(pctl->dev, "losc");
1347         if (IS_ERR(losc))
1348                 return PTR_ERR(losc);
1349
1350         hosc = devm_clk_get(pctl->dev, "hosc");
1351         if (IS_ERR(hosc))
1352                 return PTR_ERR(hosc);
1353
1354         for (i = 0; i < pctl->desc->irq_banks; i++) {
1355                 unsigned long debounce_freq;
1356                 u32 debounce;
1357
1358                 ret = of_property_read_u32_index(node, "input-debounce",
1359                                                  i, &debounce);
1360                 if (ret)
1361                         return ret;
1362
1363                 if (!debounce)
1364                         continue;
1365
1366                 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1367                 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1368                                                           debounce_freq,
1369                                                           &losc_diff);
1370
1371                 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1372                                                           debounce_freq,
1373                                                           &hosc_diff);
1374
1375                 if (hosc_diff < losc_diff) {
1376                         div = hosc_div;
1377                         src = 1;
1378                 } else {
1379                         div = losc_div;
1380                         src = 0;
1381                 }
1382
1383                 writel(src | div << 4,
1384                        pctl->membase +
1385                        sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1386         }
1387
1388         return 0;
1389 }
1390
1391 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1392                                     const struct sunxi_pinctrl_desc *desc,
1393                                     unsigned long variant)
1394 {
1395         struct device_node *node = pdev->dev.of_node;
1396         struct pinctrl_desc *pctrl_desc;
1397         struct pinctrl_pin_desc *pins;
1398         struct sunxi_pinctrl *pctl;
1399         struct pinmux_ops *pmxops;
1400         int i, ret, last_pin, pin_idx;
1401         struct clk *clk;
1402
1403         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1404         if (!pctl)
1405                 return -ENOMEM;
1406         platform_set_drvdata(pdev, pctl);
1407
1408         raw_spin_lock_init(&pctl->lock);
1409
1410         pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1411         if (IS_ERR(pctl->membase))
1412                 return PTR_ERR(pctl->membase);
1413
1414         pctl->dev = &pdev->dev;
1415         pctl->desc = desc;
1416         pctl->variant = variant;
1417
1418         pctl->irq_array = devm_kcalloc(&pdev->dev,
1419                                        IRQ_PER_BANK * pctl->desc->irq_banks,
1420                                        sizeof(*pctl->irq_array),
1421                                        GFP_KERNEL);
1422         if (!pctl->irq_array)
1423                 return -ENOMEM;
1424
1425         ret = sunxi_pinctrl_build_state(pdev);
1426         if (ret) {
1427                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1428                 return ret;
1429         }
1430
1431         pins = devm_kcalloc(&pdev->dev,
1432                             pctl->desc->npins, sizeof(*pins),
1433                             GFP_KERNEL);
1434         if (!pins)
1435                 return -ENOMEM;
1436
1437         for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1438                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1439
1440                 if (pin->variant && !(pctl->variant & pin->variant))
1441                         continue;
1442
1443                 pins[pin_idx++] = pin->pin;
1444         }
1445
1446         pctrl_desc = devm_kzalloc(&pdev->dev,
1447                                   sizeof(*pctrl_desc),
1448                                   GFP_KERNEL);
1449         if (!pctrl_desc)
1450                 return -ENOMEM;
1451
1452         pctrl_desc->name = dev_name(&pdev->dev);
1453         pctrl_desc->owner = THIS_MODULE;
1454         pctrl_desc->pins = pins;
1455         pctrl_desc->npins = pctl->ngroups;
1456         pctrl_desc->confops = &sunxi_pconf_ops;
1457         pctrl_desc->pctlops = &sunxi_pctrl_ops;
1458
1459         pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1460                               GFP_KERNEL);
1461         if (!pmxops)
1462                 return -ENOMEM;
1463
1464         if (desc->disable_strict_mode)
1465                 pmxops->strict = false;
1466
1467         pctrl_desc->pmxops = pmxops;
1468
1469         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1470         if (IS_ERR(pctl->pctl_dev)) {
1471                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1472                 return PTR_ERR(pctl->pctl_dev);
1473         }
1474
1475         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1476         if (!pctl->chip)
1477                 return -ENOMEM;
1478
1479         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1480         pctl->chip->owner = THIS_MODULE;
1481         pctl->chip->request = gpiochip_generic_request;
1482         pctl->chip->free = gpiochip_generic_free;
1483         pctl->chip->set_config = gpiochip_generic_config;
1484         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1485         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1486         pctl->chip->get = sunxi_pinctrl_gpio_get;
1487         pctl->chip->set = sunxi_pinctrl_gpio_set;
1488         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1489         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1490         pctl->chip->of_gpio_n_cells = 3;
1491         pctl->chip->can_sleep = false;
1492         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1493                             pctl->desc->pin_base;
1494         pctl->chip->label = dev_name(&pdev->dev);
1495         pctl->chip->parent = &pdev->dev;
1496         pctl->chip->base = pctl->desc->pin_base;
1497
1498         ret = gpiochip_add_data(pctl->chip, pctl);
1499         if (ret)
1500                 return ret;
1501
1502         for (i = 0; i < pctl->desc->npins; i++) {
1503                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1504
1505                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1506                                              pin->pin.number - pctl->desc->pin_base,
1507                                              pin->pin.number, 1);
1508                 if (ret)
1509                         goto gpiochip_error;
1510         }
1511
1512         ret = of_clk_get_parent_count(node);
1513         clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1514         if (IS_ERR(clk)) {
1515                 ret = PTR_ERR(clk);
1516                 goto gpiochip_error;
1517         }
1518
1519         ret = clk_prepare_enable(clk);
1520         if (ret)
1521                 goto gpiochip_error;
1522
1523         pctl->irq = devm_kcalloc(&pdev->dev,
1524                                  pctl->desc->irq_banks,
1525                                  sizeof(*pctl->irq),
1526                                  GFP_KERNEL);
1527         if (!pctl->irq) {
1528                 ret = -ENOMEM;
1529                 goto clk_error;
1530         }
1531
1532         for (i = 0; i < pctl->desc->irq_banks; i++) {
1533                 pctl->irq[i] = platform_get_irq(pdev, i);
1534                 if (pctl->irq[i] < 0) {
1535                         ret = pctl->irq[i];
1536                         goto clk_error;
1537                 }
1538         }
1539
1540         pctl->domain = irq_domain_add_linear(node,
1541                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1542                                              &sunxi_pinctrl_irq_domain_ops,
1543                                              pctl);
1544         if (!pctl->domain) {
1545                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1546                 ret = -ENOMEM;
1547                 goto clk_error;
1548         }
1549
1550         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1551                 int irqno = irq_create_mapping(pctl->domain, i);
1552
1553                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1554                                          handle_edge_irq);
1555                 irq_set_chip_data(irqno, pctl);
1556         }
1557
1558         for (i = 0; i < pctl->desc->irq_banks; i++) {
1559                 /* Mask and clear all IRQs before registering a handler */
1560                 writel(0, pctl->membase +
1561                           sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1562                 writel(0xffffffff,
1563                        pctl->membase +
1564                        sunxi_irq_status_reg_from_bank(pctl->desc, i));
1565
1566                 irq_set_chained_handler_and_data(pctl->irq[i],
1567                                                  sunxi_pinctrl_irq_handler,
1568                                                  pctl);
1569         }
1570
1571         sunxi_pinctrl_setup_debounce(pctl, node);
1572
1573         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1574
1575         return 0;
1576
1577 clk_error:
1578         clk_disable_unprepare(clk);
1579 gpiochip_error:
1580         gpiochip_remove(pctl->chip);
1581         return ret;
1582 }