1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
7 * Heavily based on Mediatek's pinctrl driver
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/seq_file.h>
24 #include <linux/slab.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
34 #include "../pinconf.h"
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
38 #define STM32_GPIO_MODER 0x00
39 #define STM32_GPIO_TYPER 0x04
40 #define STM32_GPIO_SPEEDR 0x08
41 #define STM32_GPIO_PUPDR 0x0c
42 #define STM32_GPIO_IDR 0x10
43 #define STM32_GPIO_ODR 0x14
44 #define STM32_GPIO_BSRR 0x18
45 #define STM32_GPIO_LCKR 0x1c
46 #define STM32_GPIO_AFRL 0x20
47 #define STM32_GPIO_AFRH 0x24
48 #define STM32_GPIO_SECCFGR 0x30
50 /* custom bitfield to backup pin status */
51 #define STM32_GPIO_BKP_MODE_SHIFT 0
52 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
53 #define STM32_GPIO_BKP_ALT_SHIFT 2
54 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
55 #define STM32_GPIO_BKP_SPEED_SHIFT 6
56 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
57 #define STM32_GPIO_BKP_PUPD_SHIFT 8
58 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
59 #define STM32_GPIO_BKP_TYPE 10
60 #define STM32_GPIO_BKP_VAL 11
62 #define STM32_GPIO_PINS_PER_BANK 16
63 #define STM32_GPIO_IRQ_LINE 16
65 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
67 #define gpio_range_to_bank(chip) \
68 container_of(chip, struct stm32_gpio_bank, range)
70 #define HWSPNLCK_TIMEOUT 1000 /* usec */
72 static const char * const stm32_gpio_functions[] = {
77 "af11", "af12", "af13",
78 "af14", "af15", "analog",
81 struct stm32_pinctrl_group {
87 struct stm32_gpio_bank {
90 struct reset_control *rstc;
92 struct gpio_chip gpio_chip;
93 struct pinctrl_gpio_range range;
94 struct fwnode_handle *fwnode;
95 struct irq_domain *domain;
98 u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
99 u8 irq_type[STM32_GPIO_PINS_PER_BANK];
103 struct stm32_pinctrl {
105 struct pinctrl_dev *pctl_dev;
106 struct pinctrl_desc pctl_desc;
107 struct stm32_pinctrl_group *groups;
109 const char **grp_names;
110 struct stm32_gpio_bank *banks;
112 const struct stm32_pinctrl_match_data *match_data;
113 struct irq_domain *domain;
114 struct regmap *regmap;
115 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
116 struct hwspinlock *hwlock;
117 struct stm32_desc_pin *pins;
121 spinlock_t irqmux_lock;
124 static inline int stm32_gpio_pin(int gpio)
126 return gpio % STM32_GPIO_PINS_PER_BANK;
129 static inline u32 stm32_gpio_get_mode(u32 function)
134 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
136 case STM32_PIN_ANALOG:
143 static inline u32 stm32_gpio_get_alt(u32 function)
148 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
150 case STM32_PIN_ANALOG:
157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
158 u32 offset, u32 value)
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
168 STM32_GPIO_BKP_ALT_MASK);
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
197 unsigned offset, int value)
199 stm32_gpio_backup_value(bank, offset, value);
202 offset += STM32_GPIO_PINS_PER_BANK;
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 struct pinctrl_gpio_range *range;
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
220 return pinctrl_gpio_request(chip, offset);
223 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
225 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
227 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
230 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
232 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
234 __stm32_gpio_set(bank, offset, value);
237 static int stm32_gpio_direction_output(struct gpio_chip *chip,
238 unsigned offset, int value)
240 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
242 __stm32_gpio_set(bank, offset, value);
243 pinctrl_gpio_direction_output(chip, offset);
249 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
252 struct irq_fwspec fwspec;
254 fwspec.fwnode = bank->fwnode;
255 fwspec.param_count = 2;
256 fwspec.param[0] = offset;
257 fwspec.param[1] = IRQ_TYPE_NONE;
259 return irq_create_fwspec_mapping(&fwspec);
262 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
265 int pin = stm32_gpio_pin(offset);
269 stm32_pmx_get_mode(bank, pin, &mode, &alt);
270 if ((alt == 0) && (mode == 0))
271 ret = GPIO_LINE_DIRECTION_IN;
272 else if ((alt == 0) && (mode == 1))
273 ret = GPIO_LINE_DIRECTION_OUT;
280 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
281 unsigned long *valid_mask,
284 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
285 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
289 /* All gpio are valid per default */
290 bitmap_fill(valid_mask, ngpios);
292 if (bank->secure_control) {
293 /* Tag secured pins as invalid */
294 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
296 for (i = 0; i < ngpios; i++) {
298 clear_bit(i, valid_mask);
299 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
307 static const struct gpio_chip stm32_gpio_template = {
308 .request = stm32_gpio_request,
309 .free = pinctrl_gpio_free,
310 .get = stm32_gpio_get,
311 .set = stm32_gpio_set,
312 .direction_input = pinctrl_gpio_direction_input,
313 .direction_output = stm32_gpio_direction_output,
314 .to_irq = stm32_gpio_to_irq,
315 .get_direction = stm32_gpio_get_direction,
316 .set_config = gpiochip_generic_config,
317 .init_valid_mask = stm32_gpio_init_valid_mask,
320 static void stm32_gpio_irq_trigger(struct irq_data *d)
322 struct stm32_gpio_bank *bank = d->domain->host_data;
325 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
326 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
329 /* If level interrupt type then retrig */
330 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
331 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
332 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
333 irq_chip_retrigger_hierarchy(d);
336 static void stm32_gpio_irq_eoi(struct irq_data *d)
338 irq_chip_eoi_parent(d);
339 stm32_gpio_irq_trigger(d);
342 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
344 struct stm32_gpio_bank *bank = d->domain->host_data;
348 case IRQ_TYPE_EDGE_RISING:
349 case IRQ_TYPE_EDGE_FALLING:
350 case IRQ_TYPE_EDGE_BOTH:
353 case IRQ_TYPE_LEVEL_HIGH:
354 parent_type = IRQ_TYPE_EDGE_RISING;
356 case IRQ_TYPE_LEVEL_LOW:
357 parent_type = IRQ_TYPE_EDGE_FALLING;
363 bank->irq_type[d->hwirq] = type;
365 return irq_chip_set_type_parent(d, parent_type);
368 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
370 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
371 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
374 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
378 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
380 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
388 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
390 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
392 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
395 static void stm32_gpio_irq_unmask(struct irq_data *d)
397 irq_chip_unmask_parent(d);
398 stm32_gpio_irq_trigger(d);
401 static struct irq_chip stm32_gpio_irq_chip = {
403 .irq_eoi = stm32_gpio_irq_eoi,
404 .irq_ack = irq_chip_ack_parent,
405 .irq_mask = irq_chip_mask_parent,
406 .irq_unmask = stm32_gpio_irq_unmask,
407 .irq_set_type = stm32_gpio_set_type,
408 .irq_set_wake = irq_chip_set_wake_parent,
409 .irq_request_resources = stm32_gpio_irq_request_resources,
410 .irq_release_resources = stm32_gpio_irq_release_resources,
413 static int stm32_gpio_domain_translate(struct irq_domain *d,
414 struct irq_fwspec *fwspec,
415 unsigned long *hwirq,
418 if ((fwspec->param_count != 2) ||
419 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
422 *hwirq = fwspec->param[0];
423 *type = fwspec->param[1];
427 static int stm32_gpio_domain_activate(struct irq_domain *d,
428 struct irq_data *irq_data, bool reserve)
430 struct stm32_gpio_bank *bank = d->host_data;
431 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
435 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
438 dev_err(pctl->dev, "Can't get hwspinlock\n");
443 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
446 hwspin_unlock_in_atomic(pctl->hwlock);
451 static int stm32_gpio_domain_alloc(struct irq_domain *d,
453 unsigned int nr_irqs, void *data)
455 struct stm32_gpio_bank *bank = d->host_data;
456 struct irq_fwspec *fwspec = data;
457 struct irq_fwspec parent_fwspec;
458 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
459 irq_hw_number_t hwirq = fwspec->param[0];
464 * Check first that the IRQ MUX of that line is free.
465 * gpio irq mux is shared between several banks, protect with a lock
467 spin_lock_irqsave(&pctl->irqmux_lock, flags);
469 if (pctl->irqmux_map & BIT(hwirq)) {
470 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
473 pctl->irqmux_map |= BIT(hwirq);
476 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
480 parent_fwspec.fwnode = d->parent->fwnode;
481 parent_fwspec.param_count = 2;
482 parent_fwspec.param[0] = fwspec->param[0];
483 parent_fwspec.param[1] = fwspec->param[1];
485 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
488 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
491 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
492 unsigned int nr_irqs)
494 struct stm32_gpio_bank *bank = d->host_data;
495 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
496 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
497 unsigned long flags, hwirq = irq_data->hwirq;
499 irq_domain_free_irqs_common(d, virq, nr_irqs);
501 spin_lock_irqsave(&pctl->irqmux_lock, flags);
502 pctl->irqmux_map &= ~BIT(hwirq);
503 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
506 static const struct irq_domain_ops stm32_gpio_domain_ops = {
507 .translate = stm32_gpio_domain_translate,
508 .alloc = stm32_gpio_domain_alloc,
509 .free = stm32_gpio_domain_free,
510 .activate = stm32_gpio_domain_activate,
513 /* Pinctrl functions */
514 static struct stm32_pinctrl_group *
515 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
519 for (i = 0; i < pctl->ngroups; i++) {
520 struct stm32_pinctrl_group *grp = pctl->groups + i;
529 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
530 u32 pin_num, u32 fnum)
534 for (i = 0; i < pctl->npins; i++) {
535 const struct stm32_desc_pin *pin = pctl->pins + i;
536 const struct stm32_desc_function *func = pin->functions;
538 if (pin->pin.number != pin_num)
541 for (k = 0; k < STM32_CONFIG_NUM; k++) {
542 if (func->num == fnum)
550 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
555 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
556 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
557 struct pinctrl_map **map, unsigned *reserved_maps,
560 if (*num_maps == *reserved_maps)
563 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
564 (*map)[*num_maps].data.mux.group = grp->name;
566 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
569 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
575 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
576 struct device_node *node,
577 struct pinctrl_map **map,
578 unsigned *reserved_maps,
581 struct stm32_pinctrl *pctl;
582 struct stm32_pinctrl_group *grp;
583 struct property *pins;
584 u32 pinfunc, pin, func;
585 unsigned long *configs;
586 unsigned int num_configs;
588 unsigned reserve = 0;
589 int num_pins, num_funcs, maps_per_pin, i, err = 0;
591 pctl = pinctrl_dev_get_drvdata(pctldev);
593 pins = of_find_property(node, "pinmux", NULL);
595 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
600 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
608 num_pins = pins->length / sizeof(u32);
609 num_funcs = num_pins;
613 if (has_config && num_pins >= 1)
616 if (!num_pins || !maps_per_pin) {
621 reserve = num_pins * maps_per_pin;
623 err = pinctrl_utils_reserve_map(pctldev, map,
624 reserved_maps, num_maps, reserve);
628 for (i = 0; i < num_pins; i++) {
629 err = of_property_read_u32_index(node, "pinmux",
634 pin = STM32_GET_PIN_NO(pinfunc);
635 func = STM32_GET_PIN_FUNC(pinfunc);
637 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
642 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
644 dev_err(pctl->dev, "unable to match pin %d to group\n",
650 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
651 reserved_maps, num_maps);
656 err = pinctrl_utils_add_map_configs(pctldev, map,
657 reserved_maps, num_maps, grp->name,
658 configs, num_configs,
659 PIN_MAP_TYPE_CONFIGS_GROUP);
670 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
671 struct device_node *np_config,
672 struct pinctrl_map **map, unsigned *num_maps)
674 struct device_node *np;
675 unsigned reserved_maps;
682 for_each_child_of_node(np_config, np) {
683 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
684 &reserved_maps, num_maps);
686 pinctrl_utils_free_map(pctldev, *map, *num_maps);
695 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
697 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
699 return pctl->ngroups;
702 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
705 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
707 return pctl->groups[group].name;
710 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
712 const unsigned **pins,
715 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
717 *pins = (unsigned *)&pctl->groups[group].pin;
723 static const struct pinctrl_ops stm32_pctrl_ops = {
724 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
725 .dt_free_map = pinctrl_utils_free_map,
726 .get_groups_count = stm32_pctrl_get_groups_count,
727 .get_group_name = stm32_pctrl_get_group_name,
728 .get_group_pins = stm32_pctrl_get_group_pins,
732 /* Pinmux functions */
734 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
736 return ARRAY_SIZE(stm32_gpio_functions);
739 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
742 return stm32_gpio_functions[selector];
745 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
747 const char * const **groups,
748 unsigned * const num_groups)
750 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
752 *groups = pctl->grp_names;
753 *num_groups = pctl->ngroups;
758 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
759 int pin, u32 mode, u32 alt)
761 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
763 int alt_shift = (pin % 8) * 4;
764 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
768 spin_lock_irqsave(&bank->lock, flags);
771 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
774 dev_err(pctl->dev, "Can't get hwspinlock\n");
779 val = readl_relaxed(bank->base + alt_offset);
780 val &= ~GENMASK(alt_shift + 3, alt_shift);
781 val |= (alt << alt_shift);
782 writel_relaxed(val, bank->base + alt_offset);
784 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
785 val &= ~GENMASK(pin * 2 + 1, pin * 2);
786 val |= mode << (pin * 2);
787 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
790 hwspin_unlock_in_atomic(pctl->hwlock);
792 stm32_gpio_backup_mode(bank, pin, mode, alt);
795 spin_unlock_irqrestore(&bank->lock, flags);
800 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
804 int alt_shift = (pin % 8) * 4;
805 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
808 spin_lock_irqsave(&bank->lock, flags);
810 val = readl_relaxed(bank->base + alt_offset);
811 val &= GENMASK(alt_shift + 3, alt_shift);
812 *alt = val >> alt_shift;
814 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
815 val &= GENMASK(pin * 2 + 1, pin * 2);
816 *mode = val >> (pin * 2);
818 spin_unlock_irqrestore(&bank->lock, flags);
821 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
826 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
827 struct stm32_pinctrl_group *g = pctl->groups + group;
828 struct pinctrl_gpio_range *range;
829 struct stm32_gpio_bank *bank;
833 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
837 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
839 dev_err(pctl->dev, "No gpio range defined.\n");
843 bank = gpiochip_get_data(range->gc);
844 pin = stm32_gpio_pin(g->pin);
846 mode = stm32_gpio_get_mode(function);
847 alt = stm32_gpio_get_alt(function);
849 return stm32_pmx_set_mode(bank, pin, mode, alt);
852 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
853 struct pinctrl_gpio_range *range, unsigned gpio,
856 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
857 int pin = stm32_gpio_pin(gpio);
859 return stm32_pmx_set_mode(bank, pin, !input, 0);
862 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
864 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
865 struct pinctrl_gpio_range *range;
867 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
869 dev_err(pctl->dev, "No gpio range defined.\n");
873 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
874 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
881 static const struct pinmux_ops stm32_pmx_ops = {
882 .get_functions_count = stm32_pmx_get_funcs_cnt,
883 .get_function_name = stm32_pmx_get_func_name,
884 .get_function_groups = stm32_pmx_get_func_groups,
885 .set_mux = stm32_pmx_set_mux,
886 .gpio_set_direction = stm32_pmx_gpio_set_direction,
887 .request = stm32_pmx_request,
891 /* Pinconf functions */
893 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
894 unsigned offset, u32 drive)
896 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
901 spin_lock_irqsave(&bank->lock, flags);
904 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
907 dev_err(pctl->dev, "Can't get hwspinlock\n");
912 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
914 val |= drive << offset;
915 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
918 hwspin_unlock_in_atomic(pctl->hwlock);
920 stm32_gpio_backup_driving(bank, offset, drive);
923 spin_unlock_irqrestore(&bank->lock, flags);
928 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
934 spin_lock_irqsave(&bank->lock, flags);
936 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
939 spin_unlock_irqrestore(&bank->lock, flags);
941 return (val >> offset);
944 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
945 unsigned offset, u32 speed)
947 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
952 spin_lock_irqsave(&bank->lock, flags);
955 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
958 dev_err(pctl->dev, "Can't get hwspinlock\n");
963 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
964 val &= ~GENMASK(offset * 2 + 1, offset * 2);
965 val |= speed << (offset * 2);
966 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
969 hwspin_unlock_in_atomic(pctl->hwlock);
971 stm32_gpio_backup_speed(bank, offset, speed);
974 spin_unlock_irqrestore(&bank->lock, flags);
979 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
985 spin_lock_irqsave(&bank->lock, flags);
987 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
988 val &= GENMASK(offset * 2 + 1, offset * 2);
990 spin_unlock_irqrestore(&bank->lock, flags);
992 return (val >> (offset * 2));
995 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
996 unsigned offset, u32 bias)
998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1003 spin_lock_irqsave(&bank->lock, flags);
1006 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1009 dev_err(pctl->dev, "Can't get hwspinlock\n");
1014 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1015 val &= ~GENMASK(offset * 2 + 1, offset * 2);
1016 val |= bias << (offset * 2);
1017 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1020 hwspin_unlock_in_atomic(pctl->hwlock);
1022 stm32_gpio_backup_bias(bank, offset, bias);
1025 spin_unlock_irqrestore(&bank->lock, flags);
1030 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1031 unsigned int offset)
1033 unsigned long flags;
1036 spin_lock_irqsave(&bank->lock, flags);
1038 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1039 val &= GENMASK(offset * 2 + 1, offset * 2);
1041 spin_unlock_irqrestore(&bank->lock, flags);
1043 return (val >> (offset * 2));
1046 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1047 unsigned int offset, bool dir)
1049 unsigned long flags;
1052 spin_lock_irqsave(&bank->lock, flags);
1055 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1058 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1061 spin_unlock_irqrestore(&bank->lock, flags);
1066 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1067 unsigned int pin, enum pin_config_param param,
1068 enum pin_config_param arg)
1070 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1071 struct pinctrl_gpio_range *range;
1072 struct stm32_gpio_bank *bank;
1073 int offset, ret = 0;
1075 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1077 dev_err(pctl->dev, "No gpio range defined.\n");
1081 bank = gpiochip_get_data(range->gc);
1082 offset = stm32_gpio_pin(pin);
1084 if (!gpiochip_line_is_valid(range->gc, offset)) {
1085 dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1090 case PIN_CONFIG_DRIVE_PUSH_PULL:
1091 ret = stm32_pconf_set_driving(bank, offset, 0);
1093 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1094 ret = stm32_pconf_set_driving(bank, offset, 1);
1096 case PIN_CONFIG_SLEW_RATE:
1097 ret = stm32_pconf_set_speed(bank, offset, arg);
1099 case PIN_CONFIG_BIAS_DISABLE:
1100 ret = stm32_pconf_set_bias(bank, offset, 0);
1102 case PIN_CONFIG_BIAS_PULL_UP:
1103 ret = stm32_pconf_set_bias(bank, offset, 1);
1105 case PIN_CONFIG_BIAS_PULL_DOWN:
1106 ret = stm32_pconf_set_bias(bank, offset, 2);
1108 case PIN_CONFIG_OUTPUT:
1109 __stm32_gpio_set(bank, offset, arg);
1110 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1119 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1121 unsigned long *config)
1123 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1125 *config = pctl->groups[group].config;
1130 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1131 unsigned long *configs, unsigned num_configs)
1133 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1134 struct stm32_pinctrl_group *g = &pctl->groups[group];
1137 for (i = 0; i < num_configs; i++) {
1138 mutex_lock(&pctldev->mutex);
1139 ret = stm32_pconf_parse_conf(pctldev, g->pin,
1140 pinconf_to_config_param(configs[i]),
1141 pinconf_to_config_argument(configs[i]));
1142 mutex_unlock(&pctldev->mutex);
1146 g->config = configs[i];
1152 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1153 unsigned long *configs, unsigned int num_configs)
1157 for (i = 0; i < num_configs; i++) {
1158 ret = stm32_pconf_parse_conf(pctldev, pin,
1159 pinconf_to_config_param(configs[i]),
1160 pinconf_to_config_argument(configs[i]));
1168 static struct stm32_desc_pin *
1169 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1170 unsigned int pin_number)
1172 struct stm32_desc_pin *pins = pctl->pins;
1175 for (i = 0; i < pctl->npins; i++) {
1176 if (pins->pin.number == pin_number)
1183 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1187 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1188 const struct stm32_desc_pin *pin_desc;
1189 struct pinctrl_gpio_range *range;
1190 struct stm32_gpio_bank *bank;
1192 u32 mode, alt, drive, speed, bias;
1193 static const char * const modes[] = {
1194 "input", "output", "alternate", "analog" };
1195 static const char * const speeds[] = {
1196 "low", "medium", "high", "very high" };
1197 static const char * const biasing[] = {
1198 "floating", "pull up", "pull down", "" };
1201 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1205 bank = gpiochip_get_data(range->gc);
1206 offset = stm32_gpio_pin(pin);
1208 if (!gpiochip_line_is_valid(range->gc, offset)) {
1209 seq_puts(s, "NO ACCESS");
1213 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1214 bias = stm32_pconf_get_bias(bank, offset);
1216 seq_printf(s, "%s ", modes[mode]);
1221 val = stm32_pconf_get(bank, offset, true);
1222 seq_printf(s, "- %s - %s",
1223 val ? "high" : "low",
1229 drive = stm32_pconf_get_driving(bank, offset);
1230 speed = stm32_pconf_get_speed(bank, offset);
1231 val = stm32_pconf_get(bank, offset, false);
1232 seq_printf(s, "- %s - %s - %s - %s %s",
1233 val ? "high" : "low",
1234 drive ? "open drain" : "push pull",
1236 speeds[speed], "speed");
1241 drive = stm32_pconf_get_driving(bank, offset);
1242 speed = stm32_pconf_get_speed(bank, offset);
1243 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1247 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1248 pin_desc->functions[alt + 1].name,
1249 drive ? "open drain" : "push pull",
1251 speeds[speed], "speed");
1260 static const struct pinconf_ops stm32_pconf_ops = {
1261 .pin_config_group_get = stm32_pconf_group_get,
1262 .pin_config_group_set = stm32_pconf_group_set,
1263 .pin_config_set = stm32_pconf_set,
1264 .pin_config_dbg_show = stm32_pconf_dbg_show,
1267 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
1268 struct stm32_gpio_bank *bank,
1269 unsigned int offset)
1271 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
1272 struct stm32_desc_pin *pin_desc;
1275 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
1276 if (stm32_pin_nb < pctl->npins) {
1277 pin_desc = pctl->pins + stm32_pin_nb;
1278 if (pin_desc->pin.number == stm32_pin_nb)
1282 /* Otherwise, loop all array to find the pin with the right number */
1283 for (i = 0; i < pctl->npins; i++) {
1284 pin_desc = pctl->pins + i;
1285 if (pin_desc->pin.number == stm32_pin_nb)
1291 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1293 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1295 struct pinctrl_gpio_range *range = &bank->range;
1296 struct fwnode_reference_args args;
1297 struct device *dev = pctl->dev;
1298 struct resource res;
1299 int npins = STM32_GPIO_PINS_PER_BANK;
1300 int bank_nr, err, i = 0;
1301 struct stm32_desc_pin *stm32_pin;
1304 if (!IS_ERR(bank->rstc))
1305 reset_control_deassert(bank->rstc);
1307 if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1310 bank->base = devm_ioremap_resource(dev, &res);
1311 if (IS_ERR(bank->base))
1312 return PTR_ERR(bank->base);
1314 err = clk_prepare_enable(bank->clk);
1316 dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
1320 bank->gpio_chip = stm32_gpio_template;
1322 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1324 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1325 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1326 bank->gpio_chip.base = args.args[1];
1328 /* get the last defined gpio line (offset + nb of pins) */
1329 npins = args.args[0] + args.args[2];
1330 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1331 npins = max(npins, (int)(args.args[0] + args.args[2]));
1333 bank_nr = pctl->nbanks;
1334 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1335 range->name = bank->gpio_chip.label;
1336 range->id = bank_nr;
1337 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1338 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1339 range->npins = npins;
1340 range->gc = &bank->gpio_chip;
1341 pinctrl_add_gpio_range(pctl->pctl_dev,
1342 &pctl->banks[bank_nr].range);
1345 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1346 bank_ioport_nr = bank_nr;
1348 bank->gpio_chip.base = -1;
1350 bank->gpio_chip.ngpio = npins;
1351 bank->gpio_chip.fwnode = fwnode;
1352 bank->gpio_chip.parent = dev;
1353 bank->bank_nr = bank_nr;
1354 bank->bank_ioport_nr = bank_ioport_nr;
1355 bank->secure_control = pctl->match_data->secure_control;
1356 spin_lock_init(&bank->lock);
1359 /* create irq hierarchical domain */
1360 bank->fwnode = fwnode;
1362 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1363 bank->fwnode, &stm32_gpio_domain_ops,
1366 if (!bank->domain) {
1372 names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
1378 for (i = 0; i < npins; i++) {
1379 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1380 if (stm32_pin && stm32_pin->pin.name)
1381 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
1386 bank->gpio_chip.names = (const char * const *)names;
1388 err = gpiochip_add_data(&bank->gpio_chip, bank);
1390 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1394 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1398 clk_disable_unprepare(bank->clk);
1402 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1404 struct device_node *np = pdev->dev.of_node;
1405 struct device_node *parent;
1406 struct irq_domain *domain;
1408 if (!of_property_present(np, "interrupt-parent"))
1411 parent = of_irq_find_parent(np);
1413 return ERR_PTR(-ENXIO);
1415 domain = irq_find_host(parent);
1416 of_node_put(parent);
1418 /* domain not registered yet */
1419 return ERR_PTR(-EPROBE_DEFER);
1424 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1425 struct stm32_pinctrl *pctl)
1427 struct device_node *np = pdev->dev.of_node;
1428 struct device *dev = &pdev->dev;
1431 int mask, mask_width;
1433 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1434 if (IS_ERR(pctl->regmap))
1435 return PTR_ERR(pctl->regmap);
1439 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1443 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1445 mask = SYSCFG_IRQMUX_MASK;
1447 mask_width = fls(mask);
1449 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1450 struct reg_field mux;
1452 mux.reg = offset + (i / 4) * 4;
1453 mux.lsb = (i % 4) * mask_width;
1454 mux.msb = mux.lsb + mask_width - 1;
1456 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1457 i, mux.reg, mux.lsb, mux.msb);
1459 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1460 if (IS_ERR(pctl->irqmux[i]))
1461 return PTR_ERR(pctl->irqmux[i]);
1467 static int stm32_pctrl_build_state(struct platform_device *pdev)
1469 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1472 pctl->ngroups = pctl->npins;
1474 /* Allocate groups */
1475 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1476 sizeof(*pctl->groups), GFP_KERNEL);
1480 /* We assume that one pin is one group, use pin name as group name. */
1481 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1482 sizeof(*pctl->grp_names), GFP_KERNEL);
1483 if (!pctl->grp_names)
1486 for (i = 0; i < pctl->npins; i++) {
1487 const struct stm32_desc_pin *pin = pctl->pins + i;
1488 struct stm32_pinctrl_group *group = pctl->groups + i;
1490 group->name = pin->pin.name;
1491 group->pin = pin->pin.number;
1492 pctl->grp_names[i] = pin->pin.name;
1498 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1499 struct stm32_desc_pin *pins)
1501 const struct stm32_desc_pin *p;
1502 int i, nb_pins_available = 0;
1504 for (i = 0; i < pctl->match_data->npins; i++) {
1505 p = pctl->match_data->pins + i;
1506 if (pctl->pkg && !(pctl->pkg & p->pkg))
1509 memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1510 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1512 nb_pins_available++;
1515 pctl->npins = nb_pins_available;
1520 int stm32_pctl_probe(struct platform_device *pdev)
1522 const struct stm32_pinctrl_match_data *match_data;
1523 struct fwnode_handle *child;
1524 struct device *dev = &pdev->dev;
1525 struct stm32_pinctrl *pctl;
1526 struct pinctrl_pin_desc *pins;
1527 int i, ret, hwlock_id;
1530 match_data = device_get_match_data(dev);
1534 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1538 platform_set_drvdata(pdev, pctl);
1540 /* check for IRQ controller (may require deferred probe) */
1541 pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1542 if (IS_ERR(pctl->domain))
1543 return PTR_ERR(pctl->domain);
1545 dev_warn(dev, "pinctrl without interrupt support\n");
1547 /* hwspinlock is optional */
1548 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1549 if (hwlock_id < 0) {
1550 if (hwlock_id == -EPROBE_DEFER)
1553 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1556 spin_lock_init(&pctl->irqmux_lock);
1559 pctl->match_data = match_data;
1561 /* get optional package information */
1562 if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1563 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1565 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1566 sizeof(*pctl->pins), GFP_KERNEL);
1570 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1574 ret = stm32_pctrl_build_state(pdev);
1576 dev_err(dev, "build state failed: %d\n", ret);
1581 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1586 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1591 for (i = 0; i < pctl->npins; i++)
1592 pins[i] = pctl->pins[i].pin;
1594 pctl->pctl_desc.name = dev_name(&pdev->dev);
1595 pctl->pctl_desc.owner = THIS_MODULE;
1596 pctl->pctl_desc.pins = pins;
1597 pctl->pctl_desc.npins = pctl->npins;
1598 pctl->pctl_desc.link_consumers = true;
1599 pctl->pctl_desc.confops = &stm32_pconf_ops;
1600 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1601 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1602 pctl->dev = &pdev->dev;
1604 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1607 if (IS_ERR(pctl->pctl_dev)) {
1608 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1609 return PTR_ERR(pctl->pctl_dev);
1612 banks = gpiochip_node_count(dev);
1614 dev_err(dev, "at least one GPIO bank is required\n");
1617 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1623 for_each_gpiochip_node(dev, child) {
1624 struct stm32_gpio_bank *bank = &pctl->banks[i];
1625 struct device_node *np = to_of_node(child);
1627 bank->rstc = of_reset_control_get_exclusive(np, NULL);
1628 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1629 fwnode_handle_put(child);
1630 return -EPROBE_DEFER;
1633 bank->clk = of_clk_get_by_name(np, NULL);
1634 if (IS_ERR(bank->clk)) {
1635 fwnode_handle_put(child);
1636 return dev_err_probe(dev, PTR_ERR(bank->clk),
1637 "failed to get clk\n");
1642 for_each_gpiochip_node(dev, child) {
1643 ret = stm32_gpiolib_register_bank(pctl, child);
1645 fwnode_handle_put(child);
1647 for (i = 0; i < pctl->nbanks; i++)
1648 clk_disable_unprepare(pctl->banks[i].clk);
1656 dev_info(dev, "Pinctrl STM32 initialized\n");
1661 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1662 struct stm32_pinctrl *pctl, u32 pin)
1664 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1665 u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1666 struct pinctrl_gpio_range *range;
1667 struct stm32_gpio_bank *bank;
1671 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1675 if (!gpiochip_line_is_valid(range->gc, offset))
1678 pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1680 if (!desc || (!pin_is_irq && !desc->gpio_owner))
1683 bank = gpiochip_get_data(range->gc);
1685 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1686 alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1687 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1688 mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1690 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1695 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1696 val = val >> STM32_GPIO_BKP_VAL;
1697 __stm32_gpio_set(bank, offset, val);
1700 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1701 val >>= STM32_GPIO_BKP_TYPE;
1702 ret = stm32_pconf_set_driving(bank, offset, val);
1706 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1707 val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1708 ret = stm32_pconf_set_speed(bank, offset, val);
1712 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1713 val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1714 ret = stm32_pconf_set_bias(bank, offset, val);
1719 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1724 int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
1726 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1729 for (i = 0; i < pctl->nbanks; i++)
1730 clk_disable(pctl->banks[i].clk);
1735 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1737 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1738 struct stm32_pinctrl_group *g = pctl->groups;
1741 for (i = 0; i < pctl->nbanks; i++)
1742 clk_enable(pctl->banks[i].clk);
1744 for (i = 0; i < pctl->ngroups; i++, g++)
1745 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);