1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC
5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6 * Copyright (C) 2022 StarFive Technology Co., Ltd.
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/seq_file.h>
20 #include <linux/spinlock.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
31 #include "../pinmux.h"
32 #include "../pinconf.h"
33 #include "pinctrl-starfive-jh7110.h"
35 /* pad control bits */
36 #define JH7110_PADCFG_POS BIT(7)
37 #define JH7110_PADCFG_SMT BIT(6)
38 #define JH7110_PADCFG_SLEW BIT(5)
39 #define JH7110_PADCFG_PD BIT(4)
40 #define JH7110_PADCFG_PU BIT(3)
41 #define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU)
42 #define JH7110_PADCFG_DS_MASK GENMASK(2, 1)
43 #define JH7110_PADCFG_DS_2MA (0U << 1)
44 #define JH7110_PADCFG_DS_4MA BIT(1)
45 #define JH7110_PADCFG_DS_8MA (2U << 1)
46 #define JH7110_PADCFG_DS_12MA (3U << 1)
47 #define JH7110_PADCFG_IE BIT(0)
50 * The packed pinmux values from the device tree look like this:
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
53 * | din | dout | doen | function | pin |
55 static unsigned int jh7110_pinmux_din(u32 v)
57 return (v & GENMASK(31, 24)) >> 24;
60 static u32 jh7110_pinmux_dout(u32 v)
62 return (v & GENMASK(23, 16)) >> 16;
65 static u32 jh7110_pinmux_doen(u32 v)
67 return (v & GENMASK(15, 10)) >> 10;
70 static u32 jh7110_pinmux_function(u32 v)
72 return (v & GENMASK(9, 8)) >> 8;
75 static unsigned int jh7110_pinmux_pin(u32 v)
77 return v & GENMASK(7, 0);
80 static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)
82 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
84 return container_of(gc, struct jh7110_pinctrl, gc);
87 struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)
89 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
91 return container_of(gc, struct jh7110_pinctrl, gc);
93 EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);
95 #ifdef CONFIG_DEBUG_FS
96 static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,
97 struct seq_file *s, unsigned int pin)
99 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
100 const struct jh7110_pinctrl_soc_info *info = sfp->info;
102 seq_printf(s, "%s", dev_name(pctldev->dev));
104 if (pin < sfp->gc.ngpio) {
105 unsigned int offset = 4 * (pin / 4);
106 unsigned int shift = 8 * (pin % 4);
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
111 dout = (dout >> shift) & info->dout_mask;
112 doen = (doen >> shift) & info->doen_mask;
113 gpi = ((gpi >> shift) - 2) & info->gpi_mask;
115 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
119 #define jh7110_pin_dbg_show NULL
122 static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
123 struct device_node *np,
124 struct pinctrl_map **maps,
125 unsigned int *num_maps)
127 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
128 struct device *dev = sfp->gc.parent;
129 struct device_node *child;
130 struct pinctrl_map *map;
131 const char **pgnames;
138 for_each_available_child_of_node(np, child)
142 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
146 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
152 mutex_lock(&sfp->mutex);
153 for_each_available_child_of_node(np, child) {
154 int npins = of_property_count_u32_elems(child, "pinmux");
161 "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
167 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
173 pgnames[ngroups++] = grpname;
175 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
181 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
187 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
191 for (i = 0; i < npins; i++)
192 pins[i] = jh7110_pinmux_pin(pinmux[i]);
194 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
195 map[nmaps].data.mux.function = np->name;
196 map[nmaps].data.mux.group = grpname;
199 ret = pinctrl_generic_add_group(pctldev, grpname,
200 pins, npins, pinmux);
202 dev_err(dev, "error adding group %s: %d\n", grpname, ret);
206 ret = pinconf_generic_parse_dt_config(child, pctldev,
207 &map[nmaps].data.configs.configs,
208 &map[nmaps].data.configs.num_configs);
210 dev_err(dev, "error parsing pin config of group %s: %d\n",
215 /* don't create a map if there are no pinconf settings */
216 if (map[nmaps].data.configs.num_configs == 0)
219 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
220 map[nmaps].data.configs.group_or_pin = grpname;
224 ret = pinmux_generic_add_function(pctldev, np->name,
225 pgnames, ngroups, NULL);
227 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
230 mutex_unlock(&sfp->mutex);
239 pinctrl_utils_free_map(pctldev, map, nmaps);
240 mutex_unlock(&sfp->mutex);
244 static const struct pinctrl_ops jh7110_pinctrl_ops = {
245 .get_groups_count = pinctrl_generic_get_group_count,
246 .get_group_name = pinctrl_generic_get_group_name,
247 .get_group_pins = pinctrl_generic_get_group_pins,
248 .pin_dbg_show = jh7110_pin_dbg_show,
249 .dt_node_to_map = jh7110_dt_node_to_map,
250 .dt_free_map = pinctrl_utils_free_map,
253 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
254 unsigned int din, u32 dout, u32 doen)
256 const struct jh7110_pinctrl_soc_info *info = sfp->info;
258 unsigned int offset = 4 * (pin / 4);
259 unsigned int shift = 8 * (pin % 4);
260 u32 dout_mask = info->dout_mask << shift;
261 u32 done_mask = info->doen_mask << shift;
263 void __iomem *reg_dout;
264 void __iomem *reg_doen;
265 void __iomem *reg_din;
268 reg_dout = sfp->base + info->dout_reg_base + offset;
269 reg_doen = sfp->base + info->doen_reg_base + offset;
272 if (din != GPI_NONE) {
273 unsigned int ioffset = 4 * (din / 4);
274 unsigned int ishift = 8 * (din % 4);
276 reg_din = sfp->base + info->gpi_reg_base + ioffset;
277 ival = (pin + 2) << ishift;
278 imask = info->gpi_mask << ishift;
283 raw_spin_lock_irqsave(&sfp->lock, flags);
284 dout |= readl_relaxed(reg_dout) & ~dout_mask;
285 writel_relaxed(dout, reg_dout);
286 doen |= readl_relaxed(reg_doen) & ~done_mask;
287 writel_relaxed(doen, reg_doen);
289 ival |= readl_relaxed(reg_din) & ~imask;
290 writel_relaxed(ival, reg_din);
292 raw_spin_unlock_irqrestore(&sfp->lock, flags);
294 EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);
296 static int jh7110_set_mux(struct pinctrl_dev *pctldev,
297 unsigned int fsel, unsigned int gsel)
299 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
300 const struct jh7110_pinctrl_soc_info *info = sfp->info;
301 const struct group_desc *group;
305 group = pinctrl_generic_get_group(pctldev, gsel);
309 pinmux = group->data;
310 for (i = 0; i < group->num_pins; i++) {
313 if (info->jh7110_set_one_pin_mux)
314 info->jh7110_set_one_pin_mux(sfp,
315 jh7110_pinmux_pin(v),
316 jh7110_pinmux_din(v),
317 jh7110_pinmux_dout(v),
318 jh7110_pinmux_doen(v),
319 jh7110_pinmux_function(v));
325 static const struct pinmux_ops jh7110_pinmux_ops = {
326 .get_functions_count = pinmux_generic_get_function_count,
327 .get_function_name = pinmux_generic_get_function_name,
328 .get_function_groups = pinmux_generic_get_function_groups,
329 .set_mux = jh7110_set_mux,
333 static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 };
335 static u32 jh7110_padcfg_ds_to_mA(u32 padcfg)
337 return jh7110_drive_strength_mA[(padcfg >> 1) & 3U];
340 static u32 jh7110_padcfg_ds_from_mA(u32 v)
344 for (i = 0; i < 3; i++) {
345 if (v <= jh7110_drive_strength_mA[i])
351 static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
352 unsigned int pin, u32 mask, u32 value)
354 const struct jh7110_pinctrl_soc_info *info = sfp->info;
359 if (!info->jh7110_get_padcfg_base)
362 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
366 reg = sfp->base + padcfg_base + 4 * pin;
369 raw_spin_lock_irqsave(&sfp->lock, flags);
370 value |= readl_relaxed(reg) & ~mask;
371 writel_relaxed(value, reg);
372 raw_spin_unlock_irqrestore(&sfp->lock, flags);
375 static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
376 unsigned int pin, unsigned long *config)
378 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
379 const struct jh7110_pinctrl_soc_info *info = sfp->info;
380 int param = pinconf_to_config_param(*config);
385 if (!info->jh7110_get_padcfg_base)
388 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
392 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
394 case PIN_CONFIG_BIAS_DISABLE:
395 enabled = !(padcfg & JH7110_PADCFG_BIAS);
398 case PIN_CONFIG_BIAS_PULL_DOWN:
399 enabled = padcfg & JH7110_PADCFG_PD;
402 case PIN_CONFIG_BIAS_PULL_UP:
403 enabled = padcfg & JH7110_PADCFG_PU;
406 case PIN_CONFIG_DRIVE_STRENGTH:
408 arg = jh7110_padcfg_ds_to_mA(padcfg);
410 case PIN_CONFIG_INPUT_ENABLE:
411 enabled = padcfg & JH7110_PADCFG_IE;
414 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
415 enabled = padcfg & JH7110_PADCFG_SMT;
418 case PIN_CONFIG_SLEW_RATE:
420 arg = !!(padcfg & JH7110_PADCFG_SLEW);
426 *config = pinconf_to_config_packed(param, arg);
427 return enabled ? 0 : -EINVAL;
430 static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,
432 unsigned long *config)
434 const struct group_desc *group;
436 group = pinctrl_generic_get_group(pctldev, gsel);
440 return jh7110_pinconf_get(pctldev, group->pins[0], config);
443 static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
445 unsigned long *configs,
446 unsigned int num_configs)
448 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
449 const struct group_desc *group;
453 group = pinctrl_generic_get_group(pctldev, gsel);
459 for (i = 0; i < num_configs; i++) {
460 int param = pinconf_to_config_param(configs[i]);
461 u32 arg = pinconf_to_config_argument(configs[i]);
464 case PIN_CONFIG_BIAS_DISABLE:
465 mask |= JH7110_PADCFG_BIAS;
466 value &= ~JH7110_PADCFG_BIAS;
468 case PIN_CONFIG_BIAS_PULL_DOWN:
471 mask |= JH7110_PADCFG_BIAS;
472 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD;
474 case PIN_CONFIG_BIAS_PULL_UP:
477 mask |= JH7110_PADCFG_BIAS;
478 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU;
480 case PIN_CONFIG_DRIVE_STRENGTH:
481 mask |= JH7110_PADCFG_DS_MASK;
482 value = (value & ~JH7110_PADCFG_DS_MASK) |
483 jh7110_padcfg_ds_from_mA(arg);
485 case PIN_CONFIG_INPUT_ENABLE:
486 mask |= JH7110_PADCFG_IE;
488 value |= JH7110_PADCFG_IE;
490 value &= ~JH7110_PADCFG_IE;
492 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
493 mask |= JH7110_PADCFG_SMT;
495 value |= JH7110_PADCFG_SMT;
497 value &= ~JH7110_PADCFG_SMT;
499 case PIN_CONFIG_SLEW_RATE:
500 mask |= JH7110_PADCFG_SLEW;
502 value |= JH7110_PADCFG_SLEW;
504 value &= ~JH7110_PADCFG_SLEW;
511 for (i = 0; i < group->num_pins; i++)
512 jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
517 #ifdef CONFIG_DEBUG_FS
518 static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev,
519 struct seq_file *s, unsigned int pin)
521 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
522 const struct jh7110_pinctrl_soc_info *info = sfp->info;
526 if (!info->jh7110_get_padcfg_base)
529 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
533 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
534 seq_printf(s, " (0x%02x)", value);
537 #define jh7110_pinconf_dbg_show NULL
540 static const struct pinconf_ops jh7110_pinconf_ops = {
541 .pin_config_get = jh7110_pinconf_get,
542 .pin_config_group_get = jh7110_pinconf_group_get,
543 .pin_config_group_set = jh7110_pinconf_group_set,
544 .pin_config_dbg_show = jh7110_pinconf_dbg_show,
548 static int jh7110_gpio_get_direction(struct gpio_chip *gc,
551 struct jh7110_pinctrl *sfp = container_of(gc,
552 struct jh7110_pinctrl, gc);
553 const struct jh7110_pinctrl_soc_info *info = sfp->info;
554 unsigned int offset = 4 * (gpio / 4);
555 unsigned int shift = 8 * (gpio % 4);
556 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
558 doen = (doen >> shift) & info->doen_mask;
560 return doen == GPOEN_ENABLE ?
561 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
564 static int jh7110_gpio_direction_input(struct gpio_chip *gc,
567 struct jh7110_pinctrl *sfp = container_of(gc,
568 struct jh7110_pinctrl, gc);
569 const struct jh7110_pinctrl_soc_info *info = sfp->info;
571 /* enable input and schmitt trigger */
572 jh7110_padcfg_rmw(sfp, gpio,
573 JH7110_PADCFG_IE | JH7110_PADCFG_SMT,
574 JH7110_PADCFG_IE | JH7110_PADCFG_SMT);
576 if (info->jh7110_set_one_pin_mux)
577 info->jh7110_set_one_pin_mux(sfp, gpio,
578 GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
583 static int jh7110_gpio_direction_output(struct gpio_chip *gc,
584 unsigned int gpio, int value)
586 struct jh7110_pinctrl *sfp = container_of(gc,
587 struct jh7110_pinctrl, gc);
588 const struct jh7110_pinctrl_soc_info *info = sfp->info;
590 if (info->jh7110_set_one_pin_mux)
591 info->jh7110_set_one_pin_mux(sfp, gpio,
592 GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,
595 /* disable input, schmitt trigger and bias */
596 jh7110_padcfg_rmw(sfp, gpio,
597 JH7110_PADCFG_IE | JH7110_PADCFG_SMT |
598 JH7110_PADCFG_BIAS, 0);
602 static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio)
604 struct jh7110_pinctrl *sfp = container_of(gc,
605 struct jh7110_pinctrl, gc);
606 const struct jh7110_pinctrl_soc_info *info = sfp->info;
607 void __iomem *reg = sfp->base + info->gpioin_reg_base
610 return !!(readl_relaxed(reg) & BIT(gpio % 32));
613 static void jh7110_gpio_set(struct gpio_chip *gc,
614 unsigned int gpio, int value)
616 struct jh7110_pinctrl *sfp = container_of(gc,
617 struct jh7110_pinctrl, gc);
618 const struct jh7110_pinctrl_soc_info *info = sfp->info;
619 unsigned int offset = 4 * (gpio / 4);
620 unsigned int shift = 8 * (gpio % 4);
621 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
622 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
623 u32 mask = info->dout_mask << shift;
626 raw_spin_lock_irqsave(&sfp->lock, flags);
627 dout |= readl_relaxed(reg_dout) & ~mask;
628 writel_relaxed(dout, reg_dout);
629 raw_spin_unlock_irqrestore(&sfp->lock, flags);
632 static int jh7110_gpio_set_config(struct gpio_chip *gc,
633 unsigned int gpio, unsigned long config)
635 struct jh7110_pinctrl *sfp = container_of(gc,
636 struct jh7110_pinctrl, gc);
637 u32 arg = pinconf_to_config_argument(config);
641 switch (pinconf_to_config_param(config)) {
642 case PIN_CONFIG_BIAS_DISABLE:
643 mask = JH7110_PADCFG_BIAS;
646 case PIN_CONFIG_BIAS_PULL_DOWN:
649 mask = JH7110_PADCFG_BIAS;
650 value = JH7110_PADCFG_PD;
652 case PIN_CONFIG_BIAS_PULL_UP:
655 mask = JH7110_PADCFG_BIAS;
656 value = JH7110_PADCFG_PU;
658 case PIN_CONFIG_DRIVE_PUSH_PULL:
660 case PIN_CONFIG_INPUT_ENABLE:
661 mask = JH7110_PADCFG_IE;
662 value = arg ? JH7110_PADCFG_IE : 0;
664 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
665 mask = JH7110_PADCFG_SMT;
666 value = arg ? JH7110_PADCFG_SMT : 0;
672 jh7110_padcfg_rmw(sfp, gpio, mask, value);
676 static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc)
678 struct jh7110_pinctrl *sfp = container_of(gc,
679 struct jh7110_pinctrl, gc);
681 sfp->gpios.name = sfp->gc.label;
682 sfp->gpios.base = sfp->gc.base;
683 sfp->gpios.pin_base = 0;
684 sfp->gpios.npins = sfp->gc.ngpio;
685 sfp->gpios.gc = &sfp->gc;
686 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
690 static void jh7110_irq_ack(struct irq_data *d)
692 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
693 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
694 irq_hw_number_t gpio = irqd_to_hwirq(d);
695 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
697 u32 mask = BIT(gpio % 32);
701 raw_spin_lock_irqsave(&sfp->lock, flags);
702 value = readl_relaxed(ic) & ~mask;
703 writel_relaxed(value, ic);
704 writel_relaxed(value | mask, ic);
705 raw_spin_unlock_irqrestore(&sfp->lock, flags);
708 static void jh7110_irq_mask(struct irq_data *d)
710 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
711 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
712 irq_hw_number_t gpio = irqd_to_hwirq(d);
713 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
715 u32 mask = BIT(gpio % 32);
719 raw_spin_lock_irqsave(&sfp->lock, flags);
720 value = readl_relaxed(ie) & ~mask;
721 writel_relaxed(value, ie);
722 raw_spin_unlock_irqrestore(&sfp->lock, flags);
724 gpiochip_disable_irq(&sfp->gc, d->hwirq);
727 static void jh7110_irq_mask_ack(struct irq_data *d)
729 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
730 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
731 irq_hw_number_t gpio = irqd_to_hwirq(d);
732 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
734 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
736 u32 mask = BIT(gpio % 32);
740 raw_spin_lock_irqsave(&sfp->lock, flags);
741 value = readl_relaxed(ie) & ~mask;
742 writel_relaxed(value, ie);
744 value = readl_relaxed(ic) & ~mask;
745 writel_relaxed(value, ic);
746 writel_relaxed(value | mask, ic);
747 raw_spin_unlock_irqrestore(&sfp->lock, flags);
750 static void jh7110_irq_unmask(struct irq_data *d)
752 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
753 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
754 irq_hw_number_t gpio = irqd_to_hwirq(d);
755 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
757 u32 mask = BIT(gpio % 32);
761 gpiochip_enable_irq(&sfp->gc, d->hwirq);
763 raw_spin_lock_irqsave(&sfp->lock, flags);
764 value = readl_relaxed(ie) | mask;
765 writel_relaxed(value, ie);
766 raw_spin_unlock_irqrestore(&sfp->lock, flags);
769 static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger)
771 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
772 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
773 irq_hw_number_t gpio = irqd_to_hwirq(d);
774 void __iomem *base = sfp->base + 4 * (gpio / 32);
775 u32 mask = BIT(gpio % 32);
776 u32 irq_type, edge_both, polarity;
780 case IRQ_TYPE_EDGE_RISING:
781 irq_type = mask; /* 1: edge triggered */
782 edge_both = 0; /* 0: single edge */
783 polarity = mask; /* 1: rising edge */
785 case IRQ_TYPE_EDGE_FALLING:
786 irq_type = mask; /* 1: edge triggered */
787 edge_both = 0; /* 0: single edge */
788 polarity = 0; /* 0: falling edge */
790 case IRQ_TYPE_EDGE_BOTH:
791 irq_type = mask; /* 1: edge triggered */
792 edge_both = mask; /* 1: both edges */
793 polarity = 0; /* 0: ignored */
795 case IRQ_TYPE_LEVEL_HIGH:
796 irq_type = 0; /* 0: level triggered */
797 edge_both = 0; /* 0: ignored */
798 polarity = mask; /* 1: high level */
800 case IRQ_TYPE_LEVEL_LOW:
801 irq_type = 0; /* 0: level triggered */
802 edge_both = 0; /* 0: ignored */
803 polarity = 0; /* 0: low level */
809 if (trigger & IRQ_TYPE_EDGE_BOTH)
810 irq_set_handler_locked(d, handle_edge_irq);
812 irq_set_handler_locked(d, handle_level_irq);
814 raw_spin_lock_irqsave(&sfp->lock, flags);
815 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;
816 writel_relaxed(irq_type, base + irq_reg->is_reg_base);
818 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;
819 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
821 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;
822 writel_relaxed(polarity, base + irq_reg->iev_reg_base);
823 raw_spin_unlock_irqrestore(&sfp->lock, flags);
827 static struct irq_chip jh7110_irq_chip = {
828 .irq_ack = jh7110_irq_ack,
829 .irq_mask = jh7110_irq_mask,
830 .irq_mask_ack = jh7110_irq_mask_ack,
831 .irq_unmask = jh7110_irq_unmask,
832 .irq_set_type = jh7110_irq_set_type,
833 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
834 GPIOCHIP_IRQ_RESOURCE_HELPERS,
837 static void jh7110_disable_clock(void *data)
839 clk_disable_unprepare(data);
842 int jh7110_pinctrl_probe(struct platform_device *pdev)
844 struct device *dev = &pdev->dev;
845 const struct jh7110_pinctrl_soc_info *info;
846 struct jh7110_pinctrl *sfp;
847 struct pinctrl_desc *jh7110_pinctrl_desc;
848 struct reset_control *rst;
852 info = of_device_get_match_data(&pdev->dev);
856 if (!info->pins || !info->npins) {
857 dev_err(dev, "wrong pinctrl info\n");
861 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
865 #if IS_ENABLED(CONFIG_PM_SLEEP)
866 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,
867 sizeof(*sfp->saved_regs), GFP_KERNEL);
868 if (!sfp->saved_regs)
872 sfp->base = devm_platform_ioremap_resource(pdev, 0);
873 if (IS_ERR(sfp->base))
874 return PTR_ERR(sfp->base);
876 clk = devm_clk_get_optional(dev, NULL);
878 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
880 rst = devm_reset_control_get_exclusive(dev, NULL);
882 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
885 * we don't want to assert reset and risk undoing pin muxing for the
886 * early boot serial console, but let's make sure the reset line is
887 * deasserted in case someone runs a really minimal bootloader.
889 ret = reset_control_deassert(rst);
891 return dev_err_probe(dev, ret, "could not deassert reset\n");
894 ret = clk_prepare_enable(clk);
896 return dev_err_probe(dev, ret, "could not enable clock\n");
898 ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk);
903 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev,
904 sizeof(*jh7110_pinctrl_desc),
906 if (!jh7110_pinctrl_desc)
909 jh7110_pinctrl_desc->name = dev_name(dev);
910 jh7110_pinctrl_desc->pins = info->pins;
911 jh7110_pinctrl_desc->npins = info->npins;
912 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops;
913 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops;
914 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops;
915 jh7110_pinctrl_desc->owner = THIS_MODULE;
919 platform_set_drvdata(pdev, sfp);
920 sfp->gc.parent = dev;
921 raw_spin_lock_init(&sfp->lock);
922 mutex_init(&sfp->mutex);
924 ret = devm_pinctrl_register_and_init(dev,
928 return dev_err_probe(dev, ret,
929 "could not register pinctrl driver\n");
931 sfp->gc.label = dev_name(dev);
932 sfp->gc.owner = THIS_MODULE;
933 sfp->gc.request = pinctrl_gpio_request;
934 sfp->gc.free = pinctrl_gpio_free;
935 sfp->gc.get_direction = jh7110_gpio_get_direction;
936 sfp->gc.direction_input = jh7110_gpio_direction_input;
937 sfp->gc.direction_output = jh7110_gpio_direction_output;
938 sfp->gc.get = jh7110_gpio_get;
939 sfp->gc.set = jh7110_gpio_set;
940 sfp->gc.set_config = jh7110_gpio_set_config;
941 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
942 sfp->gc.base = info->gc_base;
943 sfp->gc.ngpio = info->ngpios;
945 jh7110_irq_chip.name = sfp->gc.label;
946 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
947 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
948 sfp->gc.irq.num_parents = 1;
949 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
950 sizeof(*sfp->gc.irq.parents),
952 if (!sfp->gc.irq.parents)
954 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
955 sfp->gc.irq.handler = handle_bad_irq;
956 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
958 ret = platform_get_irq(pdev, 0);
961 sfp->gc.irq.parents[0] = ret;
963 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
965 return dev_err_probe(dev, ret, "could not register gpiochip\n");
967 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
969 return pinctrl_enable(sfp->pctl);
971 EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe);
973 static int jh7110_pinctrl_suspend(struct device *dev)
975 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
979 raw_spin_lock_irqsave(&sfp->lock, flags);
980 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
981 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i);
983 raw_spin_unlock_irqrestore(&sfp->lock, flags);
987 static int jh7110_pinctrl_resume(struct device *dev)
989 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
993 raw_spin_lock_irqsave(&sfp->lock, flags);
994 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
995 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);
997 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1001 const struct dev_pm_ops jh7110_pinctrl_pm_ops = {
1002 LATE_SYSTEM_SLEEP_PM_OPS(jh7110_pinctrl_suspend, jh7110_pinctrl_resume)
1004 EXPORT_SYMBOL_GPL(jh7110_pinctrl_pm_ops);
1006 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");
1007 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1008 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
1009 MODULE_LICENSE("GPL");