drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl / GPIO driver for StarFive JH7100 SoC
   4  *
   5  * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
   6  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
   7  */
   8
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/io.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reset.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/spinlock.h>
  20
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/pinctrl.h>
  24 #include <linux/pinctrl/pinmux.h>
  25
  26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
  27
  28 #include "../core.h"
  29 #include "../pinctrl-utils.h"
  30 #include "../pinmux.h"
  31 #include "../pinconf.h"
  32
  33 #define DRIVER_NAME "pinctrl-starfive"
  34
  35 /*
  36  * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
  37  * https://github.com/starfive-tech/JH7100_Docs
  38  */
  39 #define NR_GPIOS        64
  40
  41 /*
  42  * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
  43  * are enabled. If set to 0 the GPIO interrupts are disabled.
  44  */
  45 #define GPIOEN          0x000
  46
  47 /*
  48  * The following 32-bit registers come in pairs, but only the offset of the
  49  * first register is defined. The first controls (interrupts for) GPIO 0-31 and
  50  * the second GPIO 32-63.
  51  */
  52
  53 /*
  54  * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
  55  * interrupt is level-triggered.
  56  */
  57 #define GPIOIS          0x010
  58
  59 /*
  60  * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
  61  * both positive and negative edges. If set to 0 the interrupt is triggered by a
  62  * single edge.
  63  */
  64 #define GPIOIBE         0x018
  65
  66 /*
  67  * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
  68  * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
  69  * interrupt is triggered on a falling edge (edge-triggered) or low level
  70  * (level-triggered).
  71  */
  72 #define GPIOIEV         0x020
  73
  74 /*
  75  * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
  76  * the interrupt is disabled (masked). Note that the current documentation is
  77  * wrong and says the exct opposite of this.
  78  */
  79 #define GPIOIE          0x028
  80
  81 /*
  82  * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
  83  * interrupt.
  84  */
  85 #define GPIOIC          0x030
  86
  87 /*
  88  * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
  89  */
  90 #define GPIORIS         0x038
  91
  92 /*
  93  * Interrupt Status after Masking. A 1 means the configured edge or level was
  94  * detected and not masked.
  95  */
  96 #define GPIOMIS         0x040
  97
  98 /*
  99  * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
 100  * a digital 1 and if 0 the pin is a digital 0.
 101  */
 102 #define GPIODIN         0x048
 103
 104 /*
 105  * From the data sheet section 12.2, there are 64 32-bit output data registers
 106  * and 64 output enable registers. Output data and output enable registers for
 107  * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
 108  * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
 109  * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
 110  * and GPOn_DOEN_CFG is 0x54 + 8n.
 111  */
 112 #define GPON_DOUT_CFG   0x050
 113 #define GPON_DOEN_CFG   0x054
 114
 115 /*
 116  * From Section 12.3, there are 75 input signal configuration registers which
 117  * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
 118  * GPI_USB_OVER_CURRENT_CFG 0x378
 119  */
 120 #define GPI_CFG_OFFSET  0x250
 121
 122 /*
 123  * Pad Control Bits. There are 16 pad control bits for each pin located in 103
 124  * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
 125  * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
 126  * bit of each register.
 127  */
 128 #define PAD_SLEW_RATE_MASK              GENMASK(11, 9)
 129 #define PAD_SLEW_RATE_POS               9
 130 #define PAD_BIAS_STRONG_PULL_UP         BIT(8)
 131 #define PAD_INPUT_ENABLE                BIT(7)
 132 #define PAD_INPUT_SCHMITT_ENABLE        BIT(6)
 133 #define PAD_BIAS_DISABLE                BIT(5)
 134 #define PAD_BIAS_PULL_DOWN              BIT(4)
 135 #define PAD_BIAS_MASK \
 136         (PAD_BIAS_STRONG_PULL_UP | \
 137          PAD_BIAS_DISABLE | \
 138          PAD_BIAS_PULL_DOWN)
 139 #define PAD_DRIVE_STRENGTH_MASK         GENMASK(3, 0)
 140 #define PAD_DRIVE_STRENGTH_POS          0
 141
 142 /*
 143  * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
 144  * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
 145  * PAD_GPIO pads. This is a global setting.
 146  */
 147 #define IO_PADSHARE_SEL                 0x1a0
 148
 149 /*
 150  * This just needs to be some number such that when
 151  * sfp->gpio.pin_base = PAD_INVALID_GPIO then
 152  * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
 153  * That is it should underflow and return something >= NR_GPIOS.
 154  */
 155 #define PAD_INVALID_GPIO                0x10000
 156
 157 /*
 158  * The packed pinmux values from the device tree look like this:
 159  *
 160  *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
 161  *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
 162  *
 163  * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
 164  *
 165  *  |      31       | 30 - 8 |   7 - 0   |
 166  *  | dout/doen rev | unused | dout/doen |
 167  */
 168 static unsigned int starfive_pinmux_to_gpio(u32 v)
 169 {
 170         return v & (NR_GPIOS - 1);
 171 }
 172
 173 static u32 starfive_pinmux_to_dout(u32 v)
 174 {
 175         return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
 176 }
 177
 178 static u32 starfive_pinmux_to_doen(u32 v)
 179 {
 180         return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
 181 }
 182
 183 static u32 starfive_pinmux_to_din(u32 v)
 184 {
 185         return (v >> 8) & GENMASK(7, 0);
 186 }
 187
 188 /*
 189  * The maximum GPIO output current depends on the chosen drive strength:
 190  *
 191  *  DS:   0     1     2     3     4     5     6     7
 192  *  mA:  14.2  21.2  28.2  35.2  42.2  49.1  56.0  62.8
 193  *
 194  * After rounding that is 7*DS + 14 mA
 195  */
 196 static u32 starfive_drive_strength_to_max_mA(u16 ds)
 197 {
 198         return 7 * ds + 14;
 199 }
 200
 201 static u16 starfive_drive_strength_from_max_mA(u32 i)
 202 {
 203         return (clamp(i, 14U, 63U) - 14) / 7;
 204 }
 205
 206 struct starfive_pinctrl {
 207         struct gpio_chip gc;
 208         struct pinctrl_gpio_range gpios;
 209         raw_spinlock_t lock;
 210         void __iomem *base;
 211         void __iomem *padctl;
 212         struct pinctrl_dev *pctl;
 213         struct mutex mutex; /* serialize adding groups and functions */
 214 };
 215
 216 static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
 217                                                 unsigned int pin)
 218 {
 219         return pin - sfp->gpios.pin_base;
 220 }
 221
 222 static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
 223                                                 unsigned int gpio)
 224 {
 225         return sfp->gpios.pin_base + gpio;
 226 }
 227
 228 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
 229 {
 230         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 231
 232         return container_of(gc, struct starfive_pinctrl, gc);
 233 }
 234
 235 static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
 236 {
 237         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 238
 239         return container_of(gc, struct starfive_pinctrl, gc);
 240 }
 241
 242 static const struct pinctrl_pin_desc starfive_pins[] = {
 243         PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
 244         PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
 245         PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
 246         PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
 247         PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
 248         PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
 249         PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
 250         PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
 251         PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
 252         PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
 253         PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
 254         PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
 255         PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
 256         PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
 257         PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
 258         PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
 259         PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
 260         PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
 261         PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
 262         PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
 263         PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
 264         PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
 265         PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
 266         PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
 267         PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
 268         PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
 269         PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
 270         PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
 271         PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
 272         PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
 273         PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
 274         PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
 275         PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
 276         PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
 277         PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
 278         PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
 279         PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
 280         PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
 281         PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
 282         PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
 283         PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
 284         PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
 285         PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
 286         PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
 287         PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
 288         PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
 289         PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
 290         PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
 291         PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
 292         PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
 293         PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
 294         PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
 295         PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
 296         PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
 297         PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
 298         PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
 299         PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
 300         PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
 301         PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
 302         PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
 303         PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
 304         PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
 305         PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
 306         PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
 307         PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
 308         PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
 309         PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
 310         PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
 311         PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
 312         PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
 313         PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
 314         PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
 315         PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
 316         PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
 317         PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
 318         PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
 319         PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
 320         PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
 321         PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
 322         PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
 323         PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
 324         PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
 325         PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
 326         PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
 327         PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
 328         PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
 329         PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
 330         PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
 331         PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
 332         PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
 333         PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
 334         PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
 335         PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
 336         PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
 337         PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
 338         PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
 339         PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
 340         PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
 341         PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
 342         PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
 343         PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
 344         PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
 345         PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
 346         PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
 347         PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
 348         PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
 349         PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
 350         PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
 351         PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
 352         PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
 353         PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
 354         PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
 355         PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
 356         PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
 357         PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
 358         PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
 359         PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
 360         PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
 361         PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
 362         PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
 363         PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
 364         PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
 365         PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
 366         PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
 367         PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
 368         PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
 369         PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
 370         PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
 371         PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
 372         PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
 373         PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
 374         PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
 375         PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
 376         PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
 377         PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
 378         PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
 379         PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
 380         PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
 381         PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
 382         PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
 383         PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
 384         PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
 385         PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
 386         PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
 387         PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
 388         PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
 389         PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
 390         PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
 391         PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
 392         PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
 393         PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
 394         PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
 395         PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
 396         PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
 397         PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
 398         PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
 399         PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
 400         PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
 401         PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
 402         PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
 403         PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
 404         PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
 405         PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
 406         PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
 407         PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
 408         PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
 409         PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
 410         PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
 411         PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
 412         PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
 413         PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
 414         PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
 415         PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
 416         PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
 417         PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
 418         PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
 419         PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
 420         PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
 421         PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
 422         PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
 423         PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
 424         PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
 425         PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
 426         PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
 427         PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
 428         PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
 429         PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
 430         PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
 431         PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
 432         PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
 433         PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
 434         PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
 435         PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
 436         PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
 437         PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
 438         PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
 439         PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
 440         PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
 441         PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
 442         PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
 443         PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
 444         PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
 445         PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
 446         PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
 447         PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
 448         PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
 449 };
 450
 451 #ifdef CONFIG_DEBUG_FS
 452 static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
 453                                   struct seq_file *s,
 454                                   unsigned int pin)
 455 {
 456         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 457         unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
 458         void __iomem *reg;
 459         u32 dout, doen;
 460
 461         if (gpio >= NR_GPIOS)
 462                 return;
 463
 464         reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 465         dout = readl_relaxed(reg + 0x000);
 466         doen = readl_relaxed(reg + 0x004);
 467
 468         seq_printf(s, "dout=%lu%s doen=%lu%s",
 469                    dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
 470                    doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
 471 }
 472 #else
 473 #define starfive_pin_dbg_show NULL
 474 #endif
 475
 476 static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
 477                                    struct device_node *np,
 478                                    struct pinctrl_map **maps,
 479                                    unsigned int *num_maps)
 480 {
 481         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 482         struct device *dev = sfp->gc.parent;
 483         struct device_node *child;
 484         struct pinctrl_map *map;
 485         const char **pgnames;
 486         const char *grpname;
 487         u32 *pinmux;
 488         int ngroups;
 489         int *pins;
 490         int nmaps;
 491         int ret;
 492
 493         nmaps = 0;
 494         ngroups = 0;
 495         for_each_available_child_of_node(np, child) {
 496                 int npinmux = of_property_count_u32_elems(child, "pinmux");
 497                 int npins   = of_property_count_u32_elems(child, "pins");
 498
 499                 if (npinmux > 0 && npins > 0) {
 500                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
 501                                 np, child);
 502                         of_node_put(child);
 503                         return -EINVAL;
 504                 }
 505                 if (npinmux == 0 && npins == 0) {
 506                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
 507                                 np, child);
 508                         of_node_put(child);
 509                         return -EINVAL;
 510                 }
 511
 512                 if (npinmux > 0)
 513                         nmaps += 2;
 514                 else
 515                         nmaps += 1;
 516                 ngroups += 1;
 517         }
 518
 519         pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
 520         if (!pgnames)
 521                 return -ENOMEM;
 522
 523         map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
 524         if (!map)
 525                 return -ENOMEM;
 526
 527         nmaps = 0;
 528         ngroups = 0;
 529         mutex_lock(&sfp->mutex);
 530         for_each_available_child_of_node(np, child) {
 531                 int npins;
 532                 int i;
 533
 534                 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
 535                 if (!grpname) {
 536                         ret = -ENOMEM;
 537                         goto put_child;
 538                 }
 539
 540                 pgnames[ngroups++] = grpname;
 541
 542                 if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
 543                         pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
 544                         if (!pins) {
 545                                 ret = -ENOMEM;
 546                                 goto put_child;
 547                         }
 548
 549                         pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
 550                         if (!pinmux) {
 551                                 ret = -ENOMEM;
 552                                 goto put_child;
 553                         }
 554
 555                         ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
 556                         if (ret)
 557                                 goto put_child;
 558
 559                         for (i = 0; i < npins; i++) {
 560                                 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
 561
 562                                 pins[i] = starfive_gpio_to_pin(sfp, gpio);
 563                         }
 564
 565                         map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
 566                         map[nmaps].data.mux.function = np->name;
 567                         map[nmaps].data.mux.group = grpname;
 568                         nmaps += 1;
 569                 } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
 570                         pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
 571                         if (!pins) {
 572                                 ret = -ENOMEM;
 573                                 goto put_child;
 574                         }
 575
 576                         pinmux = NULL;
 577
 578                         for (i = 0; i < npins; i++) {
 579                                 u32 v;
 580
 581                                 ret = of_property_read_u32_index(child, "pins", i, &v);
 582                                 if (ret)
 583                                         goto put_child;
 584                                 pins[i] = v;
 585                         }
 586                 } else {
 587                         ret = -EINVAL;
 588                         goto put_child;
 589                 }
 590
 591                 ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
 592                 if (ret < 0) {
 593                         dev_err(dev, "error adding group %s: %d\n", grpname, ret);
 594                         goto put_child;
 595                 }
 596
 597                 ret = pinconf_generic_parse_dt_config(child, pctldev,
 598                                                       &map[nmaps].data.configs.configs,
 599                                                       &map[nmaps].data.configs.num_configs);
 600                 if (ret) {
 601                         dev_err(dev, "error parsing pin config of group %s: %d\n",
 602                                 grpname, ret);
 603                         goto put_child;
 604                 }
 605
 606                 /* don't create a map if there are no pinconf settings */
 607                 if (map[nmaps].data.configs.num_configs == 0)
 608                         continue;
 609
 610                 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 611                 map[nmaps].data.configs.group_or_pin = grpname;
 612                 nmaps += 1;
 613         }
 614
 615         ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
 616         if (ret < 0) {
 617                 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
 618                 goto free_map;
 619         }
 620
 621         *maps = map;
 622         *num_maps = nmaps;
 623         mutex_unlock(&sfp->mutex);
 624         return 0;
 625
 626 put_child:
 627         of_node_put(child);
 628 free_map:
 629         pinctrl_utils_free_map(pctldev, map, nmaps);
 630         mutex_unlock(&sfp->mutex);
 631         return ret;
 632 }
 633
 634 static const struct pinctrl_ops starfive_pinctrl_ops = {
 635         .get_groups_count = pinctrl_generic_get_group_count,
 636         .get_group_name = pinctrl_generic_get_group_name,
 637         .get_group_pins = pinctrl_generic_get_group_pins,
 638         .pin_dbg_show = starfive_pin_dbg_show,
 639         .dt_node_to_map = starfive_dt_node_to_map,
 640         .dt_free_map = pinctrl_utils_free_map,
 641 };
 642
 643 static int starfive_set_mux(struct pinctrl_dev *pctldev,
 644                             unsigned int fsel, unsigned int gsel)
 645 {
 646         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 647         struct device *dev = sfp->gc.parent;
 648         const struct group_desc *group;
 649         const u32 *pinmux;
 650         unsigned int i;
 651
 652         group = pinctrl_generic_get_group(pctldev, gsel);
 653         if (!group)
 654                 return -EINVAL;
 655
 656         pinmux = group->data;
 657         for (i = 0; i < group->grp.npins; i++) {
 658                 u32 v = pinmux[i];
 659                 unsigned int gpio = starfive_pinmux_to_gpio(v);
 660                 u32 dout = starfive_pinmux_to_dout(v);
 661                 u32 doen = starfive_pinmux_to_doen(v);
 662                 u32 din = starfive_pinmux_to_din(v);
 663                 void __iomem *reg_dout;
 664                 void __iomem *reg_doen;
 665                 void __iomem *reg_din;
 666                 unsigned long flags;
 667
 668                 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
 669                         gpio, dout, doen, din);
 670
 671                 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 672                 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 673                 if (din != GPI_NONE)
 674                         reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
 675                 else
 676                         reg_din = NULL;
 677
 678                 raw_spin_lock_irqsave(&sfp->lock, flags);
 679                 writel_relaxed(dout, reg_dout);
 680                 writel_relaxed(doen, reg_doen);
 681                 if (reg_din)
 682                         writel_relaxed(gpio + 2, reg_din);
 683                 raw_spin_unlock_irqrestore(&sfp->lock, flags);
 684         }
 685
 686         return 0;
 687 }
 688
 689 static const struct pinmux_ops starfive_pinmux_ops = {
 690         .get_functions_count = pinmux_generic_get_function_count,
 691         .get_function_name = pinmux_generic_get_function_name,
 692         .get_function_groups = pinmux_generic_get_function_groups,
 693         .set_mux = starfive_set_mux,
 694         .strict = true,
 695 };
 696
 697 static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
 698                                unsigned int pin)
 699 {
 700         void __iomem *reg = sfp->padctl + 4 * (pin / 2);
 701         int shift = 16 * (pin % 2);
 702
 703         return readl_relaxed(reg) >> shift;
 704 }
 705
 706 static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
 707                                 unsigned int pin,
 708                                 u16 _mask, u16 _value)
 709 {
 710         void __iomem *reg = sfp->padctl + 4 * (pin / 2);
 711         int shift = 16 * (pin % 2);
 712         u32 mask = (u32)_mask << shift;
 713         u32 value = (u32)_value << shift;
 714         unsigned long flags;
 715
 716         dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
 717
 718         raw_spin_lock_irqsave(&sfp->lock, flags);
 719         value |= readl_relaxed(reg) & ~mask;
 720         writel_relaxed(value, reg);
 721         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 722 }
 723
 724 #define PIN_CONFIG_STARFIVE_STRONG_PULL_UP      (PIN_CONFIG_END + 1)
 725
 726 static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
 727         { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
 728 };
 729
 730 #ifdef CONFIG_DEBUG_FS
 731 static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
 732         PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
 733 };
 734
 735 static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
 736               ARRAY_SIZE(starfive_pinconf_custom_params));
 737 #else
 738 #define starfive_pinconf_custom_conf_items NULL
 739 #endif
 740
 741 static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
 742                                 unsigned int pin, unsigned long *config)
 743 {
 744         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 745         int param = pinconf_to_config_param(*config);
 746         u16 value = starfive_padctl_get(sfp, pin);
 747         bool enabled;
 748         u32 arg;
 749
 750         switch (param) {
 751         case PIN_CONFIG_BIAS_DISABLE:
 752                 enabled = value & PAD_BIAS_DISABLE;
 753                 arg = 0;
 754                 break;
 755         case PIN_CONFIG_BIAS_PULL_DOWN:
 756                 enabled = value & PAD_BIAS_PULL_DOWN;
 757                 arg = 1;
 758                 break;
 759         case PIN_CONFIG_BIAS_PULL_UP:
 760                 enabled = !(value & PAD_BIAS_MASK);
 761                 arg = 1;
 762                 break;
 763         case PIN_CONFIG_DRIVE_STRENGTH:
 764                 enabled = value & PAD_DRIVE_STRENGTH_MASK;
 765                 arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
 766                 break;
 767         case PIN_CONFIG_INPUT_ENABLE:
 768                 enabled = value & PAD_INPUT_ENABLE;
 769                 arg = enabled;
 770                 break;
 771         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 772                 enabled = value & PAD_INPUT_SCHMITT_ENABLE;
 773                 arg = enabled;
 774                 break;
 775         case PIN_CONFIG_SLEW_RATE:
 776                 enabled = value & PAD_SLEW_RATE_MASK;
 777                 arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
 778                 break;
 779         case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
 780                 enabled = value & PAD_BIAS_STRONG_PULL_UP;
 781                 arg = enabled;
 782                 break;
 783         default:
 784                 return -ENOTSUPP;
 785         }
 786
 787         *config = pinconf_to_config_packed(param, arg);
 788         return enabled ? 0 : -EINVAL;
 789 }
 790
 791 static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
 792                                       unsigned int gsel, unsigned long *config)
 793 {
 794         const struct group_desc *group;
 795
 796         group = pinctrl_generic_get_group(pctldev, gsel);
 797         if (!group)
 798                 return -EINVAL;
 799
 800         return starfive_pinconf_get(pctldev, group->grp.pins[0], config);
 801 }
 802
 803 static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
 804                                       unsigned int gsel,
 805                                       unsigned long *configs,
 806                                       unsigned int num_configs)
 807 {
 808         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 809         const struct group_desc *group;
 810         u16 mask, value;
 811         int i;
 812
 813         group = pinctrl_generic_get_group(pctldev, gsel);
 814         if (!group)
 815                 return -EINVAL;
 816
 817         mask = 0;
 818         value = 0;
 819         for (i = 0; i < num_configs; i++) {
 820                 int param = pinconf_to_config_param(configs[i]);
 821                 u32 arg = pinconf_to_config_argument(configs[i]);
 822
 823                 switch (param) {
 824                 case PIN_CONFIG_BIAS_DISABLE:
 825                         mask |= PAD_BIAS_MASK;
 826                         value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
 827                         break;
 828                 case PIN_CONFIG_BIAS_PULL_DOWN:
 829                         if (arg == 0)
 830                                 return -ENOTSUPP;
 831                         mask |= PAD_BIAS_MASK;
 832                         value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
 833                         break;
 834                 case PIN_CONFIG_BIAS_PULL_UP:
 835                         if (arg == 0)
 836                                 return -ENOTSUPP;
 837                         mask |= PAD_BIAS_MASK;
 838                         value = value & ~PAD_BIAS_MASK;
 839                         break;
 840                 case PIN_CONFIG_DRIVE_STRENGTH:
 841                         mask |= PAD_DRIVE_STRENGTH_MASK;
 842                         value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
 843                                 starfive_drive_strength_from_max_mA(arg);
 844                         break;
 845                 case PIN_CONFIG_INPUT_ENABLE:
 846                         mask |= PAD_INPUT_ENABLE;
 847                         if (arg)
 848                                 value |= PAD_INPUT_ENABLE;
 849                         else
 850                                 value &= ~PAD_INPUT_ENABLE;
 851                         break;
 852                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 853                         mask |= PAD_INPUT_SCHMITT_ENABLE;
 854                         if (arg)
 855                                 value |= PAD_INPUT_SCHMITT_ENABLE;
 856                         else
 857                                 value &= ~PAD_INPUT_SCHMITT_ENABLE;
 858                         break;
 859                 case PIN_CONFIG_SLEW_RATE:
 860                         mask |= PAD_SLEW_RATE_MASK;
 861                         value = (value & ~PAD_SLEW_RATE_MASK) |
 862                                 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
 863                         break;
 864                 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
 865                         if (arg) {
 866                                 mask |= PAD_BIAS_MASK;
 867                                 value = (value & ~PAD_BIAS_MASK) |
 868                                         PAD_BIAS_STRONG_PULL_UP;
 869                         } else {
 870                                 mask |= PAD_BIAS_STRONG_PULL_UP;
 871                                 value = value & ~PAD_BIAS_STRONG_PULL_UP;
 872                         }
 873                         break;
 874                 default:
 875                         return -ENOTSUPP;
 876                 }
 877         }
 878
 879         for (i = 0; i < group->grp.npins; i++)
 880                 starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value);
 881
 882         return 0;
 883 }
 884
 885 #ifdef CONFIG_DEBUG_FS
 886 static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 887                                       struct seq_file *s, unsigned int pin)
 888 {
 889         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 890         u16 value = starfive_padctl_get(sfp, pin);
 891
 892         seq_printf(s, " (0x%03x)", value);
 893 }
 894 #else
 895 #define starfive_pinconf_dbg_show NULL
 896 #endif
 897
 898 static const struct pinconf_ops starfive_pinconf_ops = {
 899         .pin_config_get = starfive_pinconf_get,
 900         .pin_config_group_get = starfive_pinconf_group_get,
 901         .pin_config_group_set = starfive_pinconf_group_set,
 902         .pin_config_dbg_show = starfive_pinconf_dbg_show,
 903         .is_generic = true,
 904 };
 905
 906 static struct pinctrl_desc starfive_desc = {
 907         .name = DRIVER_NAME,
 908         .pins = starfive_pins,
 909         .npins = ARRAY_SIZE(starfive_pins),
 910         .pctlops = &starfive_pinctrl_ops,
 911         .pmxops = &starfive_pinmux_ops,
 912         .confops = &starfive_pinconf_ops,
 913         .owner = THIS_MODULE,
 914         .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
 915         .custom_params = starfive_pinconf_custom_params,
 916         .custom_conf_items = starfive_pinconf_custom_conf_items,
 917 };
 918
 919 static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
 920 {
 921         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 922         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 923
 924         if (readl_relaxed(doen) == GPO_ENABLE)
 925                 return GPIO_LINE_DIRECTION_OUT;
 926
 927         return GPIO_LINE_DIRECTION_IN;
 928 }
 929
 930 static int starfive_gpio_direction_input(struct gpio_chip *gc,
 931                                          unsigned int gpio)
 932 {
 933         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 934         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 935         unsigned long flags;
 936
 937         /* enable input and schmitt trigger */
 938         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
 939                             PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
 940                             PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
 941
 942         raw_spin_lock_irqsave(&sfp->lock, flags);
 943         writel_relaxed(GPO_DISABLE, doen);
 944         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 945         return 0;
 946 }
 947
 948 static int starfive_gpio_direction_output(struct gpio_chip *gc,
 949                                           unsigned int gpio, int value)
 950 {
 951         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 952         void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 953         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 954         unsigned long flags;
 955
 956         raw_spin_lock_irqsave(&sfp->lock, flags);
 957         writel_relaxed(value, dout);
 958         writel_relaxed(GPO_ENABLE, doen);
 959         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 960
 961         /* disable input, schmitt trigger and bias */
 962         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
 963                             PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
 964                             PAD_BIAS_DISABLE);
 965
 966         return 0;
 967 }
 968
 969 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 970 {
 971         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 972         void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
 973
 974         return !!(readl_relaxed(din) & BIT(gpio % 32));
 975 }
 976
 977 static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
 978                               int value)
 979 {
 980         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 981         void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 982         unsigned long flags;
 983
 984         raw_spin_lock_irqsave(&sfp->lock, flags);
 985         writel_relaxed(value, dout);
 986         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 987 }
 988
 989 static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
 990                                     unsigned long config)
 991 {
 992         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 993         u32 arg = pinconf_to_config_argument(config);
 994         u16 value;
 995         u16 mask;
 996
 997         switch (pinconf_to_config_param(config)) {
 998         case PIN_CONFIG_BIAS_DISABLE:
 999                 mask  = PAD_BIAS_MASK;
1000                 value = PAD_BIAS_DISABLE;
1001                 break;
1002         case PIN_CONFIG_BIAS_PULL_DOWN:
1003                 if (arg == 0)
1004                         return -ENOTSUPP;
1005                 mask  = PAD_BIAS_MASK;
1006                 value = PAD_BIAS_PULL_DOWN;
1007                 break;
1008         case PIN_CONFIG_BIAS_PULL_UP:
1009                 if (arg == 0)
1010                         return -ENOTSUPP;
1011                 mask  = PAD_BIAS_MASK;
1012                 value = 0;
1013                 break;
1014         case PIN_CONFIG_DRIVE_PUSH_PULL:
1015                 return 0;
1016         case PIN_CONFIG_INPUT_ENABLE:
1017                 mask  = PAD_INPUT_ENABLE;
1018                 value = arg ? PAD_INPUT_ENABLE : 0;
1019                 break;
1020         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1021                 mask  = PAD_INPUT_SCHMITT_ENABLE;
1022                 value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
1023                 break;
1024         default:
1025                 return -ENOTSUPP;
1026         }
1027
1028         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1029         return 0;
1030 }
1031
1032 static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
1033 {
1034         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1035
1036         sfp->gpios.name = sfp->gc.label;
1037         sfp->gpios.base = sfp->gc.base;
1038         /*
1039          * sfp->gpios.pin_base depends on the chosen signal group
1040          * and is set in starfive_probe()
1041          */
1042         sfp->gpios.npins = NR_GPIOS;
1043         sfp->gpios.gc = &sfp->gc;
1044         pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1045         return 0;
1046 }
1047
1048 static void starfive_irq_ack(struct irq_data *d)
1049 {
1050         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1051         irq_hw_number_t gpio = irqd_to_hwirq(d);
1052         void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1053         u32 mask = BIT(gpio % 32);
1054         unsigned long flags;
1055
1056         raw_spin_lock_irqsave(&sfp->lock, flags);
1057         writel_relaxed(mask, ic);
1058         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1059 }
1060
1061 static void starfive_irq_mask(struct irq_data *d)
1062 {
1063         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1064         irq_hw_number_t gpio = irqd_to_hwirq(d);
1065         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1066         u32 mask = BIT(gpio % 32);
1067         unsigned long flags;
1068         u32 value;
1069
1070         raw_spin_lock_irqsave(&sfp->lock, flags);
1071         value = readl_relaxed(ie) & ~mask;
1072         writel_relaxed(value, ie);
1073         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1074
1075         gpiochip_disable_irq(&sfp->gc, gpio);
1076 }
1077
1078 static void starfive_irq_mask_ack(struct irq_data *d)
1079 {
1080         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1081         irq_hw_number_t gpio = irqd_to_hwirq(d);
1082         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1083         void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1084         u32 mask = BIT(gpio % 32);
1085         unsigned long flags;
1086         u32 value;
1087
1088         raw_spin_lock_irqsave(&sfp->lock, flags);
1089         value = readl_relaxed(ie) & ~mask;
1090         writel_relaxed(value, ie);
1091         writel_relaxed(mask, ic);
1092         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1093 }
1094
1095 static void starfive_irq_unmask(struct irq_data *d)
1096 {
1097         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1098         irq_hw_number_t gpio = irqd_to_hwirq(d);
1099         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1100         u32 mask = BIT(gpio % 32);
1101         unsigned long flags;
1102         u32 value;
1103
1104         gpiochip_enable_irq(&sfp->gc, gpio);
1105
1106         raw_spin_lock_irqsave(&sfp->lock, flags);
1107         value = readl_relaxed(ie) | mask;
1108         writel_relaxed(value, ie);
1109         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1110 }
1111
1112 static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
1113 {
1114         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1115         irq_hw_number_t gpio = irqd_to_hwirq(d);
1116         void __iomem *base = sfp->base + 4 * (gpio / 32);
1117         u32 mask = BIT(gpio % 32);
1118         u32 irq_type, edge_both, polarity;
1119         unsigned long flags;
1120
1121         switch (trigger) {
1122         case IRQ_TYPE_EDGE_RISING:
1123                 irq_type  = mask; /* 1: edge triggered */
1124                 edge_both = 0;    /* 0: single edge */
1125                 polarity  = mask; /* 1: rising edge */
1126                 break;
1127         case IRQ_TYPE_EDGE_FALLING:
1128                 irq_type  = mask; /* 1: edge triggered */
1129                 edge_both = 0;    /* 0: single edge */
1130                 polarity  = 0;    /* 0: falling edge */
1131                 break;
1132         case IRQ_TYPE_EDGE_BOTH:
1133                 irq_type  = mask; /* 1: edge triggered */
1134                 edge_both = mask; /* 1: both edges */
1135                 polarity  = 0;    /* 0: ignored */
1136                 break;
1137         case IRQ_TYPE_LEVEL_HIGH:
1138                 irq_type  = 0;    /* 0: level triggered */
1139                 edge_both = 0;    /* 0: ignored */
1140                 polarity  = mask; /* 1: high level */
1141                 break;
1142         case IRQ_TYPE_LEVEL_LOW:
1143                 irq_type  = 0;    /* 0: level triggered */
1144                 edge_both = 0;    /* 0: ignored */
1145                 polarity  = 0;    /* 0: low level */
1146                 break;
1147         default:
1148                 return -EINVAL;
1149         }
1150
1151         if (trigger & IRQ_TYPE_EDGE_BOTH)
1152                 irq_set_handler_locked(d, handle_edge_irq);
1153         else
1154                 irq_set_handler_locked(d, handle_level_irq);
1155
1156         raw_spin_lock_irqsave(&sfp->lock, flags);
1157         irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
1158         writel_relaxed(irq_type, base + GPIOIS);
1159         edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
1160         writel_relaxed(edge_both, base + GPIOIBE);
1161         polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
1162         writel_relaxed(polarity, base + GPIOIEV);
1163         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1164         return 0;
1165 }
1166
1167 static const struct irq_chip starfive_irq_chip = {
1168         .name = "StarFive GPIO",
1169         .irq_ack = starfive_irq_ack,
1170         .irq_mask = starfive_irq_mask,
1171         .irq_mask_ack = starfive_irq_mask_ack,
1172         .irq_unmask = starfive_irq_unmask,
1173         .irq_set_type = starfive_irq_set_type,
1174         .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1175         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1176 };
1177
1178 static void starfive_gpio_irq_handler(struct irq_desc *desc)
1179 {
1180         struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1181         struct irq_chip *chip = irq_desc_get_chip(desc);
1182         unsigned long mis;
1183         unsigned int pin;
1184
1185         chained_irq_enter(chip, desc);
1186
1187         mis = readl_relaxed(sfp->base + GPIOMIS + 0);
1188         for_each_set_bit(pin, &mis, 32)
1189                 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1190
1191         mis = readl_relaxed(sfp->base + GPIOMIS + 4);
1192         for_each_set_bit(pin, &mis, 32)
1193                 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
1194
1195         chained_irq_exit(chip, desc);
1196 }
1197
1198 static int starfive_gpio_init_hw(struct gpio_chip *gc)
1199 {
1200         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1201
1202         /* mask all GPIO interrupts */
1203         writel(0, sfp->base + GPIOIE + 0);
1204         writel(0, sfp->base + GPIOIE + 4);
1205         /* clear edge interrupt flags */
1206         writel(~0U, sfp->base + GPIOIC + 0);
1207         writel(~0U, sfp->base + GPIOIC + 4);
1208         /* enable GPIO interrupts */
1209         writel(1, sfp->base + GPIOEN);
1210         return 0;
1211 }
1212
1213 static void starfive_disable_clock(void *data)
1214 {
1215         clk_disable_unprepare(data);
1216 }
1217
1218 static int starfive_probe(struct platform_device *pdev)
1219 {
1220         struct device *dev = &pdev->dev;
1221         struct starfive_pinctrl *sfp;
1222         struct reset_control *rst;
1223         struct clk *clk;
1224         u32 value;
1225         int ret;
1226
1227         sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1228         if (!sfp)
1229                 return -ENOMEM;
1230
1231         sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
1232         if (IS_ERR(sfp->base))
1233                 return PTR_ERR(sfp->base);
1234
1235         sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
1236         if (IS_ERR(sfp->padctl))
1237                 return PTR_ERR(sfp->padctl);
1238
1239         clk = devm_clk_get(dev, NULL);
1240         if (IS_ERR(clk))
1241                 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1242
1243         rst = devm_reset_control_get_exclusive(dev, NULL);
1244         if (IS_ERR(rst))
1245                 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1246
1247         ret = clk_prepare_enable(clk);
1248         if (ret)
1249                 return dev_err_probe(dev, ret, "could not enable clock\n");
1250
1251         ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
1252         if (ret)
1253                 return ret;
1254
1255         /*
1256          * We don't want to assert reset and risk undoing pin muxing for the
1257          * early boot serial console, but let's make sure the reset line is
1258          * deasserted in case someone runs a really minimal bootloader.
1259          */
1260         ret = reset_control_deassert(rst);
1261         if (ret)
1262                 return dev_err_probe(dev, ret, "could not deassert reset\n");
1263
1264         platform_set_drvdata(pdev, sfp);
1265         sfp->gc.parent = dev;
1266         raw_spin_lock_init(&sfp->lock);
1267         mutex_init(&sfp->mutex);
1268
1269         ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
1270         if (ret)
1271                 return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
1272
1273         if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
1274                 if (value > 6)
1275                         return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1276                 writel(value, sfp->padctl + IO_PADSHARE_SEL);
1277         }
1278
1279         value = readl(sfp->padctl + IO_PADSHARE_SEL);
1280         switch (value) {
1281         case 0:
1282                 sfp->gpios.pin_base = PAD_INVALID_GPIO;
1283                 goto out_pinctrl_enable;
1284         case 1:
1285                 sfp->gpios.pin_base = PAD_GPIO(0);
1286                 break;
1287         case 2:
1288                 sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
1289                 break;
1290         case 3:
1291                 sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
1292                 break;
1293         case 4: case 5: case 6:
1294                 sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
1295                 break;
1296         default:
1297                 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1298         }
1299
1300         sfp->gc.label = dev_name(dev);
1301         sfp->gc.owner = THIS_MODULE;
1302         sfp->gc.request = pinctrl_gpio_request;
1303         sfp->gc.free = pinctrl_gpio_free;
1304         sfp->gc.get_direction = starfive_gpio_get_direction;
1305         sfp->gc.direction_input = starfive_gpio_direction_input;
1306         sfp->gc.direction_output = starfive_gpio_direction_output;
1307         sfp->gc.get = starfive_gpio_get;
1308         sfp->gc.set = starfive_gpio_set;
1309         sfp->gc.set_config = starfive_gpio_set_config;
1310         sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1311         sfp->gc.base = -1;
1312         sfp->gc.ngpio = NR_GPIOS;
1313
1314         gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
1315         sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
1316         sfp->gc.irq.num_parents = 1;
1317         sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1318                                            sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
1319         if (!sfp->gc.irq.parents)
1320                 return -ENOMEM;
1321         sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1322         sfp->gc.irq.handler = handle_bad_irq;
1323         sfp->gc.irq.init_hw = starfive_gpio_init_hw;
1324
1325         ret = platform_get_irq(pdev, 0);
1326         if (ret < 0)
1327                 return ret;
1328         sfp->gc.irq.parents[0] = ret;
1329
1330         ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1331         if (ret)
1332                 return dev_err_probe(dev, ret, "could not register gpiochip\n");
1333
1334         irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1335
1336 out_pinctrl_enable:
1337         return pinctrl_enable(sfp->pctl);
1338 }
1339
1340 static const struct of_device_id starfive_of_match[] = {
1341         { .compatible = "starfive,jh7100-pinctrl" },
1342         { /* sentinel */ }
1343 };
1344 MODULE_DEVICE_TABLE(of, starfive_of_match);
1345
1346 static struct platform_driver starfive_pinctrl_driver = {
1347         .probe = starfive_probe,
1348         .driver = {
1349                 .name = DRIVER_NAME,
1350                 .of_match_table = starfive_of_match,
1351         },
1352 };
1353 module_platform_driver(starfive_pinctrl_driver);
1354
1355 MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
1356 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1357 MODULE_LICENSE("GPL v2");