2 * pinmux driver for CSR SiRFprimaII
5 * Rongjun Ying <rongjun.ying@csr.com>
6 * Yuping Luo <yuping.luo@csr.com>
7 * Barry Song <baohua.song@csr.com>
9 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
12 * Licensed under GPLv2 or later.
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/of_platform.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_gpio.h>
33 #include "pinctrl-sirf.h"
35 #define DRIVER_NAME "pinmux-sirf"
37 struct sirfsoc_gpio_bank {
43 struct sirfsoc_gpio_chip {
44 struct of_mm_gpio_chip chip;
45 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
49 static struct sirfsoc_pin_group *sirfsoc_pin_groups;
50 static int sirfsoc_pingrp_cnt;
52 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
54 return sirfsoc_pingrp_cnt;
57 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
60 return sirfsoc_pin_groups[selector].name;
63 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
65 const unsigned **pins,
68 *pins = sirfsoc_pin_groups[selector].pins;
69 *num_pins = sirfsoc_pin_groups[selector].num_pins;
73 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
74 struct seq_file *s, unsigned offset)
76 seq_printf(s, " " DRIVER_NAME);
79 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
80 struct device_node *np_config,
81 struct pinctrl_map **map, unsigned *num_maps)
83 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
84 struct device_node *np;
85 struct property *prop;
86 const char *function, *group;
87 int ret, index = 0, count = 0;
89 /* calculate number of maps required */
90 for_each_child_of_node(np_config, np) {
91 ret = of_property_read_string(np, "sirf,function", &function);
97 ret = of_property_count_strings(np, "sirf,pins");
107 dev_err(spmx->dev, "No child nodes passed via DT\n");
111 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
115 for_each_child_of_node(np_config, np) {
116 of_property_read_string(np, "sirf,function", &function);
117 of_property_for_each_string(np, "sirf,pins", prop, group) {
118 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
119 (*map)[index].data.mux.group = group;
120 (*map)[index].data.mux.function = function;
130 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
131 struct pinctrl_map *map, unsigned num_maps)
136 static const struct pinctrl_ops sirfsoc_pctrl_ops = {
137 .get_groups_count = sirfsoc_get_groups_count,
138 .get_group_name = sirfsoc_get_group_name,
139 .get_group_pins = sirfsoc_get_group_pins,
140 .pin_dbg_show = sirfsoc_pin_dbg_show,
141 .dt_node_to_map = sirfsoc_dt_node_to_map,
142 .dt_free_map = sirfsoc_dt_free_map,
145 static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
146 static int sirfsoc_pmxfunc_cnt;
148 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
149 unsigned selector, bool enable)
152 const struct sirfsoc_padmux *mux =
153 sirfsoc_pmx_functions[selector].padmux;
154 const struct sirfsoc_muxmask *mask = mux->muxmask;
156 for (i = 0; i < mux->muxmask_counts; i++) {
158 muxval = readl(spmx->gpio_virtbase +
159 SIRFSOC_GPIO_PAD_EN(mask[i].group));
161 muxval = muxval & ~mask[i].mask;
163 muxval = muxval | mask[i].mask;
164 writel(muxval, spmx->gpio_virtbase +
165 SIRFSOC_GPIO_PAD_EN(mask[i].group));
168 if (mux->funcmask && enable) {
172 readl(spmx->rsc_virtbase + mux->ctrlreg);
174 (func_en_val & ~mux->funcmask) | (mux->funcval);
175 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
179 static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
183 struct sirfsoc_pmx *spmx;
185 spmx = pinctrl_dev_get_drvdata(pmxdev);
186 sirfsoc_pinmux_endisable(spmx, selector, true);
191 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
193 return sirfsoc_pmxfunc_cnt;
196 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
199 return sirfsoc_pmx_functions[selector].name;
202 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
204 const char * const **groups,
205 unsigned * const num_groups)
207 *groups = sirfsoc_pmx_functions[selector].groups;
208 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
212 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
213 struct pinctrl_gpio_range *range, unsigned offset)
215 struct sirfsoc_pmx *spmx;
217 int group = range->id;
221 spmx = pinctrl_dev_get_drvdata(pmxdev);
223 muxval = readl(spmx->gpio_virtbase +
224 SIRFSOC_GPIO_PAD_EN(group));
225 muxval = muxval | (1 << (offset - range->pin_base));
226 writel(muxval, spmx->gpio_virtbase +
227 SIRFSOC_GPIO_PAD_EN(group));
232 static const struct pinmux_ops sirfsoc_pinmux_ops = {
233 .set_mux = sirfsoc_pinmux_set_mux,
234 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
235 .get_function_name = sirfsoc_pinmux_get_func_name,
236 .get_function_groups = sirfsoc_pinmux_get_groups,
237 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
240 static struct pinctrl_desc sirfsoc_pinmux_desc = {
242 .pctlops = &sirfsoc_pctrl_ops,
243 .pmxops = &sirfsoc_pinmux_ops,
244 .owner = THIS_MODULE,
247 static void __iomem *sirfsoc_rsc_of_iomap(void)
249 const struct of_device_id rsc_ids[] = {
250 { .compatible = "sirf,prima2-rsc" },
253 struct device_node *np;
255 np = of_find_matching_node(NULL, rsc_ids);
257 panic("unable to find compatible rsc node in dtb\n");
259 return of_iomap(np, 0);
262 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
263 const struct of_phandle_args *gpiospec,
266 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
270 *flags = gpiospec->args[1];
272 return gpiospec->args[0];
275 static const struct of_device_id pinmux_ids[] = {
276 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
277 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
281 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
284 struct sirfsoc_pmx *spmx;
285 struct device_node *np = pdev->dev.of_node;
286 const struct sirfsoc_pinctrl_data *pdata;
288 /* Create state holders etc for this driver */
289 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
293 spmx->dev = &pdev->dev;
295 platform_set_drvdata(pdev, spmx);
297 spmx->gpio_virtbase = of_iomap(np, 0);
298 if (!spmx->gpio_virtbase) {
299 dev_err(&pdev->dev, "can't map gpio registers\n");
303 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
304 if (!spmx->rsc_virtbase) {
306 dev_err(&pdev->dev, "can't map rsc registers\n");
307 goto out_no_rsc_remap;
310 pdata = of_match_node(pinmux_ids, np)->data;
311 sirfsoc_pin_groups = pdata->grps;
312 sirfsoc_pingrp_cnt = pdata->grps_cnt;
313 sirfsoc_pmx_functions = pdata->funcs;
314 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
315 sirfsoc_pinmux_desc.pins = pdata->pads;
316 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
319 /* Now register the pin controller and all pins it handles */
320 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
321 if (IS_ERR(spmx->pmx)) {
322 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
323 ret = PTR_ERR(spmx->pmx);
327 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
332 iounmap(spmx->rsc_virtbase);
334 iounmap(spmx->gpio_virtbase);
338 #ifdef CONFIG_PM_SLEEP
339 static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
342 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
344 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
345 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
346 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
347 SIRFSOC_GPIO_CTRL(i, j));
349 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
350 SIRFSOC_GPIO_INT_STATUS(i));
351 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
352 SIRFSOC_GPIO_PAD_EN(i));
354 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
356 for (i = 0; i < 3; i++)
357 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
362 static int sirfsoc_pinmux_resume_noirq(struct device *dev)
365 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
367 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
368 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
369 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
370 SIRFSOC_GPIO_CTRL(i, j));
372 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
373 SIRFSOC_GPIO_INT_STATUS(i));
374 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
375 SIRFSOC_GPIO_PAD_EN(i));
377 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
379 for (i = 0; i < 3; i++)
380 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
385 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
386 .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
387 .resume_noirq = sirfsoc_pinmux_resume_noirq,
388 .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
389 .restore_noirq = sirfsoc_pinmux_resume_noirq,
393 static struct platform_driver sirfsoc_pinmux_driver = {
396 .of_match_table = pinmux_ids,
397 #ifdef CONFIG_PM_SLEEP
398 .pm = &sirfsoc_pinmux_pm_ops,
401 .probe = sirfsoc_pinmux_probe,
404 static int __init sirfsoc_pinmux_init(void)
406 return platform_driver_register(&sirfsoc_pinmux_driver);
408 arch_initcall(sirfsoc_pinmux_init);
410 static inline struct sirfsoc_gpio_bank *
411 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
413 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
416 static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
418 return offset % SIRFSOC_GPIO_BANK_SIZE;
421 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
423 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
424 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
425 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
426 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
430 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
432 spin_lock_irqsave(&sgpio->lock, flags);
434 val = readl(sgpio->chip.regs + offset);
436 writel(val, sgpio->chip.regs + offset);
438 spin_unlock_irqrestore(&sgpio->lock, flags);
441 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
442 struct sirfsoc_gpio_bank *bank,
448 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
450 spin_lock_irqsave(&sgpio->lock, flags);
452 val = readl(sgpio->chip.regs + offset);
453 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
454 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
455 writel(val, sgpio->chip.regs + offset);
457 spin_unlock_irqrestore(&sgpio->lock, flags);
460 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
462 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
463 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
464 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
466 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
469 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
471 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
472 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
473 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
474 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
478 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
480 spin_lock_irqsave(&sgpio->lock, flags);
482 val = readl(sgpio->chip.regs + offset);
483 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
484 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
485 writel(val, sgpio->chip.regs + offset);
487 spin_unlock_irqrestore(&sgpio->lock, flags);
490 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
492 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
493 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
494 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
495 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
499 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
501 spin_lock_irqsave(&sgpio->lock, flags);
503 val = readl(sgpio->chip.regs + offset);
504 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
509 case IRQ_TYPE_EDGE_RISING:
510 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
511 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
512 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
514 case IRQ_TYPE_EDGE_FALLING:
515 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
516 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
517 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
519 case IRQ_TYPE_EDGE_BOTH:
520 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
521 SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
522 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
524 case IRQ_TYPE_LEVEL_LOW:
525 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
526 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
527 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
529 case IRQ_TYPE_LEVEL_HIGH:
530 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
531 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
532 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
536 writel(val, sgpio->chip.regs + offset);
538 spin_unlock_irqrestore(&sgpio->lock, flags);
543 static struct irq_chip sirfsoc_irq_chip = {
544 .name = "sirf-gpio-irq",
545 .irq_ack = sirfsoc_gpio_irq_ack,
546 .irq_mask = sirfsoc_gpio_irq_mask,
547 .irq_unmask = sirfsoc_gpio_irq_unmask,
548 .irq_set_type = sirfsoc_gpio_irq_type,
551 static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
553 unsigned int irq = irq_desc_get_irq(desc);
554 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
555 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
556 struct sirfsoc_gpio_bank *bank;
559 struct irq_chip *chip = irq_desc_get_chip(desc);
562 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
563 bank = &sgpio->sgpio_bank[i];
564 if (bank->parent_irq == irq)
567 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
569 chained_irq_enter(chip, desc);
571 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
574 "%s: gpio id %d status %#x no interrupt is flagged\n",
575 __func__, bank->id, status);
576 handle_bad_irq(desc);
581 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
584 * Here we must check whether the corresponding GPIO's interrupt
585 * has been enabled, otherwise just skip it
587 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
588 pr_debug("%s: gpio id %d idx %d happens\n",
589 __func__, bank->id, idx);
590 generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
591 bank->id * SIRFSOC_GPIO_BANK_SIZE));
595 status = status >> 1;
598 chained_irq_exit(chip, desc);
601 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
602 unsigned ctrl_offset)
606 val = readl(sgpio->chip.regs + ctrl_offset);
607 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
608 writel(val, sgpio->chip.regs + ctrl_offset);
611 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
613 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
614 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
617 if (pinctrl_gpio_request(chip->base + offset))
620 spin_lock_irqsave(&bank->lock, flags);
624 * set direction as input and mask irq
626 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
627 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
629 spin_unlock_irqrestore(&bank->lock, flags);
634 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
636 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
637 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
640 spin_lock_irqsave(&bank->lock, flags);
642 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
643 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
645 spin_unlock_irqrestore(&bank->lock, flags);
647 pinctrl_gpio_free(chip->base + offset);
650 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
652 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
653 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
654 int idx = sirfsoc_gpio_to_bankoff(gpio);
658 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
660 spin_lock_irqsave(&bank->lock, flags);
662 sirfsoc_gpio_set_input(sgpio, offset);
664 spin_unlock_irqrestore(&bank->lock, flags);
669 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
670 struct sirfsoc_gpio_bank *bank,
677 spin_lock_irqsave(&bank->lock, flags);
679 out_ctrl = readl(sgpio->chip.regs + offset);
681 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
683 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
685 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
686 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
687 writel(out_ctrl, sgpio->chip.regs + offset);
689 spin_unlock_irqrestore(&bank->lock, flags);
692 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
693 unsigned gpio, int value)
695 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
696 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
697 int idx = sirfsoc_gpio_to_bankoff(gpio);
701 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
703 spin_lock_irqsave(&sgpio->lock, flags);
705 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
707 spin_unlock_irqrestore(&sgpio->lock, flags);
712 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
714 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
715 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
719 spin_lock_irqsave(&bank->lock, flags);
721 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
723 spin_unlock_irqrestore(&bank->lock, flags);
725 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
728 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
731 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
732 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
736 spin_lock_irqsave(&bank->lock, flags);
738 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
740 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
742 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
743 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
745 spin_unlock_irqrestore(&bank->lock, flags);
748 static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
752 const unsigned long *p = (const unsigned long *)pullups;
754 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
755 for_each_set_bit(n, p + i, BITS_PER_LONG) {
756 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
757 u32 val = readl(sgpio->chip.regs + offset);
758 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
759 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
760 writel(val, sgpio->chip.regs + offset);
765 static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
766 const u32 *pulldowns)
769 const unsigned long *p = (const unsigned long *)pulldowns;
771 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
772 for_each_set_bit(n, p + i, BITS_PER_LONG) {
773 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
774 u32 val = readl(sgpio->chip.regs + offset);
775 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
776 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
777 writel(val, sgpio->chip.regs + offset);
782 static int sirfsoc_gpio_probe(struct device_node *np)
785 static struct sirfsoc_gpio_chip *sgpio;
786 struct sirfsoc_gpio_bank *bank;
788 struct platform_device *pdev;
790 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
792 pdev = of_find_device_by_node(np);
796 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
799 spin_lock_init(&sgpio->lock);
801 regs = of_iomap(np, 0);
805 sgpio->chip.gc.request = sirfsoc_gpio_request;
806 sgpio->chip.gc.free = sirfsoc_gpio_free;
807 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
808 sgpio->chip.gc.get = sirfsoc_gpio_get_value;
809 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
810 sgpio->chip.gc.set = sirfsoc_gpio_set_value;
811 sgpio->chip.gc.base = 0;
812 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
813 sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
814 sgpio->chip.gc.of_node = np;
815 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
816 sgpio->chip.gc.of_gpio_n_cells = 2;
817 sgpio->chip.gc.parent = &pdev->dev;
818 sgpio->chip.regs = regs;
820 err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
822 dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
827 err = gpiochip_irqchip_add(&sgpio->chip.gc,
833 "could not connect irqchip to gpiochip\n");
837 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
838 bank = &sgpio->sgpio_bank[i];
839 spin_lock_init(&bank->lock);
840 bank->parent_irq = platform_get_irq(pdev, i);
841 if (bank->parent_irq < 0) {
842 err = bank->parent_irq;
846 gpiochip_set_chained_irqchip(&sgpio->chip.gc,
849 sirfsoc_gpio_handle_irq);
852 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
853 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
856 "could not add gpiochip pin range\n");
860 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
861 SIRFSOC_GPIO_NO_OF_BANKS))
862 sirfsoc_gpio_set_pullup(sgpio, pullups);
864 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
865 SIRFSOC_GPIO_NO_OF_BANKS))
866 sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
872 gpiochip_remove(&sgpio->chip.gc);
878 static int __init sirfsoc_gpio_init(void)
881 struct device_node *np;
883 np = of_find_matching_node(NULL, pinmux_ids);
888 return sirfsoc_gpio_probe(np);
890 subsys_initcall(sirfsoc_gpio_init);