2 * SuperH Pin Function Controller Support
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/bug.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/stringify.h>
26 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
27 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
28 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
29 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
30 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
31 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
40 #define SH_PFC_PIN_GROUP(n) \
45 .nr_pins = ARRAY_SIZE(n##_pins), \
48 struct sh_pfc_pin_group {
50 const unsigned int *pins;
51 const unsigned int *mux;
55 #define SH_PFC_FUNCTION(n) \
58 .groups = n##_groups, \
59 .nr_groups = ARRAY_SIZE(n##_groups), \
62 struct sh_pfc_function {
64 const char * const *groups;
65 unsigned int nr_groups;
73 struct pinmux_cfg_reg {
75 u8 reg_width, field_width;
77 const u8 *var_field_width;
80 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
81 .reg = r, .reg_width = r_width, .field_width = f_width, \
82 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
84 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
85 .reg = r, .reg_width = r_width, \
86 .var_field_width = (const u8 [r_width]) \
87 { var_fw0, var_fwn, 0 }, \
88 .enum_ids = (const u16 [])
90 struct pinmux_data_reg {
96 #define PINMUX_DATA_REG(name, r, r_width) \
97 .reg = r, .reg_width = r_width, \
98 .enum_ids = (const u16 [r_width]) \
104 #define PINMUX_IRQ(ids...) \
105 { .gpios = (const short []) { ids, -1 } }
107 struct pinmux_range {
115 struct sh_pfc_soc_operations {
116 int (*init)(struct sh_pfc *pfc);
117 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
118 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
120 int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
121 int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
125 struct sh_pfc_soc_info {
127 const struct sh_pfc_soc_operations *ops;
129 struct pinmux_range input;
130 struct pinmux_range output;
131 struct pinmux_range function;
133 const struct sh_pfc_pin *pins;
134 unsigned int nr_pins;
135 const struct sh_pfc_pin_group *groups;
136 unsigned int nr_groups;
137 const struct sh_pfc_function *functions;
138 unsigned int nr_functions;
141 const struct pinmux_func *func_gpios;
142 unsigned int nr_func_gpios;
145 const struct pinmux_cfg_reg *cfg_regs;
146 const struct pinmux_data_reg *data_regs;
148 const u16 *gpio_data;
149 unsigned int gpio_data_size;
151 const struct pinmux_irq *gpio_irq;
152 unsigned int gpio_irq_size;
157 /* -----------------------------------------------------------------------------
158 * Helper macros to create pin and port lists
162 * sh_pfc_soc_info gpio_data array macros
165 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
167 #define PINMUX_IPSR_NOGP(ispr, fn) \
168 PINMUX_DATA(fn##_MARK, FN_##fn)
169 #define PINMUX_IPSR_DATA(ipsr, fn) \
170 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
171 #define PINMUX_IPSR_NOGM(ispr, fn, ms) \
172 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
173 #define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
174 PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
175 #define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
176 PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
179 * GP port style (32 ports banks)
182 #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
184 #define PORT_GP_32(bank, fn, sfx) \
185 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
186 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
187 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
188 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
189 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
190 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
191 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
192 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
193 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
194 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
195 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
196 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
197 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
198 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
199 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
200 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
202 #define PORT_GP_32_REV(bank, fn, sfx) \
203 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
204 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
205 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
206 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
207 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
208 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
209 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
210 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
211 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
212 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
213 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
214 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
215 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
216 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
217 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
218 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
220 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
221 #define _GP_ALL(bank, pin, name, sfx) name##_##sfx
222 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
224 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
225 #define _GP_GPIO(bank, _pin, _name, sfx) \
227 .pin = (bank * 32) + _pin, \
228 .name = __stringify(_name), \
229 .enum_id = _name##_DATA, \
231 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
233 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
234 #define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN)
235 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
238 * PORT style (linear pin space)
241 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
243 #define PORT_10(pn, fn, pfx, sfx) \
244 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
245 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
246 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
247 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
248 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
250 #define PORT_90(pn, fn, pfx, sfx) \
251 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
252 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
253 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
254 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
255 PORT_10(pn+90, fn, pfx##9, sfx)
257 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
258 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
259 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
261 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
262 #define PINMUX_GPIO(_pin) \
265 .name = __stringify(GPIO_##_pin), \
266 .enum_id = _pin##_DATA, \
269 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
270 #define SH_PFC_PIN_CFG(_pin, cfgs) \
273 .name = __stringify(PORT##_pin), \
274 .enum_id = PORT##_pin##_DATA, \
278 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
279 #define SH_PFC_PIN_NAMED(row, col, _name) \
281 .pin = PIN_NUMBER(row, col), \
282 .name = __stringify(PIN_##_name), \
283 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
286 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
287 * PORT_name_OUT, PORT_name_IN marks
289 #define _PORT_DATA(pn, pfx, sfx) \
290 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
291 PORT##pfx##_OUT, PORT##pfx##_IN)
292 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
294 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
295 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
296 [gpio - (base)] = { \
297 .name = __stringify(gpio), \
298 .enum_id = data_or_mark, \
300 #define GPIO_FN(str) \
301 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
306 #define PORTCR(nr, reg) \
308 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
309 /* PULMD[1:0], handled by .set_bias() */ \
312 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
313 /* SEC, not supported */ \
316 PORT##nr##_FN0, PORT##nr##_FN1, \
317 PORT##nr##_FN2, PORT##nr##_FN3, \
318 PORT##nr##_FN4, PORT##nr##_FN5, \
319 PORT##nr##_FN6, PORT##nr##_FN7 \
323 #endif /* __SH_PFC_H */