1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Pin Function Controller pinmux support.
5 * Copyright (C) 2012 Paul Mundt
8 #define DRV_NAME "sh-pfc"
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/pinctrl/machine.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
26 #include "../pinconf.h"
28 struct sh_pfc_pin_config {
29 unsigned int mux_mark;
34 struct sh_pfc_pinctrl {
35 struct pinctrl_dev *pctl;
36 struct pinctrl_desc pctl_desc;
40 struct pinctrl_pin_desc *pins;
41 struct sh_pfc_pin_config *configs;
43 const char *func_prop_name;
44 const char *groups_prop_name;
45 const char *pins_prop_name;
48 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
50 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
52 return pmx->pfc->info->nr_groups;
55 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
58 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
60 return pmx->pfc->info->groups[selector].name;
63 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
64 const unsigned **pins, unsigned *num_pins)
66 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
68 *pins = pmx->pfc->info->groups[selector].pins;
69 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
74 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
77 seq_puts(s, DRV_NAME);
81 static int sh_pfc_map_add_config(struct pinctrl_map *map,
82 const char *group_or_pin,
83 enum pinctrl_map_type type,
84 unsigned long *configs,
85 unsigned int num_configs)
89 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
95 map->data.configs.group_or_pin = group_or_pin;
96 map->data.configs.configs = cfgs;
97 map->data.configs.num_configs = num_configs;
102 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
103 struct device_node *np,
104 struct pinctrl_map **map,
105 unsigned int *num_maps, unsigned int *index)
107 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
108 struct device *dev = pmx->pfc->dev;
109 struct pinctrl_map *maps = *map;
110 unsigned int nmaps = *num_maps;
111 unsigned int idx = *index;
112 unsigned int num_configs;
113 const char *function = NULL;
114 unsigned long *configs;
115 struct property *prop;
116 unsigned int num_groups;
117 unsigned int num_pins;
122 /* Support both the old Renesas-specific properties and the new standard
123 * properties. Mixing old and new properties isn't allowed, neither
124 * inside a subnode nor across subnodes.
126 if (!pmx->func_prop_name) {
127 if (of_find_property(np, "groups", NULL) ||
128 of_find_property(np, "pins", NULL)) {
129 pmx->func_prop_name = "function";
130 pmx->groups_prop_name = "groups";
131 pmx->pins_prop_name = "pins";
133 pmx->func_prop_name = "renesas,function";
134 pmx->groups_prop_name = "renesas,groups";
135 pmx->pins_prop_name = "renesas,pins";
139 /* Parse the function and configuration properties. At least a function
140 * or one configuration must be specified.
142 ret = of_property_read_string(np, pmx->func_prop_name, &function);
143 if (ret < 0 && ret != -EINVAL) {
144 dev_err(dev, "Invalid function in DT\n");
148 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
152 if (!function && num_configs == 0) {
154 "DT node must contain at least a function or config\n");
159 /* Count the number of pins and groups and reallocate mappings. */
160 ret = of_property_count_strings(np, pmx->pins_prop_name);
161 if (ret == -EINVAL) {
163 } else if (ret < 0) {
164 dev_err(dev, "Invalid pins list in DT\n");
170 ret = of_property_count_strings(np, pmx->groups_prop_name);
171 if (ret == -EINVAL) {
173 } else if (ret < 0) {
174 dev_err(dev, "Invalid pin groups list in DT\n");
180 if (!num_pins && !num_groups) {
181 dev_err(dev, "No pin or group provided in DT node\n");
189 nmaps += num_pins + num_groups;
191 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
200 /* Iterate over pins and groups and create the mappings. */
201 of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
203 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
204 maps[idx].data.mux.group = group;
205 maps[idx].data.mux.function = function;
210 ret = sh_pfc_map_add_config(&maps[idx], group,
211 PIN_MAP_TYPE_CONFIGS_GROUP,
212 configs, num_configs);
225 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
226 ret = sh_pfc_map_add_config(&maps[idx], pin,
227 PIN_MAP_TYPE_CONFIGS_PIN,
228 configs, num_configs);
241 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
242 struct pinctrl_map *map, unsigned num_maps)
249 for (i = 0; i < num_maps; ++i) {
250 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
251 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
252 kfree(map[i].data.configs.configs);
258 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
259 struct device_node *np,
260 struct pinctrl_map **map, unsigned *num_maps)
262 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
263 struct device *dev = pmx->pfc->dev;
264 struct device_node *child;
272 for_each_child_of_node(np, child) {
273 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
281 /* If no mapping has been found in child nodes try the config node. */
282 if (*num_maps == 0) {
283 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
292 dev_err(dev, "no mapping found in node %pOF\n", np);
297 sh_pfc_dt_free_map(pctldev, *map, *num_maps);
301 #endif /* CONFIG_OF */
303 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
304 .get_groups_count = sh_pfc_get_groups_count,
305 .get_group_name = sh_pfc_get_group_name,
306 .get_group_pins = sh_pfc_get_group_pins,
307 .pin_dbg_show = sh_pfc_pin_dbg_show,
309 .dt_node_to_map = sh_pfc_dt_node_to_map,
310 .dt_free_map = sh_pfc_dt_free_map,
314 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
316 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
318 return pmx->pfc->info->nr_functions;
321 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
324 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
326 return pmx->pfc->info->functions[selector].name;
329 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
331 const char * const **groups,
332 unsigned * const num_groups)
334 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
336 *groups = pmx->pfc->info->functions[selector].groups;
337 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
342 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
345 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
346 struct sh_pfc *pfc = pmx->pfc;
347 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
352 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
354 spin_lock_irqsave(&pfc->lock, flags);
356 for (i = 0; i < grp->nr_pins; ++i) {
357 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
358 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
361 * This driver cannot manage both gpio and mux when the gpio
362 * pin is already enabled. So, this function fails.
364 if (cfg->gpio_enabled) {
369 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
374 /* All group pins are configured, mark the pins as mux_set */
375 for (i = 0; i < grp->nr_pins; ++i) {
376 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
377 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
380 cfg->mux_mark = grp->mux[i];
384 spin_unlock_irqrestore(&pfc->lock, flags);
388 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
389 struct pinctrl_gpio_range *range,
392 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
393 struct sh_pfc *pfc = pmx->pfc;
394 int idx = sh_pfc_get_pin_index(pfc, offset);
395 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
399 spin_lock_irqsave(&pfc->lock, flags);
402 /* If GPIOs are handled externally the pin mux type need to be
405 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
407 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
412 cfg->gpio_enabled = true;
417 spin_unlock_irqrestore(&pfc->lock, flags);
422 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
423 struct pinctrl_gpio_range *range,
426 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
427 struct sh_pfc *pfc = pmx->pfc;
428 int idx = sh_pfc_get_pin_index(pfc, offset);
429 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
432 spin_lock_irqsave(&pfc->lock, flags);
433 cfg->gpio_enabled = false;
434 /* If mux is already set, this configures it here */
436 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
437 spin_unlock_irqrestore(&pfc->lock, flags);
440 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
441 struct pinctrl_gpio_range *range,
442 unsigned offset, bool input)
444 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
445 struct sh_pfc *pfc = pmx->pfc;
446 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
447 int idx = sh_pfc_get_pin_index(pfc, offset);
448 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
453 /* Check if the requested direction is supported by the pin. Not all SoC
454 * provide pin config data, so perform the check conditionally.
457 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
458 if (!(pin->configs & dir))
462 spin_lock_irqsave(&pfc->lock, flags);
464 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
469 spin_unlock_irqrestore(&pfc->lock, flags);
473 static const struct pinmux_ops sh_pfc_pinmux_ops = {
474 .get_functions_count = sh_pfc_get_functions_count,
475 .get_function_name = sh_pfc_get_function_name,
476 .get_function_groups = sh_pfc_get_function_groups,
477 .set_mux = sh_pfc_func_set_mux,
478 .gpio_request_enable = sh_pfc_gpio_request_enable,
479 .gpio_disable_free = sh_pfc_gpio_disable_free,
480 .gpio_set_direction = sh_pfc_gpio_set_direction,
483 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
484 unsigned int pin, unsigned int *offset, unsigned int *size)
486 const struct pinmux_drive_reg_field *field;
487 const struct pinmux_drive_reg *reg;
490 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
491 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
492 field = ®->fields[i];
494 if (field->size && field->pin == pin) {
495 *offset = field->offset;
506 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
515 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
519 spin_lock_irqsave(&pfc->lock, flags);
520 val = sh_pfc_read(pfc, reg);
521 spin_unlock_irqrestore(&pfc->lock, flags);
523 val = (val >> offset) & GENMASK(size - 1, 0);
525 /* Convert the value to mA based on a full drive strength value of 24mA.
526 * We can make the full value configurable later if needed.
528 return (val + 1) * (size == 2 ? 6 : 3);
531 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
532 unsigned int pin, u16 strength)
541 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
545 step = size == 2 ? 6 : 3;
547 if (strength < step || strength > 24)
550 /* Convert the value from mA based on a full drive strength value of
551 * 24mA. We can make the full value configurable later if needed.
553 strength = strength / step - 1;
555 spin_lock_irqsave(&pfc->lock, flags);
557 val = sh_pfc_read(pfc, reg);
558 val &= ~GENMASK(offset + size - 1, offset);
559 val |= strength << offset;
561 sh_pfc_write(pfc, reg, val);
563 spin_unlock_irqrestore(&pfc->lock, flags);
568 /* Check whether the requested parameter is supported for a pin. */
569 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
570 enum pin_config_param param)
572 int idx = sh_pfc_get_pin_index(pfc, _pin);
573 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
576 case PIN_CONFIG_BIAS_DISABLE:
577 return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
579 case PIN_CONFIG_BIAS_PULL_UP:
580 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
582 case PIN_CONFIG_BIAS_PULL_DOWN:
583 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
585 case PIN_CONFIG_DRIVE_STRENGTH:
586 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
588 case PIN_CONFIG_POWER_SOURCE:
589 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
596 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
597 unsigned long *config)
599 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
600 struct sh_pfc *pfc = pmx->pfc;
601 enum pin_config_param param = pinconf_to_config_param(*config);
605 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
609 case PIN_CONFIG_BIAS_DISABLE:
610 case PIN_CONFIG_BIAS_PULL_UP:
611 case PIN_CONFIG_BIAS_PULL_DOWN: {
614 if (!pfc->info->ops || !pfc->info->ops->get_bias)
617 spin_lock_irqsave(&pfc->lock, flags);
618 bias = pfc->info->ops->get_bias(pfc, _pin);
619 spin_unlock_irqrestore(&pfc->lock, flags);
628 case PIN_CONFIG_DRIVE_STRENGTH: {
631 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
639 case PIN_CONFIG_POWER_SOURCE: {
643 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
646 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
647 if (WARN(bit < 0, "invalid pin %#x", _pin))
650 spin_lock_irqsave(&pfc->lock, flags);
651 val = sh_pfc_read(pfc, pocctrl);
652 spin_unlock_irqrestore(&pfc->lock, flags);
654 arg = (val & BIT(bit)) ? 3300 : 1800;
662 *config = pinconf_to_config_packed(param, arg);
666 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
667 unsigned long *configs, unsigned num_configs)
669 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
670 struct sh_pfc *pfc = pmx->pfc;
671 enum pin_config_param param;
675 for (i = 0; i < num_configs; i++) {
676 param = pinconf_to_config_param(configs[i]);
678 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
682 case PIN_CONFIG_BIAS_PULL_UP:
683 case PIN_CONFIG_BIAS_PULL_DOWN:
684 case PIN_CONFIG_BIAS_DISABLE:
685 if (!pfc->info->ops || !pfc->info->ops->set_bias)
688 spin_lock_irqsave(&pfc->lock, flags);
689 pfc->info->ops->set_bias(pfc, _pin, param);
690 spin_unlock_irqrestore(&pfc->lock, flags);
694 case PIN_CONFIG_DRIVE_STRENGTH: {
696 pinconf_to_config_argument(configs[i]);
699 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
706 case PIN_CONFIG_POWER_SOURCE: {
707 unsigned int mV = pinconf_to_config_argument(configs[i]);
711 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
714 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
715 if (WARN(bit < 0, "invalid pin %#x", _pin))
718 if (mV != 1800 && mV != 3300)
721 spin_lock_irqsave(&pfc->lock, flags);
722 val = sh_pfc_read(pfc, pocctrl);
727 sh_pfc_write(pfc, pocctrl, val);
728 spin_unlock_irqrestore(&pfc->lock, flags);
736 } /* for each config */
741 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
742 unsigned long *configs,
743 unsigned num_configs)
745 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
746 const unsigned int *pins;
747 unsigned int num_pins;
750 pins = pmx->pfc->info->groups[group].pins;
751 num_pins = pmx->pfc->info->groups[group].nr_pins;
753 for (i = 0; i < num_pins; ++i) {
754 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
762 static const struct pinconf_ops sh_pfc_pinconf_ops = {
764 .pin_config_get = sh_pfc_pinconf_get,
765 .pin_config_set = sh_pfc_pinconf_set,
766 .pin_config_group_set = sh_pfc_pinconf_group_set,
767 .pin_config_config_dbg_show = pinconf_generic_dump_config,
770 /* PFC ranges -> pinctrl pin descs */
771 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
775 /* Allocate and initialize the pins and configs arrays. */
776 pmx->pins = devm_kcalloc(pfc->dev,
777 pfc->info->nr_pins, sizeof(*pmx->pins),
779 if (unlikely(!pmx->pins))
782 pmx->configs = devm_kcalloc(pfc->dev,
783 pfc->info->nr_pins, sizeof(*pmx->configs),
785 if (unlikely(!pmx->configs))
788 for (i = 0; i < pfc->info->nr_pins; ++i) {
789 const struct sh_pfc_pin *info = &pfc->info->pins[i];
790 struct pinctrl_pin_desc *pin = &pmx->pins[i];
792 /* If the pin number is equal to -1 all pins are considered */
793 pin->number = info->pin != (u16)-1 ? info->pin : i;
794 pin->name = info->name;
800 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
802 struct sh_pfc_pinctrl *pmx;
805 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
811 ret = sh_pfc_map_pins(pfc, pmx);
815 pmx->pctl_desc.name = DRV_NAME;
816 pmx->pctl_desc.owner = THIS_MODULE;
817 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
818 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
819 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
820 pmx->pctl_desc.pins = pmx->pins;
821 pmx->pctl_desc.npins = pfc->info->nr_pins;
823 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
826 dev_err(pfc->dev, "could not register: %i\n", ret);
831 return pinctrl_enable(pmx->pctl);