drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7795 ES1.x processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2015-2017  Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9
  10 #include "core.h"
  11 #include "sh_pfc.h"
  12
  13 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  14                    SH_PFC_PIN_CFG_PULL_UP | \
  15                    SH_PFC_PIN_CFG_PULL_DOWN)
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  19         PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),  \
  20         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  21         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  22         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  23         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  24         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  25         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  26         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  27         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  30 /*
  31  * F_() : just information
  32  * FM() : macro for FN_xxx / xxx_MARK
  33  */
  34
  35 /* GPSR0 */
  36 #define GPSR0_15        F_(D15,                 IP7_11_8)
  37 #define GPSR0_14        F_(D14,                 IP7_7_4)
  38 #define GPSR0_13        F_(D13,                 IP7_3_0)
  39 #define GPSR0_12        F_(D12,                 IP6_31_28)
  40 #define GPSR0_11        F_(D11,                 IP6_27_24)
  41 #define GPSR0_10        F_(D10,                 IP6_23_20)
  42 #define GPSR0_9         F_(D9,                  IP6_19_16)
  43 #define GPSR0_8         F_(D8,                  IP6_15_12)
  44 #define GPSR0_7         F_(D7,                  IP6_11_8)
  45 #define GPSR0_6         F_(D6,                  IP6_7_4)
  46 #define GPSR0_5         F_(D5,                  IP6_3_0)
  47 #define GPSR0_4         F_(D4,                  IP5_31_28)
  48 #define GPSR0_3         F_(D3,                  IP5_27_24)
  49 #define GPSR0_2         F_(D2,                  IP5_23_20)
  50 #define GPSR0_1         F_(D1,                  IP5_19_16)
  51 #define GPSR0_0         F_(D0,                  IP5_15_12)
  52
  53 /* GPSR1 */
  54 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  55 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  56 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  57 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  58 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  59 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  60 #define GPSR1_21        F_(CS1_N_A26,           IP4_19_16)
  61 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  62 #define GPSR1_19        F_(A19,                 IP4_11_8)
  63 #define GPSR1_18        F_(A18,                 IP4_7_4)
  64 #define GPSR1_17        F_(A17,                 IP4_3_0)
  65 #define GPSR1_16        F_(A16,                 IP3_31_28)
  66 #define GPSR1_15        F_(A15,                 IP3_27_24)
  67 #define GPSR1_14        F_(A14,                 IP3_23_20)
  68 #define GPSR1_13        F_(A13,                 IP3_19_16)
  69 #define GPSR1_12        F_(A12,                 IP3_15_12)
  70 #define GPSR1_11        F_(A11,                 IP3_11_8)
  71 #define GPSR1_10        F_(A10,                 IP3_7_4)
  72 #define GPSR1_9         F_(A9,                  IP3_3_0)
  73 #define GPSR1_8         F_(A8,                  IP2_31_28)
  74 #define GPSR1_7         F_(A7,                  IP2_27_24)
  75 #define GPSR1_6         F_(A6,                  IP2_23_20)
  76 #define GPSR1_5         F_(A5,                  IP2_19_16)
  77 #define GPSR1_4         F_(A4,                  IP2_15_12)
  78 #define GPSR1_3         F_(A3,                  IP2_11_8)
  79 #define GPSR1_2         F_(A2,                  IP2_7_4)
  80 #define GPSR1_1         F_(A1,                  IP2_3_0)
  81 #define GPSR1_0         F_(A0,                  IP1_31_28)
  82
  83 /* GPSR2 */
  84 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  85 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  86 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  87 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  88 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  89 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  90 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  91 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
  92 #define GPSR2_6         F_(PWM0,                IP1_19_16)
  93 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
  94 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
  95 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
  96 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
  97 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
  98 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
  99
 100 /* GPSR3 */
 101 #define GPSR3_15        F_(SD1_WP,              IP10_23_20)
 102 #define GPSR3_14        F_(SD1_CD,              IP10_19_16)
 103 #define GPSR3_13        F_(SD0_WP,              IP10_15_12)
 104 #define GPSR3_12        F_(SD0_CD,              IP10_11_8)
 105 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 106 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 107 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 108 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 109 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 110 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 111 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 112 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 113 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 114 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 115 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 116 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 117
 118 /* GPSR4 */
 119 #define GPSR4_17        FM(SD3_DS)
 120 #define GPSR4_16        F_(SD3_DAT7,            IP10_7_4)
 121 #define GPSR4_15        F_(SD3_DAT6,            IP10_3_0)
 122 #define GPSR4_14        F_(SD3_DAT5,            IP9_31_28)
 123 #define GPSR4_13        F_(SD3_DAT4,            IP9_27_24)
 124 #define GPSR4_12        FM(SD3_DAT3)
 125 #define GPSR4_11        FM(SD3_DAT2)
 126 #define GPSR4_10        FM(SD3_DAT1)
 127 #define GPSR4_9         FM(SD3_DAT0)
 128 #define GPSR4_8         FM(SD3_CMD)
 129 #define GPSR4_7         FM(SD3_CLK)
 130 #define GPSR4_6         F_(SD2_DS,              IP9_23_20)
 131 #define GPSR4_5         F_(SD2_DAT3,            IP9_19_16)
 132 #define GPSR4_4         F_(SD2_DAT2,            IP9_15_12)
 133 #define GPSR4_3         F_(SD2_DAT1,            IP9_11_8)
 134 #define GPSR4_2         F_(SD2_DAT0,            IP9_7_4)
 135 #define GPSR4_1         FM(SD2_CMD)
 136 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 137
 138 /* GPSR5 */
 139 #define GPSR5_25        F_(MLB_DAT,             IP13_19_16)
 140 #define GPSR5_24        F_(MLB_SIG,             IP13_15_12)
 141 #define GPSR5_23        F_(MLB_CLK,             IP13_11_8)
 142 #define GPSR5_22        FM(MSIOF0_RXD)
 143 #define GPSR5_21        F_(MSIOF0_SS2,          IP13_7_4)
 144 #define GPSR5_20        FM(MSIOF0_TXD)
 145 #define GPSR5_19        F_(MSIOF0_SS1,          IP13_3_0)
 146 #define GPSR5_18        F_(MSIOF0_SYNC,         IP12_31_28)
 147 #define GPSR5_17        FM(MSIOF0_SCK)
 148 #define GPSR5_16        F_(HRTS0_N,             IP12_27_24)
 149 #define GPSR5_15        F_(HCTS0_N,             IP12_23_20)
 150 #define GPSR5_14        F_(HTX0,                IP12_19_16)
 151 #define GPSR5_13        F_(HRX0,                IP12_15_12)
 152 #define GPSR5_12        F_(HSCK0,               IP12_11_8)
 153 #define GPSR5_11        F_(RX2_A,               IP12_7_4)
 154 #define GPSR5_10        F_(TX2_A,               IP12_3_0)
 155 #define GPSR5_9         F_(SCK2,                IP11_31_28)
 156 #define GPSR5_8         F_(RTS1_N_TANS,         IP11_27_24)
 157 #define GPSR5_7         F_(CTS1_N,              IP11_23_20)
 158 #define GPSR5_6         F_(TX1_A,               IP11_19_16)
 159 #define GPSR5_5         F_(RX1_A,               IP11_15_12)
 160 #define GPSR5_4         F_(RTS0_N_TANS,         IP11_11_8)
 161 #define GPSR5_3         F_(CTS0_N,              IP11_7_4)
 162 #define GPSR5_2         F_(TX0,                 IP11_3_0)
 163 #define GPSR5_1         F_(RX0,                 IP10_31_28)
 164 #define GPSR5_0         F_(SCK0,                IP10_27_24)
 165
 166 /* GPSR6 */
 167 #define GPSR6_31        F_(USB31_OVC,           IP17_7_4)
 168 #define GPSR6_30        F_(USB31_PWEN,          IP17_3_0)
 169 #define GPSR6_29        F_(USB30_OVC,           IP16_31_28)
 170 #define GPSR6_28        F_(USB30_PWEN,          IP16_27_24)
 171 #define GPSR6_27        F_(USB1_OVC,            IP16_23_20)
 172 #define GPSR6_26        F_(USB1_PWEN,           IP16_19_16)
 173 #define GPSR6_25        F_(USB0_OVC,            IP16_15_12)
 174 #define GPSR6_24        F_(USB0_PWEN,           IP16_11_8)
 175 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP16_7_4)
 176 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP16_3_0)
 177 #define GPSR6_21        F_(SSI_SDATA9_A,        IP15_31_28)
 178 #define GPSR6_20        F_(SSI_SDATA8,          IP15_27_24)
 179 #define GPSR6_19        F_(SSI_SDATA7,          IP15_23_20)
 180 #define GPSR6_18        F_(SSI_WS78,            IP15_19_16)
 181 #define GPSR6_17        F_(SSI_SCK78,           IP15_15_12)
 182 #define GPSR6_16        F_(SSI_SDATA6,          IP15_11_8)
 183 #define GPSR6_15        F_(SSI_WS6,             IP15_7_4)
 184 #define GPSR6_14        F_(SSI_SCK6,            IP15_3_0)
 185 #define GPSR6_13        FM(SSI_SDATA5)
 186 #define GPSR6_12        FM(SSI_WS5)
 187 #define GPSR6_11        FM(SSI_SCK5)
 188 #define GPSR6_10        F_(SSI_SDATA4,          IP14_31_28)
 189 #define GPSR6_9         F_(SSI_WS4,             IP14_27_24)
 190 #define GPSR6_8         F_(SSI_SCK4,            IP14_23_20)
 191 #define GPSR6_7         F_(SSI_SDATA3,          IP14_19_16)
 192 #define GPSR6_6         F_(SSI_WS349,           IP14_15_12)
 193 #define GPSR6_5         F_(SSI_SCK349,          IP14_11_8)
 194 #define GPSR6_4         F_(SSI_SDATA2_A,        IP14_7_4)
 195 #define GPSR6_3         F_(SSI_SDATA1_A,        IP14_3_0)
 196 #define GPSR6_2         F_(SSI_SDATA0,          IP13_31_28)
 197 #define GPSR6_1         F_(SSI_WS01239,         IP13_27_24)
 198 #define GPSR6_0         F_(SSI_SCK01239,        IP13_23_20)
 199
 200 /* GPSR7 */
 201 #define GPSR7_3         FM(HDMI1_CEC)
 202 #define GPSR7_2         FM(HDMI0_CEC)
 203 #define GPSR7_1         FM(AVS2)
 204 #define GPSR7_0         FM(AVS1)
 205
 206
 207 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 208 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 209 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 210 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_TANS_A)               F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   FM(A25)                 FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    FM(A24)                 FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    FM(A23)                 FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)FM(A22)                 F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        FM(A21)                 FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        FM(A20)                 FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227
 228 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 229 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_TANS_B)               F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP4_19_16       FM(CS1_N_A26)           F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N_TANS)                 FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP7_15_12       FM(FSCLKST)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271
 272 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 273 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       F_(0, 0)                        F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP9_7_4         FM(SD2_DAT0)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP9_11_8        FM(SD2_DAT1)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP9_15_12       FM(SD2_DAT2)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP9_19_16       FM(SD2_DAT3)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP9_23_20       FM(SD2_DS)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP9_27_24       FM(SD3_DAT4)            FM(SD2_CD_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_31_28       FM(SD3_DAT5)            FM(SD2_WP_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP10_3_0        FM(SD3_DAT6)            FM(SD3_CD)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP10_7_4        FM(SD3_DAT7)            FM(SD3_WP)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP10_11_8       FM(SD0_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP10_15_12      FM(SD0_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP10_19_16      FM(SD1_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP10_23_20      FM(SD1_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP10_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP11_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP11_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP11_11_8       FM(RTS0_N_TANS)         FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP11_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP11_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP11_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP11_27_24      FM(RTS1_N_TANS)         FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP12_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP12_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP12_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP12_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP12_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP12_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP12_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315
 316 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 317 #define IP12_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP13_3_0        FM(MSIOF0_SS1)          FM(RX5)         F_(0, 0)                FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP13_7_4        FM(MSIOF0_SS2)          FM(TX5)         FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP13_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP13_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP13_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP13_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP13_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP14_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP14_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP14_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP14_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP14_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP14_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP14_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP14_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP15_3_0        FM(SSI_SCK6)            FM(USB2_PWEN)   F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP15_7_4        FM(SSI_WS6)             FM(USB2_OVC)    F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP15_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP15_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP15_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP15_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP15_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP15_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP16_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP16_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP16_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP16_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP16_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP16_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP16_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP16_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_B)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP17_3_0        FM(USB31_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP17_7_4        FM(USB31_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352
 353 #define PINMUX_GPSR     \
 354 \
 355                                                                                                 GPSR6_31 \
 356                                                                                                 GPSR6_30 \
 357                                                                                                 GPSR6_29 \
 358                                                                                                 GPSR6_28 \
 359                 GPSR1_27                                                                        GPSR6_27 \
 360                 GPSR1_26                                                                        GPSR6_26 \
 361                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 362                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 363                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 364                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 365                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 366                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 367                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 368                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 369                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 370                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 371 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 372 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 373 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 374 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 375 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 376 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 377 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 378 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 379 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 380 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 381 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 382 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 383 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 384 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 385 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 386 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 387
 388 #define PINMUX_IPSR                             \
 389 \
 390 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 391 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 392 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 393 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 394 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 395 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 396 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 397 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 398 \
 399 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 400 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 401 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 402 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 403 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 404 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 405 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 406 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 407 \
 408 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 409 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 410 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 411 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 412 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 413 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 414 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 415 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 416 \
 417 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 418 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 419 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 420 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 421 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 422 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 423 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 424 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 425 \
 426 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0 \
 427 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4 \
 428 FM(IP16_11_8)   IP16_11_8 \
 429 FM(IP16_15_12)  IP16_15_12 \
 430 FM(IP16_19_16)  IP16_19_16 \
 431 FM(IP16_23_20)  IP16_23_20 \
 432 FM(IP16_27_24)  IP16_27_24 \
 433 FM(IP16_31_28)  IP16_31_28
 434
 435 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 436 #define MOD_SEL0_30_29          FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)
 437 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 438 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 439 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 440 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 441 #define MOD_SEL0_21_20          FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)
 442 #define MOD_SEL0_19             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 443 #define MOD_SEL0_18             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 444 #define MOD_SEL0_17             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 445 #define MOD_SEL0_16_15          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 446 #define MOD_SEL0_14             FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)
 447 #define MOD_SEL0_13             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 448 #define MOD_SEL0_12             FM(SEL_FSO_0)           FM(SEL_FSO_1)
 449 #define MOD_SEL0_11             FM(SEL_FM_0)            FM(SEL_FM_1)
 450 #define MOD_SEL0_10             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 451 #define MOD_SEL0_9              FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 452 #define MOD_SEL0_8              FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 453 #define MOD_SEL0_7_6            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 454 #define MOD_SEL0_5_4            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 455 #define MOD_SEL0_3              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 456 #define MOD_SEL0_2_1            FM(SEL_ADG_0)           FM(SEL_ADG_1)           FM(SEL_ADG_2)           FM(SEL_ADG_3)
 457
 458 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 459 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 460 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 461 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 462 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 463 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 464 #define MOD_SEL1_20             FM(SEL_SSI_0)           FM(SEL_SSI_1)
 465 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 466 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 467 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 468 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 469 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 470 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 471 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 472 #define MOD_SEL1_10             FM(SEL_SATA_0)          FM(SEL_SATA_1)
 473 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 474 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 475 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 476 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 477 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 478 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 479 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 480 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 481
 482 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 483 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 484 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 485 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 486 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 487
 488 #define PINMUX_MOD_SELS\
 489 \
 490                         MOD_SEL1_31_30          MOD_SEL2_31 \
 491 MOD_SEL0_30_29                                  MOD_SEL2_30 \
 492                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 493 MOD_SEL0_28_27 \
 494 \
 495 MOD_SEL0_26_25_24       MOD_SEL1_26 \
 496                         MOD_SEL1_25_24 \
 497 \
 498 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 499 MOD_SEL0_22 \
 500 MOD_SEL0_21_20 \
 501                         MOD_SEL1_20 \
 502 MOD_SEL0_19             MOD_SEL1_19 \
 503 MOD_SEL0_18             MOD_SEL1_18_17 \
 504 MOD_SEL0_17 \
 505 MOD_SEL0_16_15          MOD_SEL1_16 \
 506                         MOD_SEL1_15_14 \
 507 MOD_SEL0_14 \
 508 MOD_SEL0_13             MOD_SEL1_13 \
 509 MOD_SEL0_12             MOD_SEL1_12 \
 510 MOD_SEL0_11             MOD_SEL1_11 \
 511 MOD_SEL0_10             MOD_SEL1_10 \
 512 MOD_SEL0_9              MOD_SEL1_9 \
 513 MOD_SEL0_8 \
 514 MOD_SEL0_7_6 \
 515                         MOD_SEL1_6 \
 516 MOD_SEL0_5_4            MOD_SEL1_5 \
 517                         MOD_SEL1_4 \
 518 MOD_SEL0_3              MOD_SEL1_3 \
 519 MOD_SEL0_2_1            MOD_SEL1_2 \
 520                         MOD_SEL1_1 \
 521                         MOD_SEL1_0              MOD_SEL2_0
 522
 523 /*
 524  * These pins are not able to be muxed but have other properties
 525  * that can be set, such as drive-strength or pull-up/pull-down enable.
 526  */
 527 #define PINMUX_STATIC \
 528         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 529         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 530         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 531         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 532         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 533         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 534         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 535         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 536         FM(CLKOUT) FM(PRESETOUT) \
 537         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
 538         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 539
 540 #define PINMUX_PHYS \
 541         FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 542
 543 enum {
 544         PINMUX_RESERVED = 0,
 545
 546         PINMUX_DATA_BEGIN,
 547         GP_ALL(DATA),
 548         PINMUX_DATA_END,
 549
 550 #define F_(x, y)
 551 #define FM(x)   FN_##x,
 552         PINMUX_FUNCTION_BEGIN,
 553         GP_ALL(FN),
 554         PINMUX_GPSR
 555         PINMUX_IPSR
 556         PINMUX_MOD_SELS
 557         PINMUX_FUNCTION_END,
 558 #undef F_
 559 #undef FM
 560
 561 #define F_(x, y)
 562 #define FM(x)   x##_MARK,
 563         PINMUX_MARK_BEGIN,
 564         PINMUX_GPSR
 565         PINMUX_IPSR
 566         PINMUX_MOD_SELS
 567         PINMUX_STATIC
 568         PINMUX_PHYS
 569         PINMUX_MARK_END,
 570 #undef F_
 571 #undef FM
 572 };
 573
 574 static const u16 pinmux_data[] = {
 575         PINMUX_DATA_GP_ALL(),
 576
 577         PINMUX_SINGLE(AVS1),
 578         PINMUX_SINGLE(AVS2),
 579         PINMUX_SINGLE(HDMI0_CEC),
 580         PINMUX_SINGLE(HDMI1_CEC),
 581         PINMUX_SINGLE(MSIOF0_RXD),
 582         PINMUX_SINGLE(MSIOF0_SCK),
 583         PINMUX_SINGLE(MSIOF0_TXD),
 584         PINMUX_SINGLE(SD2_CMD),
 585         PINMUX_SINGLE(SD3_CLK),
 586         PINMUX_SINGLE(SD3_CMD),
 587         PINMUX_SINGLE(SD3_DAT0),
 588         PINMUX_SINGLE(SD3_DAT1),
 589         PINMUX_SINGLE(SD3_DAT2),
 590         PINMUX_SINGLE(SD3_DAT3),
 591         PINMUX_SINGLE(SD3_DS),
 592         PINMUX_SINGLE(SSI_SCK5),
 593         PINMUX_SINGLE(SSI_SDATA5),
 594         PINMUX_SINGLE(SSI_WS5),
 595
 596         /* IPSR0 */
 597         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 598         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 599
 600         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 601         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 602         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 603
 604         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 605         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 606         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 607
 608         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 609         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 610         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 611
 612         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,      I2C_SEL_5_0,    SEL_ETHERAVB_0),
 613         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 614         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 615         PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
 616
 617         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,    I2C_SEL_5_0,    SEL_ETHERAVB_0),
 618         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 619         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A,         I2C_SEL_5_0,    SEL_SCIF4_0),
 620         PINMUX_IPSR_PHYS(IP0_23_20,     SDA5,                   I2C_SEL_5_1),
 621
 622         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 623         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 624         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 625         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 626         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 627         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 628
 629         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 630         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 631         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 632         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 633         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 634         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 635
 636         /* IPSR1 */
 637         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 638         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 639         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 640         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 641         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 642
 643         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 644         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 645         PINMUX_IPSR_GPSR(IP1_7_4,       A25),
 646         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 647         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 648         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 649
 650         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 651         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 652         PINMUX_IPSR_GPSR(IP1_11_8,      A24),
 653         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 654         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 655         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 656
 657         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 658         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 659         PINMUX_IPSR_GPSR(IP1_15_12,     A23),
 660         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 661         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 662         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 663
 664         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 665         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 666         PINMUX_IPSR_GPSR(IP1_19_16,     A22),
 667         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 668         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 669
 670         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,                I2C_SEL_3_0,    SEL_PWM1_0),
 671         PINMUX_IPSR_MSEL(IP1_23_20,     A21,                    I2C_SEL_3_0),
 672         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 673         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,           I2C_SEL_3_0,    SEL_VIN4_1),
 674         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 675         PINMUX_IPSR_PHYS(IP0_23_20,     SCL3,                   I2C_SEL_3_1),
 676
 677         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,                I2C_SEL_3_0,    SEL_PWM2_0),
 678         PINMUX_IPSR_MSEL(IP1_27_24,     A20,                    I2C_SEL_3_0),
 679         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 680         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 681         PINMUX_IPSR_PHYS(IP1_27_24,     SDA3,                   I2C_SEL_3_1),
 682
 683         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 684         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 685         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 686         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 687         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 688         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 689
 690         /* IPSR2 */
 691         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 692         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 693         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 694         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 695         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 696         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 697
 698         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 699         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 700         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 702         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 703         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 704
 705         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 706         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 707         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 708         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 709         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 710         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 711
 712         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 713         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 714         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 715         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 716         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 717         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 718
 719         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 720         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 721         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 722         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 723         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 724         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 725         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 726
 727         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 728         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 729         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 730         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 731         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 732         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 733         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 734
 735         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 736         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 737         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 738         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 739         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 740         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 741         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 742
 743         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 744         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 745         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 746         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 747         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 748         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 749         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 750
 751         /* IPSR3 */
 752         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 753         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 754         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 755         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 756
 757         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 758         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 759         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_TANS_B,          SEL_SCIF4_1),
 760         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 761
 762         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 763         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 764         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 765         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 766         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 767         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 768         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 769         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 770         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 771
 772         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 773         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 774         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 775         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 776         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 777         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 778
 779         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 780         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 781         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 782         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 783         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 784         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 785
 786         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 787         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 788         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 789         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 790         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 791         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 792
 793         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 794         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 795         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 796         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 797         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 798         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 799
 800         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 801         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 802         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 803         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 804
 805         /* IPSR4 */
 806         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 807         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 808         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 809         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 810
 811         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 812         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 813         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 814         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 815
 816         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 817         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 818         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 819         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 820
 821         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 822         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 823
 824         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N_A26),
 825         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 826         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 827
 828         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 829         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 830         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 831         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 832         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 833         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 834         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 835         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 836
 837         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 838         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 839         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 840         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 841         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 842         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 843
 844         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 845         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 846         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 847         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 848         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 849         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 850
 851         /* IPSR5 */
 852         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 853         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 854         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 855         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 856         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 857         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 858         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 859
 860         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 861         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 862         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N_TANS),
 863         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 864         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 865         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 866         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 867         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 868
 869         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 870         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 871         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 872         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 873
 874         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 875         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 876         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 877         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 878         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 879
 880         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 881         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 882         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 883         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 884         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 885
 886         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 887         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 888         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 889         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 890
 891         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 892         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 893         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 894         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 895
 896         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 897         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 898         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 899         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 900
 901         /* IPSR6 */
 902         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 903         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 904         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 905         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 906
 907         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 908         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 909         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 910         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 911
 912         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 913         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 914         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 915         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 916
 917         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 918         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 919         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 920         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 921         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 922         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 923
 924         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 925         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 926         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 927         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 928         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 929
 930         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 931         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 932         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 933         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 934         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 935         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 936         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 937
 938         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 939         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 940         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 941         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 942         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 943         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_TANS_C,          SEL_SCIF4_2),
 944         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 945
 946         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 947         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 948         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 949         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 950         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 951         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 952
 953         /* IPSR7 */
 954         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 955         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 956         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 957         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 958         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 959         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 960
 961         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 962         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 963         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 964         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 965         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 967         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 968
 969         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 970         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 971         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 972         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 973         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 974         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 975         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 976
 977         PINMUX_IPSR_GPSR(IP7_15_12,     FSCLKST),
 978
 979         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 980         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 981         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 982
 983         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 984         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 985         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 986
 987         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 988         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 989         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 990         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 991
 992         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 993         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
 995         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
 996
 997         /* IPSR8 */
 998         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
 999         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1000         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1001         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1002
1003         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1004         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1005         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1006         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1007
1008         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1009         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1010         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1011
1012         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1013         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1014         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1015         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1016
1017         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1018         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1019         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1020         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1021         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1022
1023         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1024         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1025         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1026         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1027         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1028
1029         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1030         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1031         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1032         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1033         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1034
1035         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1036         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1037         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1038         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1039         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1040
1041         /* IPSR9 */
1042         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1043
1044         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_DAT0),
1045
1046         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT1),
1047
1048         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT2),
1049
1050         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT3),
1051
1052         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DS),
1053         PINMUX_IPSR_MSEL(IP9_23_20,     SATA_DEVSLP_B,          SEL_SATA_1),
1054
1055         PINMUX_IPSR_GPSR(IP9_27_24,     SD3_DAT4),
1056         PINMUX_IPSR_MSEL(IP9_27_24,     SD2_CD_A,               SEL_SDHI2_0),
1057
1058         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_DAT5),
1059         PINMUX_IPSR_MSEL(IP9_31_28,     SD2_WP_A,               SEL_SDHI2_0),
1060
1061         /* IPSR10 */
1062         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_DAT6),
1063         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CD),
1064
1065         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT7),
1066         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_WP),
1067
1068         PINMUX_IPSR_GPSR(IP10_11_8,     SD0_CD),
1069         PINMUX_IPSR_MSEL(IP10_11_8,     SCL2_B,                 SEL_I2C2_1),
1070         PINMUX_IPSR_MSEL(IP10_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1071
1072         PINMUX_IPSR_GPSR(IP10_15_12,    SD0_WP),
1073         PINMUX_IPSR_MSEL(IP10_15_12,    SDA2_B,                 SEL_I2C2_1),
1074
1075         PINMUX_IPSR_MSEL(IP10_19_16,    SD1_CD,                 I2C_SEL_0_0),
1076         PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B,           I2C_SEL_0_0,    SEL_SIMCARD_1),
1077         PINMUX_IPSR_PHYS(IP10_19_16,    SCL0,                   I2C_SEL_0_1),
1078
1079         PINMUX_IPSR_MSEL(IP10_23_20,    SD1_WP,                 I2C_SEL_0_0),
1080         PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B,             I2C_SEL_0_0,    SEL_SIMCARD_1),
1081         PINMUX_IPSR_PHYS(IP10_23_20,    SDA0,                   I2C_SEL_0_1),
1082
1083         PINMUX_IPSR_GPSR(IP10_27_24,    SCK0),
1084         PINMUX_IPSR_MSEL(IP10_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1085         PINMUX_IPSR_MSEL(IP10_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1086         PINMUX_IPSR_MSEL(IP10_27_24,    AUDIO_CLKC_B,           SEL_ADG_1),
1087         PINMUX_IPSR_MSEL(IP10_27_24,    SDA2_A,                 SEL_I2C2_0),
1088         PINMUX_IPSR_MSEL(IP10_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1089         PINMUX_IPSR_MSEL(IP10_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1090         PINMUX_IPSR_MSEL(IP10_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1091         PINMUX_IPSR_GPSR(IP10_27_24,    ADICHS2),
1092
1093         PINMUX_IPSR_GPSR(IP10_31_28,    RX0),
1094         PINMUX_IPSR_MSEL(IP10_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1095         PINMUX_IPSR_MSEL(IP10_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1096         PINMUX_IPSR_MSEL(IP10_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1097         PINMUX_IPSR_MSEL(IP10_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1098
1099         /* IPSR11 */
1100         PINMUX_IPSR_GPSR(IP11_3_0,      TX0),
1101         PINMUX_IPSR_MSEL(IP11_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1102         PINMUX_IPSR_MSEL(IP11_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1103         PINMUX_IPSR_MSEL(IP11_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1104         PINMUX_IPSR_MSEL(IP11_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1105
1106         PINMUX_IPSR_GPSR(IP11_7_4,      CTS0_N),
1107         PINMUX_IPSR_MSEL(IP11_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1108         PINMUX_IPSR_MSEL(IP11_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1109         PINMUX_IPSR_MSEL(IP11_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1110         PINMUX_IPSR_MSEL(IP11_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1111         PINMUX_IPSR_MSEL(IP11_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1112         PINMUX_IPSR_MSEL(IP11_7_4,      AUDIO_CLKOUT_C,         SEL_ADG_2),
1113         PINMUX_IPSR_GPSR(IP11_7_4,      ADICS_SAMP),
1114
1115         PINMUX_IPSR_GPSR(IP11_11_8,     RTS0_N_TANS),
1116         PINMUX_IPSR_MSEL(IP11_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1117         PINMUX_IPSR_MSEL(IP11_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1118         PINMUX_IPSR_MSEL(IP11_11_8,     AUDIO_CLKA_B,           SEL_ADG_1),
1119         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_A,                 SEL_I2C2_0),
1120         PINMUX_IPSR_MSEL(IP11_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1121         PINMUX_IPSR_MSEL(IP11_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1122         PINMUX_IPSR_GPSR(IP11_11_8,     ADICHS1),
1123
1124         PINMUX_IPSR_MSEL(IP11_15_12,    RX1_A,                  SEL_SCIF1_0),
1125         PINMUX_IPSR_MSEL(IP11_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1126         PINMUX_IPSR_MSEL(IP11_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1127         PINMUX_IPSR_MSEL(IP11_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1128         PINMUX_IPSR_MSEL(IP11_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1129
1130         PINMUX_IPSR_MSEL(IP11_19_16,    TX1_A,                  SEL_SCIF1_0),
1131         PINMUX_IPSR_MSEL(IP11_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1132         PINMUX_IPSR_MSEL(IP11_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1133         PINMUX_IPSR_MSEL(IP11_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1134         PINMUX_IPSR_MSEL(IP11_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1135
1136         PINMUX_IPSR_GPSR(IP11_23_20,    CTS1_N),
1137         PINMUX_IPSR_MSEL(IP11_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1138         PINMUX_IPSR_MSEL(IP11_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1139         PINMUX_IPSR_MSEL(IP11_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1140         PINMUX_IPSR_MSEL(IP11_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1141         PINMUX_IPSR_MSEL(IP11_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1142         PINMUX_IPSR_GPSR(IP11_23_20,    ADIDATA),
1143
1144         PINMUX_IPSR_GPSR(IP11_27_24,    RTS1_N_TANS),
1145         PINMUX_IPSR_MSEL(IP11_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1146         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1147         PINMUX_IPSR_MSEL(IP11_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1148         PINMUX_IPSR_MSEL(IP11_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1149         PINMUX_IPSR_MSEL(IP11_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1150         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS0),
1151
1152         PINMUX_IPSR_GPSR(IP11_31_28,    SCK2),
1153         PINMUX_IPSR_MSEL(IP11_31_28,    SCIF_CLK_B,             SEL_SCIF1_1),
1154         PINMUX_IPSR_MSEL(IP11_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1155         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1156         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1157         PINMUX_IPSR_MSEL(IP11_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1158         PINMUX_IPSR_GPSR(IP11_31_28,    ADICLK),
1159
1160         /* IPSR12 */
1161         PINMUX_IPSR_MSEL(IP12_3_0,      TX2_A,                  SEL_SCIF2_0),
1162         PINMUX_IPSR_MSEL(IP12_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1163         PINMUX_IPSR_MSEL(IP12_3_0,      SCL1_A,                 SEL_I2C1_0),
1164         PINMUX_IPSR_MSEL(IP12_3_0,      FMCLK_A,                SEL_FM_0),
1165         PINMUX_IPSR_MSEL(IP12_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1166         PINMUX_IPSR_MSEL(IP12_3_0,      FSO_CFE_0_B,            SEL_FSO_1),
1167
1168         PINMUX_IPSR_MSEL(IP12_7_4,      RX2_A,                  SEL_SCIF2_0),
1169         PINMUX_IPSR_MSEL(IP12_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1170         PINMUX_IPSR_MSEL(IP12_7_4,      SDA1_A,                 SEL_I2C1_0),
1171         PINMUX_IPSR_MSEL(IP12_7_4,      FMIN_A,                 SEL_FM_0),
1172         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1173         PINMUX_IPSR_MSEL(IP12_7_4,      FSO_CFE_1_B,            SEL_FSO_1),
1174
1175         PINMUX_IPSR_GPSR(IP12_11_8,     HSCK0),
1176         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1177         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKB_A,           SEL_ADG_0),
1178         PINMUX_IPSR_MSEL(IP12_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
1179         PINMUX_IPSR_MSEL(IP12_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1180         PINMUX_IPSR_MSEL(IP12_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1181         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1182
1183         PINMUX_IPSR_GPSR(IP12_15_12,    HRX0),
1184         PINMUX_IPSR_MSEL(IP12_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1185         PINMUX_IPSR_MSEL(IP12_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
1186         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1187         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1188         PINMUX_IPSR_MSEL(IP12_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1189
1190         PINMUX_IPSR_GPSR(IP12_19_16,    HTX0),
1191         PINMUX_IPSR_MSEL(IP12_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1192         PINMUX_IPSR_MSEL(IP12_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
1193         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1194         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1195         PINMUX_IPSR_MSEL(IP12_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1196
1197         PINMUX_IPSR_GPSR(IP12_23_20,    HCTS0_N),
1198         PINMUX_IPSR_MSEL(IP12_23_20,    RX2_B,                  SEL_SCIF2_1),
1199         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1200         PINMUX_IPSR_MSEL(IP12_23_20,    SSI_SCK9_A,             SEL_SSI_0),
1201         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1202         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1203         PINMUX_IPSR_MSEL(IP12_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1204         PINMUX_IPSR_MSEL(IP12_23_20,    AUDIO_CLKOUT1_A,        SEL_ADG_0),
1205
1206         PINMUX_IPSR_GPSR(IP12_27_24,    HRTS0_N),
1207         PINMUX_IPSR_MSEL(IP12_27_24,    TX2_B,                  SEL_SCIF2_1),
1208         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1209         PINMUX_IPSR_MSEL(IP12_27_24,    SSI_WS9_A,              SEL_SSI_0),
1210         PINMUX_IPSR_MSEL(IP12_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1211         PINMUX_IPSR_MSEL(IP12_27_24,    BPFCLK_A,               SEL_FM_0),
1212         PINMUX_IPSR_MSEL(IP12_27_24,    AUDIO_CLKOUT2_A,        SEL_ADG_0),
1213
1214         PINMUX_IPSR_GPSR(IP12_31_28,    MSIOF0_SYNC),
1215         PINMUX_IPSR_MSEL(IP12_31_28,    AUDIO_CLKOUT_A,         SEL_ADG_0),
1216
1217         /* IPSR13 */
1218         PINMUX_IPSR_GPSR(IP13_3_0,      MSIOF0_SS1),
1219         PINMUX_IPSR_GPSR(IP13_3_0,      RX5),
1220         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKA_C,           SEL_ADG_2),
1221         PINMUX_IPSR_MSEL(IP13_3_0,      SSI_SCK2_A,             SEL_SSI_0),
1222         PINMUX_IPSR_MSEL(IP13_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1223         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKOUT3_A,        SEL_ADG_0),
1224         PINMUX_IPSR_MSEL(IP13_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1225
1226         PINMUX_IPSR_GPSR(IP13_7_4,      MSIOF0_SS2),
1227         PINMUX_IPSR_GPSR(IP13_7_4,      TX5),
1228         PINMUX_IPSR_MSEL(IP13_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1229         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKC_A,           SEL_ADG_0),
1230         PINMUX_IPSR_MSEL(IP13_7_4,      SSI_WS2_A,              SEL_SSI_0),
1231         PINMUX_IPSR_MSEL(IP13_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1232         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKOUT_D,         SEL_ADG_3),
1233         PINMUX_IPSR_MSEL(IP13_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1234
1235         PINMUX_IPSR_GPSR(IP13_11_8,     MLB_CLK),
1236         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1237         PINMUX_IPSR_MSEL(IP13_11_8,     SCL1_B,                 SEL_I2C1_1),
1238
1239         PINMUX_IPSR_GPSR(IP13_15_12,    MLB_SIG),
1240         PINMUX_IPSR_MSEL(IP13_15_12,    RX1_B,                  SEL_SCIF1_1),
1241         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1242         PINMUX_IPSR_MSEL(IP13_15_12,    SDA1_B,                 SEL_I2C1_1),
1243
1244         PINMUX_IPSR_GPSR(IP13_19_16,    MLB_DAT),
1245         PINMUX_IPSR_MSEL(IP13_19_16,    TX1_B,                  SEL_SCIF1_1),
1246         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1247
1248         PINMUX_IPSR_GPSR(IP13_23_20,    SSI_SCK01239),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1250
1251         PINMUX_IPSR_GPSR(IP13_27_24,    SSI_WS01239),
1252         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1253
1254         PINMUX_IPSR_GPSR(IP13_31_28,    SSI_SDATA0),
1255         PINMUX_IPSR_MSEL(IP13_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1256
1257         /* IPSR14 */
1258         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
1259
1260         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
1261         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SCK1_B,             SEL_SSI_1),
1262
1263         PINMUX_IPSR_GPSR(IP14_11_8,     SSI_SCK349),
1264         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1265         PINMUX_IPSR_MSEL(IP14_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1266
1267         PINMUX_IPSR_GPSR(IP14_15_12,    SSI_WS349),
1268         PINMUX_IPSR_MSEL(IP14_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1269         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1270         PINMUX_IPSR_MSEL(IP14_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1271
1272         PINMUX_IPSR_GPSR(IP14_19_16,    SSI_SDATA3),
1273         PINMUX_IPSR_MSEL(IP14_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1274         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1275         PINMUX_IPSR_MSEL(IP14_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1276         PINMUX_IPSR_MSEL(IP14_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1277         PINMUX_IPSR_MSEL(IP14_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1278         PINMUX_IPSR_MSEL(IP14_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1279
1280         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK4),
1281         PINMUX_IPSR_MSEL(IP14_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1282         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1283         PINMUX_IPSR_MSEL(IP14_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1284         PINMUX_IPSR_MSEL(IP14_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1285         PINMUX_IPSR_MSEL(IP14_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1286         PINMUX_IPSR_MSEL(IP14_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1287
1288         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS4),
1289         PINMUX_IPSR_MSEL(IP14_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1290         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1291         PINMUX_IPSR_MSEL(IP14_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1292         PINMUX_IPSR_MSEL(IP14_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1293         PINMUX_IPSR_MSEL(IP14_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1294         PINMUX_IPSR_MSEL(IP14_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1295
1296         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA4),
1297         PINMUX_IPSR_MSEL(IP14_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1298         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1299         PINMUX_IPSR_MSEL(IP14_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1300         PINMUX_IPSR_MSEL(IP14_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1301         PINMUX_IPSR_MSEL(IP14_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1302         PINMUX_IPSR_MSEL(IP14_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1303
1304         /* IPSR15 */
1305         PINMUX_IPSR_GPSR(IP15_3_0,      SSI_SCK6),
1306         PINMUX_IPSR_GPSR(IP15_3_0,      USB2_PWEN),
1307         PINMUX_IPSR_MSEL(IP15_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1308
1309         PINMUX_IPSR_GPSR(IP15_7_4,      SSI_WS6),
1310         PINMUX_IPSR_GPSR(IP15_7_4,      USB2_OVC),
1311         PINMUX_IPSR_MSEL(IP15_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1312
1313         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SDATA6),
1314         PINMUX_IPSR_MSEL(IP15_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1315         PINMUX_IPSR_MSEL(IP15_11_8,     SATA_DEVSLP_A,          SEL_SATA_0),
1316
1317         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_SCK78),
1318         PINMUX_IPSR_MSEL(IP15_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1319         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1320         PINMUX_IPSR_MSEL(IP15_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1322         PINMUX_IPSR_MSEL(IP15_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1323         PINMUX_IPSR_MSEL(IP15_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1324
1325         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_WS78),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1331         PINMUX_IPSR_MSEL(IP15_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1332
1333         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SDATA7),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1339         PINMUX_IPSR_MSEL(IP15_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1340         PINMUX_IPSR_MSEL(IP15_23_20,    TCLK2_A,                SEL_TIMER_TMU_0),
1341
1342         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_SDATA8),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1347         PINMUX_IPSR_MSEL(IP15_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1348         PINMUX_IPSR_MSEL(IP15_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1349
1350         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_WS1_B,              SEL_SSI_1),
1355         PINMUX_IPSR_GPSR(IP15_31_28,    SCK1),
1356         PINMUX_IPSR_MSEL(IP15_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1357         PINMUX_IPSR_GPSR(IP15_31_28,    SCK5),
1358
1359         /* IPSR16 */
1360         PINMUX_IPSR_MSEL(IP16_3_0,      AUDIO_CLKA_A,           SEL_ADG_0),
1361         PINMUX_IPSR_GPSR(IP16_3_0,      CC5_OSCOUT),
1362
1363         PINMUX_IPSR_MSEL(IP16_7_4,      AUDIO_CLKB_B,           SEL_ADG_1),
1364         PINMUX_IPSR_MSEL(IP16_7_4,      SCIF_CLK_A,             SEL_SCIF1_0),
1365         PINMUX_IPSR_MSEL(IP16_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1366         PINMUX_IPSR_MSEL(IP16_7_4,      REMOCON_A,              SEL_REMOCON_0),
1367         PINMUX_IPSR_MSEL(IP16_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1368
1369         PINMUX_IPSR_GPSR(IP16_11_8,     USB0_PWEN),
1370         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1371         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1372         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1373         PINMUX_IPSR_MSEL(IP16_11_8,     BPFCLK_B,               SEL_FM_1),
1374         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1375
1376         PINMUX_IPSR_GPSR(IP16_15_12,    USB0_OVC),
1377         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_D_C,               SEL_SIMCARD_2),
1378         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SDAT1_D,             SEL_TSIF1_3),
1379         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISD_1_D,            SEL_SSP1_1_3),
1380         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_SYNC_B,            SEL_DRIF3_1),
1381
1382         PINMUX_IPSR_GPSR(IP16_19_16,    USB1_PWEN),
1383         PINMUX_IPSR_MSEL(IP16_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    SSI_SCK1_A,             SEL_SSI_0),
1385         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1386         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1387         PINMUX_IPSR_MSEL(IP16_19_16,    FMCLK_B,                SEL_FM_1),
1388         PINMUX_IPSR_MSEL(IP16_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1389         PINMUX_IPSR_MSEL(IP16_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1390
1391         PINMUX_IPSR_GPSR(IP16_23_20,    USB1_OVC),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    SSI_WS1_A,              SEL_SSI_0),
1394         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1395         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1396         PINMUX_IPSR_MSEL(IP16_23_20,    FMIN_B,                 SEL_FM_1),
1397         PINMUX_IPSR_MSEL(IP16_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1398         PINMUX_IPSR_MSEL(IP16_23_20,    REMOCON_B,              SEL_REMOCON_1),
1399
1400         PINMUX_IPSR_GPSR(IP16_27_24,    USB30_PWEN),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    AUDIO_CLKOUT_B,         SEL_ADG_1),
1402         PINMUX_IPSR_MSEL(IP16_27_24,    SSI_SCK2_B,             SEL_SSI_1),
1403         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1404         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1405         PINMUX_IPSR_MSEL(IP16_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1406         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1407         PINMUX_IPSR_MSEL(IP16_27_24,    TCLK2_B,                SEL_TIMER_TMU_1),
1408         PINMUX_IPSR_GPSR(IP16_27_24,    TPU0TO0),
1409
1410         PINMUX_IPSR_GPSR(IP16_31_28,    USB30_OVC),
1411         PINMUX_IPSR_MSEL(IP16_31_28,    AUDIO_CLKOUT1_B,        SEL_ADG_1),
1412         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS2_B,              SEL_SSI_1),
1413         PINMUX_IPSR_MSEL(IP16_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1414         PINMUX_IPSR_MSEL(IP16_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1415         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1416         PINMUX_IPSR_MSEL(IP16_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1417         PINMUX_IPSR_MSEL(IP16_31_28,    FSO_TOE_B,              SEL_FSO_1),
1418         PINMUX_IPSR_GPSR(IP16_31_28,    TPU0TO1),
1419
1420         /* IPSR17 */
1421         PINMUX_IPSR_GPSR(IP17_3_0,      USB31_PWEN),
1422         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKOUT2_B,        SEL_ADG_1),
1423         PINMUX_IPSR_MSEL(IP17_3_0,      SSI_SCK9_B,             SEL_SSI_1),
1424         PINMUX_IPSR_MSEL(IP17_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1425         PINMUX_IPSR_MSEL(IP17_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1426         PINMUX_IPSR_MSEL(IP17_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1427         PINMUX_IPSR_GPSR(IP17_3_0,      TPU0TO2),
1428
1429         PINMUX_IPSR_GPSR(IP17_7_4,      USB31_OVC),
1430         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKOUT3_B,        SEL_ADG_1),
1431         PINMUX_IPSR_MSEL(IP17_7_4,      SSI_WS9_B,              SEL_SSI_1),
1432         PINMUX_IPSR_MSEL(IP17_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1433         PINMUX_IPSR_MSEL(IP17_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1434         PINMUX_IPSR_MSEL(IP17_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1435         PINMUX_IPSR_GPSR(IP17_7_4,      TPU0TO3),
1436
1437 /*
1438  * Static pins can not be muxed between different functions but
1439  * still need mark entries in the pinmux list. Add each static
1440  * pin to the list without an associated function. The sh-pfc
1441  * core will do the right thing and skip trying to mux the pin
1442  * while still applying configuration to it.
1443  */
1444 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1445         PINMUX_STATIC
1446 #undef FM
1447 };
1448
1449 /*
1450  * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1451  * Physical layout rows: A - AW, cols: 1 - 39.
1452  */
1453 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1454 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1455 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1456 #define PIN_NONE U16_MAX
1457
1458 static const struct sh_pfc_pin pinmux_pins[] = {
1459         PINMUX_GPIO_GP_ALL(),
1460
1461         /*
1462          * Pins not associated with a GPIO port.
1463          *
1464          * The pin positions are different between different r8a7795
1465          * packages, all that is needed for the pfc driver is a unique
1466          * number for each pin. To this end use the pin layout from
1467          * R-Car H3SiP to calculate a unique number for each pin.
1468          */
1469         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1470         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1471         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1472         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1473         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1474         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1475         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1476         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1477         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1478         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1479         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1480         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1481         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1482         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1483         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1484         SH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, CFG_FLAGS),
1485         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1486         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1487         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1488         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1489         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1490         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1491         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1492         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1493         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1494         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1495         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1496         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1497         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1498         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1499         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1500         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1501         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1502         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1503         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1504         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1505         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1506         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1507         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1508         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1509         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1510         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1511         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1512         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1513 };
1514
1515 /* - AUDIO CLOCK ------------------------------------------------------------ */
1516 static const unsigned int audio_clk_a_a_pins[] = {
1517         /* CLK A */
1518         RCAR_GP_PIN(6, 22),
1519 };
1520 static const unsigned int audio_clk_a_a_mux[] = {
1521         AUDIO_CLKA_A_MARK,
1522 };
1523 static const unsigned int audio_clk_a_b_pins[] = {
1524         /* CLK A */
1525         RCAR_GP_PIN(5, 4),
1526 };
1527 static const unsigned int audio_clk_a_b_mux[] = {
1528         AUDIO_CLKA_B_MARK,
1529 };
1530 static const unsigned int audio_clk_a_c_pins[] = {
1531         /* CLK A */
1532         RCAR_GP_PIN(5, 19),
1533 };
1534 static const unsigned int audio_clk_a_c_mux[] = {
1535         AUDIO_CLKA_C_MARK,
1536 };
1537 static const unsigned int audio_clk_b_a_pins[] = {
1538         /* CLK B */
1539         RCAR_GP_PIN(5, 12),
1540 };
1541 static const unsigned int audio_clk_b_a_mux[] = {
1542         AUDIO_CLKB_A_MARK,
1543 };
1544 static const unsigned int audio_clk_b_b_pins[] = {
1545         /* CLK B */
1546         RCAR_GP_PIN(6, 23),
1547 };
1548 static const unsigned int audio_clk_b_b_mux[] = {
1549         AUDIO_CLKB_B_MARK,
1550 };
1551 static const unsigned int audio_clk_c_a_pins[] = {
1552         /* CLK C */
1553         RCAR_GP_PIN(5, 21),
1554 };
1555 static const unsigned int audio_clk_c_a_mux[] = {
1556         AUDIO_CLKC_A_MARK,
1557 };
1558 static const unsigned int audio_clk_c_b_pins[] = {
1559         /* CLK C */
1560         RCAR_GP_PIN(5, 0),
1561 };
1562 static const unsigned int audio_clk_c_b_mux[] = {
1563         AUDIO_CLKC_B_MARK,
1564 };
1565 static const unsigned int audio_clkout_a_pins[] = {
1566         /* CLKOUT */
1567         RCAR_GP_PIN(5, 18),
1568 };
1569 static const unsigned int audio_clkout_a_mux[] = {
1570         AUDIO_CLKOUT_A_MARK,
1571 };
1572 static const unsigned int audio_clkout_b_pins[] = {
1573         /* CLKOUT */
1574         RCAR_GP_PIN(6, 28),
1575 };
1576 static const unsigned int audio_clkout_b_mux[] = {
1577         AUDIO_CLKOUT_B_MARK,
1578 };
1579 static const unsigned int audio_clkout_c_pins[] = {
1580         /* CLKOUT */
1581         RCAR_GP_PIN(5, 3),
1582 };
1583 static const unsigned int audio_clkout_c_mux[] = {
1584         AUDIO_CLKOUT_C_MARK,
1585 };
1586 static const unsigned int audio_clkout_d_pins[] = {
1587         /* CLKOUT */
1588         RCAR_GP_PIN(5, 21),
1589 };
1590 static const unsigned int audio_clkout_d_mux[] = {
1591         AUDIO_CLKOUT_D_MARK,
1592 };
1593 static const unsigned int audio_clkout1_a_pins[] = {
1594         /* CLKOUT1 */
1595         RCAR_GP_PIN(5, 15),
1596 };
1597 static const unsigned int audio_clkout1_a_mux[] = {
1598         AUDIO_CLKOUT1_A_MARK,
1599 };
1600 static const unsigned int audio_clkout1_b_pins[] = {
1601         /* CLKOUT1 */
1602         RCAR_GP_PIN(6, 29),
1603 };
1604 static const unsigned int audio_clkout1_b_mux[] = {
1605         AUDIO_CLKOUT1_B_MARK,
1606 };
1607 static const unsigned int audio_clkout2_a_pins[] = {
1608         /* CLKOUT2 */
1609         RCAR_GP_PIN(5, 16),
1610 };
1611 static const unsigned int audio_clkout2_a_mux[] = {
1612         AUDIO_CLKOUT2_A_MARK,
1613 };
1614 static const unsigned int audio_clkout2_b_pins[] = {
1615         /* CLKOUT2 */
1616         RCAR_GP_PIN(6, 30),
1617 };
1618 static const unsigned int audio_clkout2_b_mux[] = {
1619         AUDIO_CLKOUT2_B_MARK,
1620 };
1621
1622 static const unsigned int audio_clkout3_a_pins[] = {
1623         /* CLKOUT3 */
1624         RCAR_GP_PIN(5, 19),
1625 };
1626 static const unsigned int audio_clkout3_a_mux[] = {
1627         AUDIO_CLKOUT3_A_MARK,
1628 };
1629 static const unsigned int audio_clkout3_b_pins[] = {
1630         /* CLKOUT3 */
1631         RCAR_GP_PIN(6, 31),
1632 };
1633 static const unsigned int audio_clkout3_b_mux[] = {
1634         AUDIO_CLKOUT3_B_MARK,
1635 };
1636
1637 /* - EtherAVB --------------------------------------------------------------- */
1638 static const unsigned int avb_link_pins[] = {
1639         /* AVB_LINK */
1640         RCAR_GP_PIN(2, 12),
1641 };
1642 static const unsigned int avb_link_mux[] = {
1643         AVB_LINK_MARK,
1644 };
1645 static const unsigned int avb_magic_pins[] = {
1646         /* AVB_MAGIC_ */
1647         RCAR_GP_PIN(2, 10),
1648 };
1649 static const unsigned int avb_magic_mux[] = {
1650         AVB_MAGIC_MARK,
1651 };
1652 static const unsigned int avb_phy_int_pins[] = {
1653         /* AVB_PHY_INT */
1654         RCAR_GP_PIN(2, 11),
1655 };
1656 static const unsigned int avb_phy_int_mux[] = {
1657         AVB_PHY_INT_MARK,
1658 };
1659 static const unsigned int avb_mdio_pins[] = {
1660         /* AVB_MDC, AVB_MDIO */
1661         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1662 };
1663 static const unsigned int avb_mdio_mux[] = {
1664         AVB_MDC_MARK, AVB_MDIO_MARK,
1665 };
1666 static const unsigned int avb_mii_pins[] = {
1667         /*
1668          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1669          * AVB_TD1, AVB_TD2, AVB_TD3,
1670          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1671          * AVB_RD1, AVB_RD2, AVB_RD3,
1672          * AVB_TXCREFCLK
1673          */
1674         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1675         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1676         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1677         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1678         PIN_NUMBER('A', 12),
1679
1680 };
1681 static const unsigned int avb_mii_mux[] = {
1682         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1683         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1684         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1685         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1686         AVB_TXCREFCLK_MARK,
1687 };
1688 static const unsigned int avb_avtp_pps_pins[] = {
1689         /* AVB_AVTP_PPS */
1690         RCAR_GP_PIN(2, 6),
1691 };
1692 static const unsigned int avb_avtp_pps_mux[] = {
1693         AVB_AVTP_PPS_MARK,
1694 };
1695 static const unsigned int avb_avtp_match_a_pins[] = {
1696         /* AVB_AVTP_MATCH_A */
1697         RCAR_GP_PIN(2, 13),
1698 };
1699 static const unsigned int avb_avtp_match_a_mux[] = {
1700         AVB_AVTP_MATCH_A_MARK,
1701 };
1702 static const unsigned int avb_avtp_capture_a_pins[] = {
1703         /* AVB_AVTP_CAPTURE_A */
1704         RCAR_GP_PIN(2, 14),
1705 };
1706 static const unsigned int avb_avtp_capture_a_mux[] = {
1707         AVB_AVTP_CAPTURE_A_MARK,
1708 };
1709 static const unsigned int avb_avtp_match_b_pins[] = {
1710         /*  AVB_AVTP_MATCH_B */
1711         RCAR_GP_PIN(1, 8),
1712 };
1713 static const unsigned int avb_avtp_match_b_mux[] = {
1714         AVB_AVTP_MATCH_B_MARK,
1715 };
1716 static const unsigned int avb_avtp_capture_b_pins[] = {
1717         /* AVB_AVTP_CAPTURE_B */
1718         RCAR_GP_PIN(1, 11),
1719 };
1720 static const unsigned int avb_avtp_capture_b_mux[] = {
1721         AVB_AVTP_CAPTURE_B_MARK,
1722 };
1723
1724 /* - CAN ------------------------------------------------------------------ */
1725 static const unsigned int can0_data_a_pins[] = {
1726         /* TX, RX */
1727         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1728 };
1729 static const unsigned int can0_data_a_mux[] = {
1730         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1731 };
1732 static const unsigned int can0_data_b_pins[] = {
1733         /* TX, RX */
1734         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1735 };
1736 static const unsigned int can0_data_b_mux[] = {
1737         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1738 };
1739 static const unsigned int can1_data_pins[] = {
1740         /* TX, RX */
1741         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1742 };
1743 static const unsigned int can1_data_mux[] = {
1744         CAN1_TX_MARK,           CAN1_RX_MARK,
1745 };
1746
1747 /* - CAN Clock -------------------------------------------------------------- */
1748 static const unsigned int can_clk_pins[] = {
1749         /* CLK */
1750         RCAR_GP_PIN(1, 25),
1751 };
1752 static const unsigned int can_clk_mux[] = {
1753         CAN_CLK_MARK,
1754 };
1755
1756 /* - CAN FD --------------------------------------------------------------- */
1757 static const unsigned int canfd0_data_a_pins[] = {
1758         /* TX, RX */
1759         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1760 };
1761 static const unsigned int canfd0_data_a_mux[] = {
1762         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1763 };
1764 static const unsigned int canfd0_data_b_pins[] = {
1765         /* TX, RX */
1766         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1767 };
1768 static const unsigned int canfd0_data_b_mux[] = {
1769         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1770 };
1771 static const unsigned int canfd1_data_pins[] = {
1772         /* TX, RX */
1773         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1774 };
1775 static const unsigned int canfd1_data_mux[] = {
1776         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1777 };
1778
1779 /* - DRIF0 --------------------------------------------------------------- */
1780 static const unsigned int drif0_ctrl_a_pins[] = {
1781         /* CLK, SYNC */
1782         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1783 };
1784 static const unsigned int drif0_ctrl_a_mux[] = {
1785         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1786 };
1787 static const unsigned int drif0_data0_a_pins[] = {
1788         /* D0 */
1789         RCAR_GP_PIN(6, 10),
1790 };
1791 static const unsigned int drif0_data0_a_mux[] = {
1792         RIF0_D0_A_MARK,
1793 };
1794 static const unsigned int drif0_data1_a_pins[] = {
1795         /* D1 */
1796         RCAR_GP_PIN(6, 7),
1797 };
1798 static const unsigned int drif0_data1_a_mux[] = {
1799         RIF0_D1_A_MARK,
1800 };
1801 static const unsigned int drif0_ctrl_b_pins[] = {
1802         /* CLK, SYNC */
1803         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1804 };
1805 static const unsigned int drif0_ctrl_b_mux[] = {
1806         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1807 };
1808 static const unsigned int drif0_data0_b_pins[] = {
1809         /* D0 */
1810         RCAR_GP_PIN(5, 1),
1811 };
1812 static const unsigned int drif0_data0_b_mux[] = {
1813         RIF0_D0_B_MARK,
1814 };
1815 static const unsigned int drif0_data1_b_pins[] = {
1816         /* D1 */
1817         RCAR_GP_PIN(5, 2),
1818 };
1819 static const unsigned int drif0_data1_b_mux[] = {
1820         RIF0_D1_B_MARK,
1821 };
1822 static const unsigned int drif0_ctrl_c_pins[] = {
1823         /* CLK, SYNC */
1824         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1825 };
1826 static const unsigned int drif0_ctrl_c_mux[] = {
1827         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1828 };
1829 static const unsigned int drif0_data0_c_pins[] = {
1830         /* D0 */
1831         RCAR_GP_PIN(5, 13),
1832 };
1833 static const unsigned int drif0_data0_c_mux[] = {
1834         RIF0_D0_C_MARK,
1835 };
1836 static const unsigned int drif0_data1_c_pins[] = {
1837         /* D1 */
1838         RCAR_GP_PIN(5, 14),
1839 };
1840 static const unsigned int drif0_data1_c_mux[] = {
1841         RIF0_D1_C_MARK,
1842 };
1843 /* - DRIF1 --------------------------------------------------------------- */
1844 static const unsigned int drif1_ctrl_a_pins[] = {
1845         /* CLK, SYNC */
1846         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1847 };
1848 static const unsigned int drif1_ctrl_a_mux[] = {
1849         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1850 };
1851 static const unsigned int drif1_data0_a_pins[] = {
1852         /* D0 */
1853         RCAR_GP_PIN(6, 19),
1854 };
1855 static const unsigned int drif1_data0_a_mux[] = {
1856         RIF1_D0_A_MARK,
1857 };
1858 static const unsigned int drif1_data1_a_pins[] = {
1859         /* D1 */
1860         RCAR_GP_PIN(6, 20),
1861 };
1862 static const unsigned int drif1_data1_a_mux[] = {
1863         RIF1_D1_A_MARK,
1864 };
1865 static const unsigned int drif1_ctrl_b_pins[] = {
1866         /* CLK, SYNC */
1867         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1868 };
1869 static const unsigned int drif1_ctrl_b_mux[] = {
1870         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1871 };
1872 static const unsigned int drif1_data0_b_pins[] = {
1873         /* D0 */
1874         RCAR_GP_PIN(5, 7),
1875 };
1876 static const unsigned int drif1_data0_b_mux[] = {
1877         RIF1_D0_B_MARK,
1878 };
1879 static const unsigned int drif1_data1_b_pins[] = {
1880         /* D1 */
1881         RCAR_GP_PIN(5, 8),
1882 };
1883 static const unsigned int drif1_data1_b_mux[] = {
1884         RIF1_D1_B_MARK,
1885 };
1886 static const unsigned int drif1_ctrl_c_pins[] = {
1887         /* CLK, SYNC */
1888         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1889 };
1890 static const unsigned int drif1_ctrl_c_mux[] = {
1891         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1892 };
1893 static const unsigned int drif1_data0_c_pins[] = {
1894         /* D0 */
1895         RCAR_GP_PIN(5, 6),
1896 };
1897 static const unsigned int drif1_data0_c_mux[] = {
1898         RIF1_D0_C_MARK,
1899 };
1900 static const unsigned int drif1_data1_c_pins[] = {
1901         /* D1 */
1902         RCAR_GP_PIN(5, 10),
1903 };
1904 static const unsigned int drif1_data1_c_mux[] = {
1905         RIF1_D1_C_MARK,
1906 };
1907 /* - DRIF2 --------------------------------------------------------------- */
1908 static const unsigned int drif2_ctrl_a_pins[] = {
1909         /* CLK, SYNC */
1910         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1911 };
1912 static const unsigned int drif2_ctrl_a_mux[] = {
1913         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1914 };
1915 static const unsigned int drif2_data0_a_pins[] = {
1916         /* D0 */
1917         RCAR_GP_PIN(6, 7),
1918 };
1919 static const unsigned int drif2_data0_a_mux[] = {
1920         RIF2_D0_A_MARK,
1921 };
1922 static const unsigned int drif2_data1_a_pins[] = {
1923         /* D1 */
1924         RCAR_GP_PIN(6, 10),
1925 };
1926 static const unsigned int drif2_data1_a_mux[] = {
1927         RIF2_D1_A_MARK,
1928 };
1929 static const unsigned int drif2_ctrl_b_pins[] = {
1930         /* CLK, SYNC */
1931         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1932 };
1933 static const unsigned int drif2_ctrl_b_mux[] = {
1934         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1935 };
1936 static const unsigned int drif2_data0_b_pins[] = {
1937         /* D0 */
1938         RCAR_GP_PIN(6, 30),
1939 };
1940 static const unsigned int drif2_data0_b_mux[] = {
1941         RIF2_D0_B_MARK,
1942 };
1943 static const unsigned int drif2_data1_b_pins[] = {
1944         /* D1 */
1945         RCAR_GP_PIN(6, 31),
1946 };
1947 static const unsigned int drif2_data1_b_mux[] = {
1948         RIF2_D1_B_MARK,
1949 };
1950 /* - DRIF3 --------------------------------------------------------------- */
1951 static const unsigned int drif3_ctrl_a_pins[] = {
1952         /* CLK, SYNC */
1953         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1954 };
1955 static const unsigned int drif3_ctrl_a_mux[] = {
1956         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1957 };
1958 static const unsigned int drif3_data0_a_pins[] = {
1959         /* D0 */
1960         RCAR_GP_PIN(6, 19),
1961 };
1962 static const unsigned int drif3_data0_a_mux[] = {
1963         RIF3_D0_A_MARK,
1964 };
1965 static const unsigned int drif3_data1_a_pins[] = {
1966         /* D1 */
1967         RCAR_GP_PIN(6, 20),
1968 };
1969 static const unsigned int drif3_data1_a_mux[] = {
1970         RIF3_D1_A_MARK,
1971 };
1972 static const unsigned int drif3_ctrl_b_pins[] = {
1973         /* CLK, SYNC */
1974         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1975 };
1976 static const unsigned int drif3_ctrl_b_mux[] = {
1977         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1978 };
1979 static const unsigned int drif3_data0_b_pins[] = {
1980         /* D0 */
1981         RCAR_GP_PIN(6, 28),
1982 };
1983 static const unsigned int drif3_data0_b_mux[] = {
1984         RIF3_D0_B_MARK,
1985 };
1986 static const unsigned int drif3_data1_b_pins[] = {
1987         /* D1 */
1988         RCAR_GP_PIN(6, 29),
1989 };
1990 static const unsigned int drif3_data1_b_mux[] = {
1991         RIF3_D1_B_MARK,
1992 };
1993
1994 /* - DU --------------------------------------------------------------------- */
1995 static const unsigned int du_rgb666_pins[] = {
1996         /* R[7:2], G[7:2], B[7:2] */
1997         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1998         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1999         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2000         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2001         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2002         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2003 };
2004 static const unsigned int du_rgb666_mux[] = {
2005         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2006         DU_DR3_MARK, DU_DR2_MARK,
2007         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2008         DU_DG3_MARK, DU_DG2_MARK,
2009         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2010         DU_DB3_MARK, DU_DB2_MARK,
2011 };
2012 static const unsigned int du_rgb888_pins[] = {
2013         /* R[7:0], G[7:0], B[7:0] */
2014         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2015         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2016         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2017         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2018         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2019         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2020         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2021         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2022         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2023 };
2024 static const unsigned int du_rgb888_mux[] = {
2025         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2026         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2027         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2028         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2029         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2030         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2031 };
2032 static const unsigned int du_clk_out_0_pins[] = {
2033         /* CLKOUT */
2034         RCAR_GP_PIN(1, 27),
2035 };
2036 static const unsigned int du_clk_out_0_mux[] = {
2037         DU_DOTCLKOUT0_MARK
2038 };
2039 static const unsigned int du_clk_out_1_pins[] = {
2040         /* CLKOUT */
2041         RCAR_GP_PIN(2, 3),
2042 };
2043 static const unsigned int du_clk_out_1_mux[] = {
2044         DU_DOTCLKOUT1_MARK
2045 };
2046 static const unsigned int du_sync_pins[] = {
2047         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2048         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2049 };
2050 static const unsigned int du_sync_mux[] = {
2051         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2052 };
2053 static const unsigned int du_oddf_pins[] = {
2054         /* EXDISP/EXODDF/EXCDE */
2055         RCAR_GP_PIN(2, 2),
2056 };
2057 static const unsigned int du_oddf_mux[] = {
2058         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2059 };
2060 static const unsigned int du_cde_pins[] = {
2061         /* CDE */
2062         RCAR_GP_PIN(2, 0),
2063 };
2064 static const unsigned int du_cde_mux[] = {
2065         DU_CDE_MARK,
2066 };
2067 static const unsigned int du_disp_pins[] = {
2068         /* DISP */
2069         RCAR_GP_PIN(2, 1),
2070 };
2071 static const unsigned int du_disp_mux[] = {
2072         DU_DISP_MARK,
2073 };
2074 /* - HDMI ------------------------------------------------------------------- */
2075 static const unsigned int hdmi0_cec_pins[] = {
2076         /* HDMI0_CEC */
2077         RCAR_GP_PIN(7, 2),
2078 };
2079 static const unsigned int hdmi0_cec_mux[] = {
2080         HDMI0_CEC_MARK,
2081 };
2082 static const unsigned int hdmi1_cec_pins[] = {
2083         /* HDMI1_CEC */
2084         RCAR_GP_PIN(7, 3),
2085 };
2086 static const unsigned int hdmi1_cec_mux[] = {
2087         HDMI1_CEC_MARK,
2088 };
2089
2090 /* - HSCIF0 ----------------------------------------------------------------- */
2091 static const unsigned int hscif0_data_pins[] = {
2092         /* RX, TX */
2093         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2094 };
2095 static const unsigned int hscif0_data_mux[] = {
2096         HRX0_MARK, HTX0_MARK,
2097 };
2098 static const unsigned int hscif0_clk_pins[] = {
2099         /* SCK */
2100         RCAR_GP_PIN(5, 12),
2101 };
2102 static const unsigned int hscif0_clk_mux[] = {
2103         HSCK0_MARK,
2104 };
2105 static const unsigned int hscif0_ctrl_pins[] = {
2106         /* RTS, CTS */
2107         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2108 };
2109 static const unsigned int hscif0_ctrl_mux[] = {
2110         HRTS0_N_MARK, HCTS0_N_MARK,
2111 };
2112 /* - HSCIF1 ----------------------------------------------------------------- */
2113 static const unsigned int hscif1_data_a_pins[] = {
2114         /* RX, TX */
2115         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2116 };
2117 static const unsigned int hscif1_data_a_mux[] = {
2118         HRX1_A_MARK, HTX1_A_MARK,
2119 };
2120 static const unsigned int hscif1_clk_a_pins[] = {
2121         /* SCK */
2122         RCAR_GP_PIN(6, 21),
2123 };
2124 static const unsigned int hscif1_clk_a_mux[] = {
2125         HSCK1_A_MARK,
2126 };
2127 static const unsigned int hscif1_ctrl_a_pins[] = {
2128         /* RTS, CTS */
2129         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2130 };
2131 static const unsigned int hscif1_ctrl_a_mux[] = {
2132         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2133 };
2134
2135 static const unsigned int hscif1_data_b_pins[] = {
2136         /* RX, TX */
2137         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2138 };
2139 static const unsigned int hscif1_data_b_mux[] = {
2140         HRX1_B_MARK, HTX1_B_MARK,
2141 };
2142 static const unsigned int hscif1_clk_b_pins[] = {
2143         /* SCK */
2144         RCAR_GP_PIN(5, 0),
2145 };
2146 static const unsigned int hscif1_clk_b_mux[] = {
2147         HSCK1_B_MARK,
2148 };
2149 static const unsigned int hscif1_ctrl_b_pins[] = {
2150         /* RTS, CTS */
2151         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2152 };
2153 static const unsigned int hscif1_ctrl_b_mux[] = {
2154         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2155 };
2156 /* - HSCIF2 ----------------------------------------------------------------- */
2157 static const unsigned int hscif2_data_a_pins[] = {
2158         /* RX, TX */
2159         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2160 };
2161 static const unsigned int hscif2_data_a_mux[] = {
2162         HRX2_A_MARK, HTX2_A_MARK,
2163 };
2164 static const unsigned int hscif2_clk_a_pins[] = {
2165         /* SCK */
2166         RCAR_GP_PIN(6, 10),
2167 };
2168 static const unsigned int hscif2_clk_a_mux[] = {
2169         HSCK2_A_MARK,
2170 };
2171 static const unsigned int hscif2_ctrl_a_pins[] = {
2172         /* RTS, CTS */
2173         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2174 };
2175 static const unsigned int hscif2_ctrl_a_mux[] = {
2176         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2177 };
2178
2179 static const unsigned int hscif2_data_b_pins[] = {
2180         /* RX, TX */
2181         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2182 };
2183 static const unsigned int hscif2_data_b_mux[] = {
2184         HRX2_B_MARK, HTX2_B_MARK,
2185 };
2186 static const unsigned int hscif2_clk_b_pins[] = {
2187         /* SCK */
2188         RCAR_GP_PIN(6, 21),
2189 };
2190 static const unsigned int hscif2_clk_b_mux[] = {
2191         HSCK2_B_MARK,
2192 };
2193 static const unsigned int hscif2_ctrl_b_pins[] = {
2194         /* RTS, CTS */
2195         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2196 };
2197 static const unsigned int hscif2_ctrl_b_mux[] = {
2198         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2199 };
2200 /* - HSCIF3 ----------------------------------------------------------------- */
2201 static const unsigned int hscif3_data_a_pins[] = {
2202         /* RX, TX */
2203         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2204 };
2205 static const unsigned int hscif3_data_a_mux[] = {
2206         HRX3_A_MARK, HTX3_A_MARK,
2207 };
2208 static const unsigned int hscif3_clk_pins[] = {
2209         /* SCK */
2210         RCAR_GP_PIN(1, 22),
2211 };
2212 static const unsigned int hscif3_clk_mux[] = {
2213         HSCK3_MARK,
2214 };
2215 static const unsigned int hscif3_ctrl_pins[] = {
2216         /* RTS, CTS */
2217         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2218 };
2219 static const unsigned int hscif3_ctrl_mux[] = {
2220         HRTS3_N_MARK, HCTS3_N_MARK,
2221 };
2222
2223 static const unsigned int hscif3_data_b_pins[] = {
2224         /* RX, TX */
2225         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2226 };
2227 static const unsigned int hscif3_data_b_mux[] = {
2228         HRX3_B_MARK, HTX3_B_MARK,
2229 };
2230 static const unsigned int hscif3_data_c_pins[] = {
2231         /* RX, TX */
2232         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2233 };
2234 static const unsigned int hscif3_data_c_mux[] = {
2235         HRX3_C_MARK, HTX3_C_MARK,
2236 };
2237 static const unsigned int hscif3_data_d_pins[] = {
2238         /* RX, TX */
2239         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2240 };
2241 static const unsigned int hscif3_data_d_mux[] = {
2242         HRX3_D_MARK, HTX3_D_MARK,
2243 };
2244 /* - HSCIF4 ----------------------------------------------------------------- */
2245 static const unsigned int hscif4_data_a_pins[] = {
2246         /* RX, TX */
2247         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2248 };
2249 static const unsigned int hscif4_data_a_mux[] = {
2250         HRX4_A_MARK, HTX4_A_MARK,
2251 };
2252 static const unsigned int hscif4_clk_pins[] = {
2253         /* SCK */
2254         RCAR_GP_PIN(1, 11),
2255 };
2256 static const unsigned int hscif4_clk_mux[] = {
2257         HSCK4_MARK,
2258 };
2259 static const unsigned int hscif4_ctrl_pins[] = {
2260         /* RTS, CTS */
2261         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2262 };
2263 static const unsigned int hscif4_ctrl_mux[] = {
2264         HRTS4_N_MARK, HCTS4_N_MARK,
2265 };
2266
2267 static const unsigned int hscif4_data_b_pins[] = {
2268         /* RX, TX */
2269         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2270 };
2271 static const unsigned int hscif4_data_b_mux[] = {
2272         HRX4_B_MARK, HTX4_B_MARK,
2273 };
2274
2275 /* - I2C -------------------------------------------------------------------- */
2276 static const unsigned int i2c0_pins[] = {
2277         /* SCL, SDA */
2278         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2279 };
2280
2281 static const unsigned int i2c0_mux[] = {
2282         SCL0_MARK, SDA0_MARK,
2283 };
2284
2285 static const unsigned int i2c1_a_pins[] = {
2286         /* SDA, SCL */
2287         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2288 };
2289 static const unsigned int i2c1_a_mux[] = {
2290         SDA1_A_MARK, SCL1_A_MARK,
2291 };
2292 static const unsigned int i2c1_b_pins[] = {
2293         /* SDA, SCL */
2294         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2295 };
2296 static const unsigned int i2c1_b_mux[] = {
2297         SDA1_B_MARK, SCL1_B_MARK,
2298 };
2299 static const unsigned int i2c2_a_pins[] = {
2300         /* SDA, SCL */
2301         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2302 };
2303 static const unsigned int i2c2_a_mux[] = {
2304         SDA2_A_MARK, SCL2_A_MARK,
2305 };
2306 static const unsigned int i2c2_b_pins[] = {
2307         /* SDA, SCL */
2308         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2309 };
2310 static const unsigned int i2c2_b_mux[] = {
2311         SDA2_B_MARK, SCL2_B_MARK,
2312 };
2313
2314 static const unsigned int i2c3_pins[] = {
2315         /* SCL, SDA */
2316         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2317 };
2318
2319 static const unsigned int i2c3_mux[] = {
2320         SCL3_MARK, SDA3_MARK,
2321 };
2322
2323 static const unsigned int i2c5_pins[] = {
2324         /* SCL, SDA */
2325         RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2326 };
2327
2328 static const unsigned int i2c5_mux[] = {
2329         SCL5_MARK, SDA5_MARK,
2330 };
2331
2332 static const unsigned int i2c6_a_pins[] = {
2333         /* SDA, SCL */
2334         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2335 };
2336 static const unsigned int i2c6_a_mux[] = {
2337         SDA6_A_MARK, SCL6_A_MARK,
2338 };
2339 static const unsigned int i2c6_b_pins[] = {
2340         /* SDA, SCL */
2341         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2342 };
2343 static const unsigned int i2c6_b_mux[] = {
2344         SDA6_B_MARK, SCL6_B_MARK,
2345 };
2346 static const unsigned int i2c6_c_pins[] = {
2347         /* SDA, SCL */
2348         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2349 };
2350 static const unsigned int i2c6_c_mux[] = {
2351         SDA6_C_MARK, SCL6_C_MARK,
2352 };
2353
2354 /* - INTC-EX ---------------------------------------------------------------- */
2355 static const unsigned int intc_ex_irq0_pins[] = {
2356         /* IRQ0 */
2357         RCAR_GP_PIN(2, 0),
2358 };
2359 static const unsigned int intc_ex_irq0_mux[] = {
2360         IRQ0_MARK,
2361 };
2362 static const unsigned int intc_ex_irq1_pins[] = {
2363         /* IRQ1 */
2364         RCAR_GP_PIN(2, 1),
2365 };
2366 static const unsigned int intc_ex_irq1_mux[] = {
2367         IRQ1_MARK,
2368 };
2369 static const unsigned int intc_ex_irq2_pins[] = {
2370         /* IRQ2 */
2371         RCAR_GP_PIN(2, 2),
2372 };
2373 static const unsigned int intc_ex_irq2_mux[] = {
2374         IRQ2_MARK,
2375 };
2376 static const unsigned int intc_ex_irq3_pins[] = {
2377         /* IRQ3 */
2378         RCAR_GP_PIN(2, 3),
2379 };
2380 static const unsigned int intc_ex_irq3_mux[] = {
2381         IRQ3_MARK,
2382 };
2383 static const unsigned int intc_ex_irq4_pins[] = {
2384         /* IRQ4 */
2385         RCAR_GP_PIN(2, 4),
2386 };
2387 static const unsigned int intc_ex_irq4_mux[] = {
2388         IRQ4_MARK,
2389 };
2390 static const unsigned int intc_ex_irq5_pins[] = {
2391         /* IRQ5 */
2392         RCAR_GP_PIN(2, 5),
2393 };
2394 static const unsigned int intc_ex_irq5_mux[] = {
2395         IRQ5_MARK,
2396 };
2397
2398 /* - MSIOF0 ----------------------------------------------------------------- */
2399 static const unsigned int msiof0_clk_pins[] = {
2400         /* SCK */
2401         RCAR_GP_PIN(5, 17),
2402 };
2403 static const unsigned int msiof0_clk_mux[] = {
2404         MSIOF0_SCK_MARK,
2405 };
2406 static const unsigned int msiof0_sync_pins[] = {
2407         /* SYNC */
2408         RCAR_GP_PIN(5, 18),
2409 };
2410 static const unsigned int msiof0_sync_mux[] = {
2411         MSIOF0_SYNC_MARK,
2412 };
2413 static const unsigned int msiof0_ss1_pins[] = {
2414         /* SS1 */
2415         RCAR_GP_PIN(5, 19),
2416 };
2417 static const unsigned int msiof0_ss1_mux[] = {
2418         MSIOF0_SS1_MARK,
2419 };
2420 static const unsigned int msiof0_ss2_pins[] = {
2421         /* SS2 */
2422         RCAR_GP_PIN(5, 21),
2423 };
2424 static const unsigned int msiof0_ss2_mux[] = {
2425         MSIOF0_SS2_MARK,
2426 };
2427 static const unsigned int msiof0_txd_pins[] = {
2428         /* TXD */
2429         RCAR_GP_PIN(5, 20),
2430 };
2431 static const unsigned int msiof0_txd_mux[] = {
2432         MSIOF0_TXD_MARK,
2433 };
2434 static const unsigned int msiof0_rxd_pins[] = {
2435         /* RXD */
2436         RCAR_GP_PIN(5, 22),
2437 };
2438 static const unsigned int msiof0_rxd_mux[] = {
2439         MSIOF0_RXD_MARK,
2440 };
2441 /* - MSIOF1 ----------------------------------------------------------------- */
2442 static const unsigned int msiof1_clk_a_pins[] = {
2443         /* SCK */
2444         RCAR_GP_PIN(6, 8),
2445 };
2446 static const unsigned int msiof1_clk_a_mux[] = {
2447         MSIOF1_SCK_A_MARK,
2448 };
2449 static const unsigned int msiof1_sync_a_pins[] = {
2450         /* SYNC */
2451         RCAR_GP_PIN(6, 9),
2452 };
2453 static const unsigned int msiof1_sync_a_mux[] = {
2454         MSIOF1_SYNC_A_MARK,
2455 };
2456 static const unsigned int msiof1_ss1_a_pins[] = {
2457         /* SS1 */
2458         RCAR_GP_PIN(6, 5),
2459 };
2460 static const unsigned int msiof1_ss1_a_mux[] = {
2461         MSIOF1_SS1_A_MARK,
2462 };
2463 static const unsigned int msiof1_ss2_a_pins[] = {
2464         /* SS2 */
2465         RCAR_GP_PIN(6, 6),
2466 };
2467 static const unsigned int msiof1_ss2_a_mux[] = {
2468         MSIOF1_SS2_A_MARK,
2469 };
2470 static const unsigned int msiof1_txd_a_pins[] = {
2471         /* TXD */
2472         RCAR_GP_PIN(6, 7),
2473 };
2474 static const unsigned int msiof1_txd_a_mux[] = {
2475         MSIOF1_TXD_A_MARK,
2476 };
2477 static const unsigned int msiof1_rxd_a_pins[] = {
2478         /* RXD */
2479         RCAR_GP_PIN(6, 10),
2480 };
2481 static const unsigned int msiof1_rxd_a_mux[] = {
2482         MSIOF1_RXD_A_MARK,
2483 };
2484 static const unsigned int msiof1_clk_b_pins[] = {
2485         /* SCK */
2486         RCAR_GP_PIN(5, 9),
2487 };
2488 static const unsigned int msiof1_clk_b_mux[] = {
2489         MSIOF1_SCK_B_MARK,
2490 };
2491 static const unsigned int msiof1_sync_b_pins[] = {
2492         /* SYNC */
2493         RCAR_GP_PIN(5, 3),
2494 };
2495 static const unsigned int msiof1_sync_b_mux[] = {
2496         MSIOF1_SYNC_B_MARK,
2497 };
2498 static const unsigned int msiof1_ss1_b_pins[] = {
2499         /* SS1 */
2500         RCAR_GP_PIN(5, 4),
2501 };
2502 static const unsigned int msiof1_ss1_b_mux[] = {
2503         MSIOF1_SS1_B_MARK,
2504 };
2505 static const unsigned int msiof1_ss2_b_pins[] = {
2506         /* SS2 */
2507         RCAR_GP_PIN(5, 0),
2508 };
2509 static const unsigned int msiof1_ss2_b_mux[] = {
2510         MSIOF1_SS2_B_MARK,
2511 };
2512 static const unsigned int msiof1_txd_b_pins[] = {
2513         /* TXD */
2514         RCAR_GP_PIN(5, 8),
2515 };
2516 static const unsigned int msiof1_txd_b_mux[] = {
2517         MSIOF1_TXD_B_MARK,
2518 };
2519 static const unsigned int msiof1_rxd_b_pins[] = {
2520         /* RXD */
2521         RCAR_GP_PIN(5, 7),
2522 };
2523 static const unsigned int msiof1_rxd_b_mux[] = {
2524         MSIOF1_RXD_B_MARK,
2525 };
2526 static const unsigned int msiof1_clk_c_pins[] = {
2527         /* SCK */
2528         RCAR_GP_PIN(6, 17),
2529 };
2530 static const unsigned int msiof1_clk_c_mux[] = {
2531         MSIOF1_SCK_C_MARK,
2532 };
2533 static const unsigned int msiof1_sync_c_pins[] = {
2534         /* SYNC */
2535         RCAR_GP_PIN(6, 18),
2536 };
2537 static const unsigned int msiof1_sync_c_mux[] = {
2538         MSIOF1_SYNC_C_MARK,
2539 };
2540 static const unsigned int msiof1_ss1_c_pins[] = {
2541         /* SS1 */
2542         RCAR_GP_PIN(6, 21),
2543 };
2544 static const unsigned int msiof1_ss1_c_mux[] = {
2545         MSIOF1_SS1_C_MARK,
2546 };
2547 static const unsigned int msiof1_ss2_c_pins[] = {
2548         /* SS2 */
2549         RCAR_GP_PIN(6, 27),
2550 };
2551 static const unsigned int msiof1_ss2_c_mux[] = {
2552         MSIOF1_SS2_C_MARK,
2553 };
2554 static const unsigned int msiof1_txd_c_pins[] = {
2555         /* TXD */
2556         RCAR_GP_PIN(6, 20),
2557 };
2558 static const unsigned int msiof1_txd_c_mux[] = {
2559         MSIOF1_TXD_C_MARK,
2560 };
2561 static const unsigned int msiof1_rxd_c_pins[] = {
2562         /* RXD */
2563         RCAR_GP_PIN(6, 19),
2564 };
2565 static const unsigned int msiof1_rxd_c_mux[] = {
2566         MSIOF1_RXD_C_MARK,
2567 };
2568 static const unsigned int msiof1_clk_d_pins[] = {
2569         /* SCK */
2570         RCAR_GP_PIN(5, 12),
2571 };
2572 static const unsigned int msiof1_clk_d_mux[] = {
2573         MSIOF1_SCK_D_MARK,
2574 };
2575 static const unsigned int msiof1_sync_d_pins[] = {
2576         /* SYNC */
2577         RCAR_GP_PIN(5, 15),
2578 };
2579 static const unsigned int msiof1_sync_d_mux[] = {
2580         MSIOF1_SYNC_D_MARK,
2581 };
2582 static const unsigned int msiof1_ss1_d_pins[] = {
2583         /* SS1 */
2584         RCAR_GP_PIN(5, 16),
2585 };
2586 static const unsigned int msiof1_ss1_d_mux[] = {
2587         MSIOF1_SS1_D_MARK,
2588 };
2589 static const unsigned int msiof1_ss2_d_pins[] = {
2590         /* SS2 */
2591         RCAR_GP_PIN(5, 21),
2592 };
2593 static const unsigned int msiof1_ss2_d_mux[] = {
2594         MSIOF1_SS2_D_MARK,
2595 };
2596 static const unsigned int msiof1_txd_d_pins[] = {
2597         /* TXD */
2598         RCAR_GP_PIN(5, 14),
2599 };
2600 static const unsigned int msiof1_txd_d_mux[] = {
2601         MSIOF1_TXD_D_MARK,
2602 };
2603 static const unsigned int msiof1_rxd_d_pins[] = {
2604         /* RXD */
2605         RCAR_GP_PIN(5, 13),
2606 };
2607 static const unsigned int msiof1_rxd_d_mux[] = {
2608         MSIOF1_RXD_D_MARK,
2609 };
2610 static const unsigned int msiof1_clk_e_pins[] = {
2611         /* SCK */
2612         RCAR_GP_PIN(3, 0),
2613 };
2614 static const unsigned int msiof1_clk_e_mux[] = {
2615         MSIOF1_SCK_E_MARK,
2616 };
2617 static const unsigned int msiof1_sync_e_pins[] = {
2618         /* SYNC */
2619         RCAR_GP_PIN(3, 1),
2620 };
2621 static const unsigned int msiof1_sync_e_mux[] = {
2622         MSIOF1_SYNC_E_MARK,
2623 };
2624 static const unsigned int msiof1_ss1_e_pins[] = {
2625         /* SS1 */
2626         RCAR_GP_PIN(3, 4),
2627 };
2628 static const unsigned int msiof1_ss1_e_mux[] = {
2629         MSIOF1_SS1_E_MARK,
2630 };
2631 static const unsigned int msiof1_ss2_e_pins[] = {
2632         /* SS2 */
2633         RCAR_GP_PIN(3, 5),
2634 };
2635 static const unsigned int msiof1_ss2_e_mux[] = {
2636         MSIOF1_SS2_E_MARK,
2637 };
2638 static const unsigned int msiof1_txd_e_pins[] = {
2639         /* TXD */
2640         RCAR_GP_PIN(3, 3),
2641 };
2642 static const unsigned int msiof1_txd_e_mux[] = {
2643         MSIOF1_TXD_E_MARK,
2644 };
2645 static const unsigned int msiof1_rxd_e_pins[] = {
2646         /* RXD */
2647         RCAR_GP_PIN(3, 2),
2648 };
2649 static const unsigned int msiof1_rxd_e_mux[] = {
2650         MSIOF1_RXD_E_MARK,
2651 };
2652 static const unsigned int msiof1_clk_f_pins[] = {
2653         /* SCK */
2654         RCAR_GP_PIN(5, 23),
2655 };
2656 static const unsigned int msiof1_clk_f_mux[] = {
2657         MSIOF1_SCK_F_MARK,
2658 };
2659 static const unsigned int msiof1_sync_f_pins[] = {
2660         /* SYNC */
2661         RCAR_GP_PIN(5, 24),
2662 };
2663 static const unsigned int msiof1_sync_f_mux[] = {
2664         MSIOF1_SYNC_F_MARK,
2665 };
2666 static const unsigned int msiof1_ss1_f_pins[] = {
2667         /* SS1 */
2668         RCAR_GP_PIN(6, 1),
2669 };
2670 static const unsigned int msiof1_ss1_f_mux[] = {
2671         MSIOF1_SS1_F_MARK,
2672 };
2673 static const unsigned int msiof1_ss2_f_pins[] = {
2674         /* SS2 */
2675         RCAR_GP_PIN(6, 2),
2676 };
2677 static const unsigned int msiof1_ss2_f_mux[] = {
2678         MSIOF1_SS2_F_MARK,
2679 };
2680 static const unsigned int msiof1_txd_f_pins[] = {
2681         /* TXD */
2682         RCAR_GP_PIN(6, 0),
2683 };
2684 static const unsigned int msiof1_txd_f_mux[] = {
2685         MSIOF1_TXD_F_MARK,
2686 };
2687 static const unsigned int msiof1_rxd_f_pins[] = {
2688         /* RXD */
2689         RCAR_GP_PIN(5, 25),
2690 };
2691 static const unsigned int msiof1_rxd_f_mux[] = {
2692         MSIOF1_RXD_F_MARK,
2693 };
2694 static const unsigned int msiof1_clk_g_pins[] = {
2695         /* SCK */
2696         RCAR_GP_PIN(3, 6),
2697 };
2698 static const unsigned int msiof1_clk_g_mux[] = {
2699         MSIOF1_SCK_G_MARK,
2700 };
2701 static const unsigned int msiof1_sync_g_pins[] = {
2702         /* SYNC */
2703         RCAR_GP_PIN(3, 7),
2704 };
2705 static const unsigned int msiof1_sync_g_mux[] = {
2706         MSIOF1_SYNC_G_MARK,
2707 };
2708 static const unsigned int msiof1_ss1_g_pins[] = {
2709         /* SS1 */
2710         RCAR_GP_PIN(3, 10),
2711 };
2712 static const unsigned int msiof1_ss1_g_mux[] = {
2713         MSIOF1_SS1_G_MARK,
2714 };
2715 static const unsigned int msiof1_ss2_g_pins[] = {
2716         /* SS2 */
2717         RCAR_GP_PIN(3, 11),
2718 };
2719 static const unsigned int msiof1_ss2_g_mux[] = {
2720         MSIOF1_SS2_G_MARK,
2721 };
2722 static const unsigned int msiof1_txd_g_pins[] = {
2723         /* TXD */
2724         RCAR_GP_PIN(3, 9),
2725 };
2726 static const unsigned int msiof1_txd_g_mux[] = {
2727         MSIOF1_TXD_G_MARK,
2728 };
2729 static const unsigned int msiof1_rxd_g_pins[] = {
2730         /* RXD */
2731         RCAR_GP_PIN(3, 8),
2732 };
2733 static const unsigned int msiof1_rxd_g_mux[] = {
2734         MSIOF1_RXD_G_MARK,
2735 };
2736 /* - MSIOF2 ----------------------------------------------------------------- */
2737 static const unsigned int msiof2_clk_a_pins[] = {
2738         /* SCK */
2739         RCAR_GP_PIN(1, 9),
2740 };
2741 static const unsigned int msiof2_clk_a_mux[] = {
2742         MSIOF2_SCK_A_MARK,
2743 };
2744 static const unsigned int msiof2_sync_a_pins[] = {
2745         /* SYNC */
2746         RCAR_GP_PIN(1, 8),
2747 };
2748 static const unsigned int msiof2_sync_a_mux[] = {
2749         MSIOF2_SYNC_A_MARK,
2750 };
2751 static const unsigned int msiof2_ss1_a_pins[] = {
2752         /* SS1 */
2753         RCAR_GP_PIN(1, 6),
2754 };
2755 static const unsigned int msiof2_ss1_a_mux[] = {
2756         MSIOF2_SS1_A_MARK,
2757 };
2758 static const unsigned int msiof2_ss2_a_pins[] = {
2759         /* SS2 */
2760         RCAR_GP_PIN(1, 7),
2761 };
2762 static const unsigned int msiof2_ss2_a_mux[] = {
2763         MSIOF2_SS2_A_MARK,
2764 };
2765 static const unsigned int msiof2_txd_a_pins[] = {
2766         /* TXD */
2767         RCAR_GP_PIN(1, 11),
2768 };
2769 static const unsigned int msiof2_txd_a_mux[] = {
2770         MSIOF2_TXD_A_MARK,
2771 };
2772 static const unsigned int msiof2_rxd_a_pins[] = {
2773         /* RXD */
2774         RCAR_GP_PIN(1, 10),
2775 };
2776 static const unsigned int msiof2_rxd_a_mux[] = {
2777         MSIOF2_RXD_A_MARK,
2778 };
2779 static const unsigned int msiof2_clk_b_pins[] = {
2780         /* SCK */
2781         RCAR_GP_PIN(0, 4),
2782 };
2783 static const unsigned int msiof2_clk_b_mux[] = {
2784         MSIOF2_SCK_B_MARK,
2785 };
2786 static const unsigned int msiof2_sync_b_pins[] = {
2787         /* SYNC */
2788         RCAR_GP_PIN(0, 5),
2789 };
2790 static const unsigned int msiof2_sync_b_mux[] = {
2791         MSIOF2_SYNC_B_MARK,
2792 };
2793 static const unsigned int msiof2_ss1_b_pins[] = {
2794         /* SS1 */
2795         RCAR_GP_PIN(0, 0),
2796 };
2797 static const unsigned int msiof2_ss1_b_mux[] = {
2798         MSIOF2_SS1_B_MARK,
2799 };
2800 static const unsigned int msiof2_ss2_b_pins[] = {
2801         /* SS2 */
2802         RCAR_GP_PIN(0, 1),
2803 };
2804 static const unsigned int msiof2_ss2_b_mux[] = {
2805         MSIOF2_SS2_B_MARK,
2806 };
2807 static const unsigned int msiof2_txd_b_pins[] = {
2808         /* TXD */
2809         RCAR_GP_PIN(0, 7),
2810 };
2811 static const unsigned int msiof2_txd_b_mux[] = {
2812         MSIOF2_TXD_B_MARK,
2813 };
2814 static const unsigned int msiof2_rxd_b_pins[] = {
2815         /* RXD */
2816         RCAR_GP_PIN(0, 6),
2817 };
2818 static const unsigned int msiof2_rxd_b_mux[] = {
2819         MSIOF2_RXD_B_MARK,
2820 };
2821 static const unsigned int msiof2_clk_c_pins[] = {
2822         /* SCK */
2823         RCAR_GP_PIN(2, 12),
2824 };
2825 static const unsigned int msiof2_clk_c_mux[] = {
2826         MSIOF2_SCK_C_MARK,
2827 };
2828 static const unsigned int msiof2_sync_c_pins[] = {
2829         /* SYNC */
2830         RCAR_GP_PIN(2, 11),
2831 };
2832 static const unsigned int msiof2_sync_c_mux[] = {
2833         MSIOF2_SYNC_C_MARK,
2834 };
2835 static const unsigned int msiof2_ss1_c_pins[] = {
2836         /* SS1 */
2837         RCAR_GP_PIN(2, 10),
2838 };
2839 static const unsigned int msiof2_ss1_c_mux[] = {
2840         MSIOF2_SS1_C_MARK,
2841 };
2842 static const unsigned int msiof2_ss2_c_pins[] = {
2843         /* SS2 */
2844         RCAR_GP_PIN(2, 9),
2845 };
2846 static const unsigned int msiof2_ss2_c_mux[] = {
2847         MSIOF2_SS2_C_MARK,
2848 };
2849 static const unsigned int msiof2_txd_c_pins[] = {
2850         /* TXD */
2851         RCAR_GP_PIN(2, 14),
2852 };
2853 static const unsigned int msiof2_txd_c_mux[] = {
2854         MSIOF2_TXD_C_MARK,
2855 };
2856 static const unsigned int msiof2_rxd_c_pins[] = {
2857         /* RXD */
2858         RCAR_GP_PIN(2, 13),
2859 };
2860 static const unsigned int msiof2_rxd_c_mux[] = {
2861         MSIOF2_RXD_C_MARK,
2862 };
2863 static const unsigned int msiof2_clk_d_pins[] = {
2864         /* SCK */
2865         RCAR_GP_PIN(0, 8),
2866 };
2867 static const unsigned int msiof2_clk_d_mux[] = {
2868         MSIOF2_SCK_D_MARK,
2869 };
2870 static const unsigned int msiof2_sync_d_pins[] = {
2871         /* SYNC */
2872         RCAR_GP_PIN(0, 9),
2873 };
2874 static const unsigned int msiof2_sync_d_mux[] = {
2875         MSIOF2_SYNC_D_MARK,
2876 };
2877 static const unsigned int msiof2_ss1_d_pins[] = {
2878         /* SS1 */
2879         RCAR_GP_PIN(0, 12),
2880 };
2881 static const unsigned int msiof2_ss1_d_mux[] = {
2882         MSIOF2_SS1_D_MARK,
2883 };
2884 static const unsigned int msiof2_ss2_d_pins[] = {
2885         /* SS2 */
2886         RCAR_GP_PIN(0, 13),
2887 };
2888 static const unsigned int msiof2_ss2_d_mux[] = {
2889         MSIOF2_SS2_D_MARK,
2890 };
2891 static const unsigned int msiof2_txd_d_pins[] = {
2892         /* TXD */
2893         RCAR_GP_PIN(0, 11),
2894 };
2895 static const unsigned int msiof2_txd_d_mux[] = {
2896         MSIOF2_TXD_D_MARK,
2897 };
2898 static const unsigned int msiof2_rxd_d_pins[] = {
2899         /* RXD */
2900         RCAR_GP_PIN(0, 10),
2901 };
2902 static const unsigned int msiof2_rxd_d_mux[] = {
2903         MSIOF2_RXD_D_MARK,
2904 };
2905 /* - MSIOF3 ----------------------------------------------------------------- */
2906 static const unsigned int msiof3_clk_a_pins[] = {
2907         /* SCK */
2908         RCAR_GP_PIN(0, 0),
2909 };
2910 static const unsigned int msiof3_clk_a_mux[] = {
2911         MSIOF3_SCK_A_MARK,
2912 };
2913 static const unsigned int msiof3_sync_a_pins[] = {
2914         /* SYNC */
2915         RCAR_GP_PIN(0, 1),
2916 };
2917 static const unsigned int msiof3_sync_a_mux[] = {
2918         MSIOF3_SYNC_A_MARK,
2919 };
2920 static const unsigned int msiof3_ss1_a_pins[] = {
2921         /* SS1 */
2922         RCAR_GP_PIN(0, 14),
2923 };
2924 static const unsigned int msiof3_ss1_a_mux[] = {
2925         MSIOF3_SS1_A_MARK,
2926 };
2927 static const unsigned int msiof3_ss2_a_pins[] = {
2928         /* SS2 */
2929         RCAR_GP_PIN(0, 15),
2930 };
2931 static const unsigned int msiof3_ss2_a_mux[] = {
2932         MSIOF3_SS2_A_MARK,
2933 };
2934 static const unsigned int msiof3_txd_a_pins[] = {
2935         /* TXD */
2936         RCAR_GP_PIN(0, 3),
2937 };
2938 static const unsigned int msiof3_txd_a_mux[] = {
2939         MSIOF3_TXD_A_MARK,
2940 };
2941 static const unsigned int msiof3_rxd_a_pins[] = {
2942         /* RXD */
2943         RCAR_GP_PIN(0, 2),
2944 };
2945 static const unsigned int msiof3_rxd_a_mux[] = {
2946         MSIOF3_RXD_A_MARK,
2947 };
2948 static const unsigned int msiof3_clk_b_pins[] = {
2949         /* SCK */
2950         RCAR_GP_PIN(1, 2),
2951 };
2952 static const unsigned int msiof3_clk_b_mux[] = {
2953         MSIOF3_SCK_B_MARK,
2954 };
2955 static const unsigned int msiof3_sync_b_pins[] = {
2956         /* SYNC */
2957         RCAR_GP_PIN(1, 0),
2958 };
2959 static const unsigned int msiof3_sync_b_mux[] = {
2960         MSIOF3_SYNC_B_MARK,
2961 };
2962 static const unsigned int msiof3_ss1_b_pins[] = {
2963         /* SS1 */
2964         RCAR_GP_PIN(1, 4),
2965 };
2966 static const unsigned int msiof3_ss1_b_mux[] = {
2967         MSIOF3_SS1_B_MARK,
2968 };
2969 static const unsigned int msiof3_ss2_b_pins[] = {
2970         /* SS2 */
2971         RCAR_GP_PIN(1, 5),
2972 };
2973 static const unsigned int msiof3_ss2_b_mux[] = {
2974         MSIOF3_SS2_B_MARK,
2975 };
2976 static const unsigned int msiof3_txd_b_pins[] = {
2977         /* TXD */
2978         RCAR_GP_PIN(1, 1),
2979 };
2980 static const unsigned int msiof3_txd_b_mux[] = {
2981         MSIOF3_TXD_B_MARK,
2982 };
2983 static const unsigned int msiof3_rxd_b_pins[] = {
2984         /* RXD */
2985         RCAR_GP_PIN(1, 3),
2986 };
2987 static const unsigned int msiof3_rxd_b_mux[] = {
2988         MSIOF3_RXD_B_MARK,
2989 };
2990 static const unsigned int msiof3_clk_c_pins[] = {
2991         /* SCK */
2992         RCAR_GP_PIN(1, 12),
2993 };
2994 static const unsigned int msiof3_clk_c_mux[] = {
2995         MSIOF3_SCK_C_MARK,
2996 };
2997 static const unsigned int msiof3_sync_c_pins[] = {
2998         /* SYNC */
2999         RCAR_GP_PIN(1, 13),
3000 };
3001 static const unsigned int msiof3_sync_c_mux[] = {
3002         MSIOF3_SYNC_C_MARK,
3003 };
3004 static const unsigned int msiof3_txd_c_pins[] = {
3005         /* TXD */
3006         RCAR_GP_PIN(1, 15),
3007 };
3008 static const unsigned int msiof3_txd_c_mux[] = {
3009         MSIOF3_TXD_C_MARK,
3010 };
3011 static const unsigned int msiof3_rxd_c_pins[] = {
3012         /* RXD */
3013         RCAR_GP_PIN(1, 14),
3014 };
3015 static const unsigned int msiof3_rxd_c_mux[] = {
3016         MSIOF3_RXD_C_MARK,
3017 };
3018 static const unsigned int msiof3_clk_d_pins[] = {
3019         /* SCK */
3020         RCAR_GP_PIN(1, 22),
3021 };
3022 static const unsigned int msiof3_clk_d_mux[] = {
3023         MSIOF3_SCK_D_MARK,
3024 };
3025 static const unsigned int msiof3_sync_d_pins[] = {
3026         /* SYNC */
3027         RCAR_GP_PIN(1, 23),
3028 };
3029 static const unsigned int msiof3_sync_d_mux[] = {
3030         MSIOF3_SYNC_D_MARK,
3031 };
3032 static const unsigned int msiof3_ss1_d_pins[] = {
3033         /* SS1 */
3034         RCAR_GP_PIN(1, 26),
3035 };
3036 static const unsigned int msiof3_ss1_d_mux[] = {
3037         MSIOF3_SS1_D_MARK,
3038 };
3039 static const unsigned int msiof3_txd_d_pins[] = {
3040         /* TXD */
3041         RCAR_GP_PIN(1, 25),
3042 };
3043 static const unsigned int msiof3_txd_d_mux[] = {
3044         MSIOF3_TXD_D_MARK,
3045 };
3046 static const unsigned int msiof3_rxd_d_pins[] = {
3047         /* RXD */
3048         RCAR_GP_PIN(1, 24),
3049 };
3050 static const unsigned int msiof3_rxd_d_mux[] = {
3051         MSIOF3_RXD_D_MARK,
3052 };
3053
3054 /* - PWM0 --------------------------------------------------------------------*/
3055 static const unsigned int pwm0_pins[] = {
3056         /* PWM */
3057         RCAR_GP_PIN(2, 6),
3058 };
3059 static const unsigned int pwm0_mux[] = {
3060         PWM0_MARK,
3061 };
3062 /* - PWM1 --------------------------------------------------------------------*/
3063 static const unsigned int pwm1_a_pins[] = {
3064         /* PWM */
3065         RCAR_GP_PIN(2, 7),
3066 };
3067 static const unsigned int pwm1_a_mux[] = {
3068         PWM1_A_MARK,
3069 };
3070 static const unsigned int pwm1_b_pins[] = {
3071         /* PWM */
3072         RCAR_GP_PIN(1, 8),
3073 };
3074 static const unsigned int pwm1_b_mux[] = {
3075         PWM1_B_MARK,
3076 };
3077 /* - PWM2 --------------------------------------------------------------------*/
3078 static const unsigned int pwm2_a_pins[] = {
3079         /* PWM */
3080         RCAR_GP_PIN(2, 8),
3081 };
3082 static const unsigned int pwm2_a_mux[] = {
3083         PWM2_A_MARK,
3084 };
3085 static const unsigned int pwm2_b_pins[] = {
3086         /* PWM */
3087         RCAR_GP_PIN(1, 11),
3088 };
3089 static const unsigned int pwm2_b_mux[] = {
3090         PWM2_B_MARK,
3091 };
3092 /* - PWM3 --------------------------------------------------------------------*/
3093 static const unsigned int pwm3_a_pins[] = {
3094         /* PWM */
3095         RCAR_GP_PIN(1, 0),
3096 };
3097 static const unsigned int pwm3_a_mux[] = {
3098         PWM3_A_MARK,
3099 };
3100 static const unsigned int pwm3_b_pins[] = {
3101         /* PWM */
3102         RCAR_GP_PIN(2, 2),
3103 };
3104 static const unsigned int pwm3_b_mux[] = {
3105         PWM3_B_MARK,
3106 };
3107 /* - PWM4 --------------------------------------------------------------------*/
3108 static const unsigned int pwm4_a_pins[] = {
3109         /* PWM */
3110         RCAR_GP_PIN(1, 1),
3111 };
3112 static const unsigned int pwm4_a_mux[] = {
3113         PWM4_A_MARK,
3114 };
3115 static const unsigned int pwm4_b_pins[] = {
3116         /* PWM */
3117         RCAR_GP_PIN(2, 3),
3118 };
3119 static const unsigned int pwm4_b_mux[] = {
3120         PWM4_B_MARK,
3121 };
3122 /* - PWM5 --------------------------------------------------------------------*/
3123 static const unsigned int pwm5_a_pins[] = {
3124         /* PWM */
3125         RCAR_GP_PIN(1, 2),
3126 };
3127 static const unsigned int pwm5_a_mux[] = {
3128         PWM5_A_MARK,
3129 };
3130 static const unsigned int pwm5_b_pins[] = {
3131         /* PWM */
3132         RCAR_GP_PIN(2, 4),
3133 };
3134 static const unsigned int pwm5_b_mux[] = {
3135         PWM5_B_MARK,
3136 };
3137 /* - PWM6 --------------------------------------------------------------------*/
3138 static const unsigned int pwm6_a_pins[] = {
3139         /* PWM */
3140         RCAR_GP_PIN(1, 3),
3141 };
3142 static const unsigned int pwm6_a_mux[] = {
3143         PWM6_A_MARK,
3144 };
3145 static const unsigned int pwm6_b_pins[] = {
3146         /* PWM */
3147         RCAR_GP_PIN(2, 5),
3148 };
3149 static const unsigned int pwm6_b_mux[] = {
3150         PWM6_B_MARK,
3151 };
3152
3153 /* - QSPI0 ------------------------------------------------------------------ */
3154 static const unsigned int qspi0_ctrl_pins[] = {
3155         /* QSPI0_SPCLK, QSPI0_SSL */
3156         PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3157 };
3158 static const unsigned int qspi0_ctrl_mux[] = {
3159         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3160 };
3161 static const unsigned int qspi0_data2_pins[] = {
3162         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3163         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3164 };
3165 static const unsigned int qspi0_data2_mux[] = {
3166         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3167 };
3168 static const unsigned int qspi0_data4_pins[] = {
3169         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3170         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3171         PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3172 };
3173 static const unsigned int qspi0_data4_mux[] = {
3174         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3175         QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3176 };
3177 /* - QSPI1 ------------------------------------------------------------------ */
3178 static const unsigned int qspi1_ctrl_pins[] = {
3179         /* QSPI1_SPCLK, QSPI1_SSL */
3180         PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3181 };
3182 static const unsigned int qspi1_ctrl_mux[] = {
3183         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3184 };
3185 static const unsigned int qspi1_data2_pins[] = {
3186         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3187         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3188 };
3189 static const unsigned int qspi1_data2_mux[] = {
3190         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3191 };
3192 static const unsigned int qspi1_data4_pins[] = {
3193         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3194         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3195         PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3196 };
3197 static const unsigned int qspi1_data4_mux[] = {
3198         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3199         QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3200 };
3201
3202 /* - SATA --------------------------------------------------------------------*/
3203 static const unsigned int sata0_devslp_a_pins[] = {
3204         /* DEVSLP */
3205         RCAR_GP_PIN(6, 16),
3206 };
3207 static const unsigned int sata0_devslp_a_mux[] = {
3208         SATA_DEVSLP_A_MARK,
3209 };
3210 static const unsigned int sata0_devslp_b_pins[] = {
3211         /* DEVSLP */
3212         RCAR_GP_PIN(4, 6),
3213 };
3214 static const unsigned int sata0_devslp_b_mux[] = {
3215         SATA_DEVSLP_B_MARK,
3216 };
3217
3218 /* - SCIF0 ------------------------------------------------------------------ */
3219 static const unsigned int scif0_data_pins[] = {
3220         /* RX, TX */
3221         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3222 };
3223 static const unsigned int scif0_data_mux[] = {
3224         RX0_MARK, TX0_MARK,
3225 };
3226 static const unsigned int scif0_clk_pins[] = {
3227         /* SCK */
3228         RCAR_GP_PIN(5, 0),
3229 };
3230 static const unsigned int scif0_clk_mux[] = {
3231         SCK0_MARK,
3232 };
3233 static const unsigned int scif0_ctrl_pins[] = {
3234         /* RTS, CTS */
3235         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3236 };
3237 static const unsigned int scif0_ctrl_mux[] = {
3238         RTS0_N_TANS_MARK, CTS0_N_MARK,
3239 };
3240 /* - SCIF1 ------------------------------------------------------------------ */
3241 static const unsigned int scif1_data_a_pins[] = {
3242         /* RX, TX */
3243         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3244 };
3245 static const unsigned int scif1_data_a_mux[] = {
3246         RX1_A_MARK, TX1_A_MARK,
3247 };
3248 static const unsigned int scif1_clk_pins[] = {
3249         /* SCK */
3250         RCAR_GP_PIN(6, 21),
3251 };
3252 static const unsigned int scif1_clk_mux[] = {
3253         SCK1_MARK,
3254 };
3255 static const unsigned int scif1_ctrl_pins[] = {
3256         /* RTS, CTS */
3257         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3258 };
3259 static const unsigned int scif1_ctrl_mux[] = {
3260         RTS1_N_TANS_MARK, CTS1_N_MARK,
3261 };
3262
3263 static const unsigned int scif1_data_b_pins[] = {
3264         /* RX, TX */
3265         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3266 };
3267 static const unsigned int scif1_data_b_mux[] = {
3268         RX1_B_MARK, TX1_B_MARK,
3269 };
3270 /* - SCIF2 ------------------------------------------------------------------ */
3271 static const unsigned int scif2_data_a_pins[] = {
3272         /* RX, TX */
3273         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3274 };
3275 static const unsigned int scif2_data_a_mux[] = {
3276         RX2_A_MARK, TX2_A_MARK,
3277 };
3278 static const unsigned int scif2_clk_pins[] = {
3279         /* SCK */
3280         RCAR_GP_PIN(5, 9),
3281 };
3282 static const unsigned int scif2_clk_mux[] = {
3283         SCK2_MARK,
3284 };
3285 static const unsigned int scif2_data_b_pins[] = {
3286         /* RX, TX */
3287         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3288 };
3289 static const unsigned int scif2_data_b_mux[] = {
3290         RX2_B_MARK, TX2_B_MARK,
3291 };
3292 /* - SCIF3 ------------------------------------------------------------------ */
3293 static const unsigned int scif3_data_a_pins[] = {
3294         /* RX, TX */
3295         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3296 };
3297 static const unsigned int scif3_data_a_mux[] = {
3298         RX3_A_MARK, TX3_A_MARK,
3299 };
3300 static const unsigned int scif3_clk_pins[] = {
3301         /* SCK */
3302         RCAR_GP_PIN(1, 22),
3303 };
3304 static const unsigned int scif3_clk_mux[] = {
3305         SCK3_MARK,
3306 };
3307 static const unsigned int scif3_ctrl_pins[] = {
3308         /* RTS, CTS */
3309         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3310 };
3311 static const unsigned int scif3_ctrl_mux[] = {
3312         RTS3_N_TANS_MARK, CTS3_N_MARK,
3313 };
3314 static const unsigned int scif3_data_b_pins[] = {
3315         /* RX, TX */
3316         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3317 };
3318 static const unsigned int scif3_data_b_mux[] = {
3319         RX3_B_MARK, TX3_B_MARK,
3320 };
3321 /* - SCIF4 ------------------------------------------------------------------ */
3322 static const unsigned int scif4_data_a_pins[] = {
3323         /* RX, TX */
3324         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3325 };
3326 static const unsigned int scif4_data_a_mux[] = {
3327         RX4_A_MARK, TX4_A_MARK,
3328 };
3329 static const unsigned int scif4_clk_a_pins[] = {
3330         /* SCK */
3331         RCAR_GP_PIN(2, 10),
3332 };
3333 static const unsigned int scif4_clk_a_mux[] = {
3334         SCK4_A_MARK,
3335 };
3336 static const unsigned int scif4_ctrl_a_pins[] = {
3337         /* RTS, CTS */
3338         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3339 };
3340 static const unsigned int scif4_ctrl_a_mux[] = {
3341         RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3342 };
3343 static const unsigned int scif4_data_b_pins[] = {
3344         /* RX, TX */
3345         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3346 };
3347 static const unsigned int scif4_data_b_mux[] = {
3348         RX4_B_MARK, TX4_B_MARK,
3349 };
3350 static const unsigned int scif4_clk_b_pins[] = {
3351         /* SCK */
3352         RCAR_GP_PIN(1, 5),
3353 };
3354 static const unsigned int scif4_clk_b_mux[] = {
3355         SCK4_B_MARK,
3356 };
3357 static const unsigned int scif4_ctrl_b_pins[] = {
3358         /* RTS, CTS */
3359         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3360 };
3361 static const unsigned int scif4_ctrl_b_mux[] = {
3362         RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3363 };
3364 static const unsigned int scif4_data_c_pins[] = {
3365         /* RX, TX */
3366         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3367 };
3368 static const unsigned int scif4_data_c_mux[] = {
3369         RX4_C_MARK, TX4_C_MARK,
3370 };
3371 static const unsigned int scif4_clk_c_pins[] = {
3372         /* SCK */
3373         RCAR_GP_PIN(0, 8),
3374 };
3375 static const unsigned int scif4_clk_c_mux[] = {
3376         SCK4_C_MARK,
3377 };
3378 static const unsigned int scif4_ctrl_c_pins[] = {
3379         /* RTS, CTS */
3380         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3381 };
3382 static const unsigned int scif4_ctrl_c_mux[] = {
3383         RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3384 };
3385 /* - SCIF5 ------------------------------------------------------------------ */
3386 static const unsigned int scif5_data_pins[] = {
3387         /* RX, TX */
3388         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3389 };
3390 static const unsigned int scif5_data_mux[] = {
3391         RX5_MARK, TX5_MARK,
3392 };
3393 static const unsigned int scif5_clk_pins[] = {
3394         /* SCK */
3395         RCAR_GP_PIN(6, 21),
3396 };
3397 static const unsigned int scif5_clk_mux[] = {
3398         SCK5_MARK,
3399 };
3400
3401 /* - SCIF Clock ------------------------------------------------------------- */
3402 static const unsigned int scif_clk_a_pins[] = {
3403         /* SCIF_CLK */
3404         RCAR_GP_PIN(6, 23),
3405 };
3406 static const unsigned int scif_clk_a_mux[] = {
3407         SCIF_CLK_A_MARK,
3408 };
3409 static const unsigned int scif_clk_b_pins[] = {
3410         /* SCIF_CLK */
3411         RCAR_GP_PIN(5, 9),
3412 };
3413 static const unsigned int scif_clk_b_mux[] = {
3414         SCIF_CLK_B_MARK,
3415 };
3416
3417 /* - SDHI0 ------------------------------------------------------------------ */
3418 static const unsigned int sdhi0_data1_pins[] = {
3419         /* D0 */
3420         RCAR_GP_PIN(3, 2),
3421 };
3422 static const unsigned int sdhi0_data1_mux[] = {
3423         SD0_DAT0_MARK,
3424 };
3425 static const unsigned int sdhi0_data4_pins[] = {
3426         /* D[0:3] */
3427         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3428         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3429 };
3430 static const unsigned int sdhi0_data4_mux[] = {
3431         SD0_DAT0_MARK, SD0_DAT1_MARK,
3432         SD0_DAT2_MARK, SD0_DAT3_MARK,
3433 };
3434 static const unsigned int sdhi0_ctrl_pins[] = {
3435         /* CLK, CMD */
3436         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3437 };
3438 static const unsigned int sdhi0_ctrl_mux[] = {
3439         SD0_CLK_MARK, SD0_CMD_MARK,
3440 };
3441 static const unsigned int sdhi0_cd_pins[] = {
3442         /* CD */
3443         RCAR_GP_PIN(3, 12),
3444 };
3445 static const unsigned int sdhi0_cd_mux[] = {
3446         SD0_CD_MARK,
3447 };
3448 static const unsigned int sdhi0_wp_pins[] = {
3449         /* WP */
3450         RCAR_GP_PIN(3, 13),
3451 };
3452 static const unsigned int sdhi0_wp_mux[] = {
3453         SD0_WP_MARK,
3454 };
3455 /* - SDHI1 ------------------------------------------------------------------ */
3456 static const unsigned int sdhi1_data1_pins[] = {
3457         /* D0 */
3458         RCAR_GP_PIN(3, 8),
3459 };
3460 static const unsigned int sdhi1_data1_mux[] = {
3461         SD1_DAT0_MARK,
3462 };
3463 static const unsigned int sdhi1_data4_pins[] = {
3464         /* D[0:3] */
3465         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3466         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3467 };
3468 static const unsigned int sdhi1_data4_mux[] = {
3469         SD1_DAT0_MARK, SD1_DAT1_MARK,
3470         SD1_DAT2_MARK, SD1_DAT3_MARK,
3471 };
3472 static const unsigned int sdhi1_ctrl_pins[] = {
3473         /* CLK, CMD */
3474         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3475 };
3476 static const unsigned int sdhi1_ctrl_mux[] = {
3477         SD1_CLK_MARK, SD1_CMD_MARK,
3478 };
3479 static const unsigned int sdhi1_cd_pins[] = {
3480         /* CD */
3481         RCAR_GP_PIN(3, 14),
3482 };
3483 static const unsigned int sdhi1_cd_mux[] = {
3484         SD1_CD_MARK,
3485 };
3486 static const unsigned int sdhi1_wp_pins[] = {
3487         /* WP */
3488         RCAR_GP_PIN(3, 15),
3489 };
3490 static const unsigned int sdhi1_wp_mux[] = {
3491         SD1_WP_MARK,
3492 };
3493 /* - SDHI2 ------------------------------------------------------------------ */
3494 static const unsigned int sdhi2_data1_pins[] = {
3495         /* D0 */
3496         RCAR_GP_PIN(4, 2),
3497 };
3498 static const unsigned int sdhi2_data1_mux[] = {
3499         SD2_DAT0_MARK,
3500 };
3501 static const unsigned int sdhi2_data4_pins[] = {
3502         /* D[0:3] */
3503         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3504         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3505 };
3506 static const unsigned int sdhi2_data4_mux[] = {
3507         SD2_DAT0_MARK, SD2_DAT1_MARK,
3508         SD2_DAT2_MARK, SD2_DAT3_MARK,
3509 };
3510 static const unsigned int sdhi2_data8_pins[] = {
3511         /* D[0:7] */
3512         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3513         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3514         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3515         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3516 };
3517 static const unsigned int sdhi2_data8_mux[] = {
3518         SD2_DAT0_MARK, SD2_DAT1_MARK,
3519         SD2_DAT2_MARK, SD2_DAT3_MARK,
3520         SD2_DAT4_MARK, SD2_DAT5_MARK,
3521         SD2_DAT6_MARK, SD2_DAT7_MARK,
3522 };
3523 static const unsigned int sdhi2_ctrl_pins[] = {
3524         /* CLK, CMD */
3525         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3526 };
3527 static const unsigned int sdhi2_ctrl_mux[] = {
3528         SD2_CLK_MARK, SD2_CMD_MARK,
3529 };
3530 static const unsigned int sdhi2_cd_a_pins[] = {
3531         /* CD */
3532         RCAR_GP_PIN(4, 13),
3533 };
3534 static const unsigned int sdhi2_cd_a_mux[] = {
3535         SD2_CD_A_MARK,
3536 };
3537 static const unsigned int sdhi2_cd_b_pins[] = {
3538         /* CD */
3539         RCAR_GP_PIN(5, 10),
3540 };
3541 static const unsigned int sdhi2_cd_b_mux[] = {
3542         SD2_CD_B_MARK,
3543 };
3544 static const unsigned int sdhi2_wp_a_pins[] = {
3545         /* WP */
3546         RCAR_GP_PIN(4, 14),
3547 };
3548 static const unsigned int sdhi2_wp_a_mux[] = {
3549         SD2_WP_A_MARK,
3550 };
3551 static const unsigned int sdhi2_wp_b_pins[] = {
3552         /* WP */
3553         RCAR_GP_PIN(5, 11),
3554 };
3555 static const unsigned int sdhi2_wp_b_mux[] = {
3556         SD2_WP_B_MARK,
3557 };
3558 static const unsigned int sdhi2_ds_pins[] = {
3559         /* DS */
3560         RCAR_GP_PIN(4, 6),
3561 };
3562 static const unsigned int sdhi2_ds_mux[] = {
3563         SD2_DS_MARK,
3564 };
3565 /* - SDHI3 ------------------------------------------------------------------ */
3566 static const unsigned int sdhi3_data1_pins[] = {
3567         /* D0 */
3568         RCAR_GP_PIN(4, 9),
3569 };
3570 static const unsigned int sdhi3_data1_mux[] = {
3571         SD3_DAT0_MARK,
3572 };
3573 static const unsigned int sdhi3_data4_pins[] = {
3574         /* D[0:3] */
3575         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3576         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3577 };
3578 static const unsigned int sdhi3_data4_mux[] = {
3579         SD3_DAT0_MARK, SD3_DAT1_MARK,
3580         SD3_DAT2_MARK, SD3_DAT3_MARK,
3581 };
3582 static const unsigned int sdhi3_data8_pins[] = {
3583         /* D[0:7] */
3584         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3585         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3586         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3587         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3588 };
3589 static const unsigned int sdhi3_data8_mux[] = {
3590         SD3_DAT0_MARK, SD3_DAT1_MARK,
3591         SD3_DAT2_MARK, SD3_DAT3_MARK,
3592         SD3_DAT4_MARK, SD3_DAT5_MARK,
3593         SD3_DAT6_MARK, SD3_DAT7_MARK,
3594 };
3595 static const unsigned int sdhi3_ctrl_pins[] = {
3596         /* CLK, CMD */
3597         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3598 };
3599 static const unsigned int sdhi3_ctrl_mux[] = {
3600         SD3_CLK_MARK, SD3_CMD_MARK,
3601 };
3602 static const unsigned int sdhi3_cd_pins[] = {
3603         /* CD */
3604         RCAR_GP_PIN(4, 15),
3605 };
3606 static const unsigned int sdhi3_cd_mux[] = {
3607         SD3_CD_MARK,
3608 };
3609 static const unsigned int sdhi3_wp_pins[] = {
3610         /* WP */
3611         RCAR_GP_PIN(4, 16),
3612 };
3613 static const unsigned int sdhi3_wp_mux[] = {
3614         SD3_WP_MARK,
3615 };
3616 static const unsigned int sdhi3_ds_pins[] = {
3617         /* DS */
3618         RCAR_GP_PIN(4, 17),
3619 };
3620 static const unsigned int sdhi3_ds_mux[] = {
3621         SD3_DS_MARK,
3622 };
3623
3624 /* - SSI -------------------------------------------------------------------- */
3625 static const unsigned int ssi0_data_pins[] = {
3626         /* SDATA */
3627         RCAR_GP_PIN(6, 2),
3628 };
3629 static const unsigned int ssi0_data_mux[] = {
3630         SSI_SDATA0_MARK,
3631 };
3632 static const unsigned int ssi01239_ctrl_pins[] = {
3633         /* SCK, WS */
3634         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3635 };
3636 static const unsigned int ssi01239_ctrl_mux[] = {
3637         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3638 };
3639 static const unsigned int ssi1_data_a_pins[] = {
3640         /* SDATA */
3641         RCAR_GP_PIN(6, 3),
3642 };
3643 static const unsigned int ssi1_data_a_mux[] = {
3644         SSI_SDATA1_A_MARK,
3645 };
3646 static const unsigned int ssi1_data_b_pins[] = {
3647         /* SDATA */
3648         RCAR_GP_PIN(5, 12),
3649 };
3650 static const unsigned int ssi1_data_b_mux[] = {
3651         SSI_SDATA1_B_MARK,
3652 };
3653 static const unsigned int ssi1_ctrl_a_pins[] = {
3654         /* SCK, WS */
3655         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3656 };
3657 static const unsigned int ssi1_ctrl_a_mux[] = {
3658         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3659 };
3660 static const unsigned int ssi1_ctrl_b_pins[] = {
3661         /* SCK, WS */
3662         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3663 };
3664 static const unsigned int ssi1_ctrl_b_mux[] = {
3665         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3666 };
3667 static const unsigned int ssi2_data_a_pins[] = {
3668         /* SDATA */
3669         RCAR_GP_PIN(6, 4),
3670 };
3671 static const unsigned int ssi2_data_a_mux[] = {
3672         SSI_SDATA2_A_MARK,
3673 };
3674 static const unsigned int ssi2_data_b_pins[] = {
3675         /* SDATA */
3676         RCAR_GP_PIN(5, 13),
3677 };
3678 static const unsigned int ssi2_data_b_mux[] = {
3679         SSI_SDATA2_B_MARK,
3680 };
3681 static const unsigned int ssi2_ctrl_a_pins[] = {
3682         /* SCK, WS */
3683         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3684 };
3685 static const unsigned int ssi2_ctrl_a_mux[] = {
3686         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3687 };
3688 static const unsigned int ssi2_ctrl_b_pins[] = {
3689         /* SCK, WS */
3690         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3691 };
3692 static const unsigned int ssi2_ctrl_b_mux[] = {
3693         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3694 };
3695 static const unsigned int ssi3_data_pins[] = {
3696         /* SDATA */
3697         RCAR_GP_PIN(6, 7),
3698 };
3699 static const unsigned int ssi3_data_mux[] = {
3700         SSI_SDATA3_MARK,
3701 };
3702 static const unsigned int ssi349_ctrl_pins[] = {
3703         /* SCK, WS */
3704         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3705 };
3706 static const unsigned int ssi349_ctrl_mux[] = {
3707         SSI_SCK349_MARK, SSI_WS349_MARK,
3708 };
3709 static const unsigned int ssi4_data_pins[] = {
3710         /* SDATA */
3711         RCAR_GP_PIN(6, 10),
3712 };
3713 static const unsigned int ssi4_data_mux[] = {
3714         SSI_SDATA4_MARK,
3715 };
3716 static const unsigned int ssi4_ctrl_pins[] = {
3717         /* SCK, WS */
3718         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3719 };
3720 static const unsigned int ssi4_ctrl_mux[] = {
3721         SSI_SCK4_MARK, SSI_WS4_MARK,
3722 };
3723 static const unsigned int ssi5_data_pins[] = {
3724         /* SDATA */
3725         RCAR_GP_PIN(6, 13),
3726 };
3727 static const unsigned int ssi5_data_mux[] = {
3728         SSI_SDATA5_MARK,
3729 };
3730 static const unsigned int ssi5_ctrl_pins[] = {
3731         /* SCK, WS */
3732         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3733 };
3734 static const unsigned int ssi5_ctrl_mux[] = {
3735         SSI_SCK5_MARK, SSI_WS5_MARK,
3736 };
3737 static const unsigned int ssi6_data_pins[] = {
3738         /* SDATA */
3739         RCAR_GP_PIN(6, 16),
3740 };
3741 static const unsigned int ssi6_data_mux[] = {
3742         SSI_SDATA6_MARK,
3743 };
3744 static const unsigned int ssi6_ctrl_pins[] = {
3745         /* SCK, WS */
3746         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3747 };
3748 static const unsigned int ssi6_ctrl_mux[] = {
3749         SSI_SCK6_MARK, SSI_WS6_MARK,
3750 };
3751 static const unsigned int ssi7_data_pins[] = {
3752         /* SDATA */
3753         RCAR_GP_PIN(6, 19),
3754 };
3755 static const unsigned int ssi7_data_mux[] = {
3756         SSI_SDATA7_MARK,
3757 };
3758 static const unsigned int ssi78_ctrl_pins[] = {
3759         /* SCK, WS */
3760         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3761 };
3762 static const unsigned int ssi78_ctrl_mux[] = {
3763         SSI_SCK78_MARK, SSI_WS78_MARK,
3764 };
3765 static const unsigned int ssi8_data_pins[] = {
3766         /* SDATA */
3767         RCAR_GP_PIN(6, 20),
3768 };
3769 static const unsigned int ssi8_data_mux[] = {
3770         SSI_SDATA8_MARK,
3771 };
3772 static const unsigned int ssi9_data_a_pins[] = {
3773         /* SDATA */
3774         RCAR_GP_PIN(6, 21),
3775 };
3776 static const unsigned int ssi9_data_a_mux[] = {
3777         SSI_SDATA9_A_MARK,
3778 };
3779 static const unsigned int ssi9_data_b_pins[] = {
3780         /* SDATA */
3781         RCAR_GP_PIN(5, 14),
3782 };
3783 static const unsigned int ssi9_data_b_mux[] = {
3784         SSI_SDATA9_B_MARK,
3785 };
3786 static const unsigned int ssi9_ctrl_a_pins[] = {
3787         /* SCK, WS */
3788         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3789 };
3790 static const unsigned int ssi9_ctrl_a_mux[] = {
3791         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3792 };
3793 static const unsigned int ssi9_ctrl_b_pins[] = {
3794         /* SCK, WS */
3795         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3796 };
3797 static const unsigned int ssi9_ctrl_b_mux[] = {
3798         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3799 };
3800
3801 /* - TMU -------------------------------------------------------------------- */
3802 static const unsigned int tmu_tclk1_a_pins[] = {
3803         /* TCLK */
3804         RCAR_GP_PIN(6, 23),
3805 };
3806 static const unsigned int tmu_tclk1_a_mux[] = {
3807         TCLK1_A_MARK,
3808 };
3809 static const unsigned int tmu_tclk1_b_pins[] = {
3810         /* TCLK */
3811         RCAR_GP_PIN(5, 19),
3812 };
3813 static const unsigned int tmu_tclk1_b_mux[] = {
3814         TCLK1_B_MARK,
3815 };
3816 static const unsigned int tmu_tclk2_a_pins[] = {
3817         /* TCLK */
3818         RCAR_GP_PIN(6, 19),
3819 };
3820 static const unsigned int tmu_tclk2_a_mux[] = {
3821         TCLK2_A_MARK,
3822 };
3823 static const unsigned int tmu_tclk2_b_pins[] = {
3824         /* TCLK */
3825         RCAR_GP_PIN(6, 28),
3826 };
3827 static const unsigned int tmu_tclk2_b_mux[] = {
3828         TCLK2_B_MARK,
3829 };
3830
3831 /* - USB0 ------------------------------------------------------------------- */
3832 static const unsigned int usb0_pins[] = {
3833         /* PWEN, OVC */
3834         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3835 };
3836 static const unsigned int usb0_mux[] = {
3837         USB0_PWEN_MARK, USB0_OVC_MARK,
3838 };
3839 /* - USB1 ------------------------------------------------------------------- */
3840 static const unsigned int usb1_pins[] = {
3841         /* PWEN, OVC */
3842         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3843 };
3844 static const unsigned int usb1_mux[] = {
3845         USB1_PWEN_MARK, USB1_OVC_MARK,
3846 };
3847 /* - USB2 ------------------------------------------------------------------- */
3848 static const unsigned int usb2_pins[] = {
3849         /* PWEN, OVC */
3850         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3851 };
3852 static const unsigned int usb2_mux[] = {
3853         USB2_PWEN_MARK, USB2_OVC_MARK,
3854 };
3855
3856 /* - USB30 ------------------------------------------------------------------ */
3857 static const unsigned int usb30_pins[] = {
3858         /* PWEN, OVC */
3859         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3860 };
3861 static const unsigned int usb30_mux[] = {
3862         USB30_PWEN_MARK, USB30_OVC_MARK,
3863 };
3864 /* - USB31 ------------------------------------------------------------------ */
3865 static const unsigned int usb31_pins[] = {
3866         /* PWEN, OVC */
3867         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3868 };
3869 static const unsigned int usb31_mux[] = {
3870         USB31_PWEN_MARK, USB31_OVC_MARK,
3871 };
3872
3873 static const struct sh_pfc_pin_group pinmux_groups[] = {
3874         SH_PFC_PIN_GROUP(audio_clk_a_a),
3875         SH_PFC_PIN_GROUP(audio_clk_a_b),
3876         SH_PFC_PIN_GROUP(audio_clk_a_c),
3877         SH_PFC_PIN_GROUP(audio_clk_b_a),
3878         SH_PFC_PIN_GROUP(audio_clk_b_b),
3879         SH_PFC_PIN_GROUP(audio_clk_c_a),
3880         SH_PFC_PIN_GROUP(audio_clk_c_b),
3881         SH_PFC_PIN_GROUP(audio_clkout_a),
3882         SH_PFC_PIN_GROUP(audio_clkout_b),
3883         SH_PFC_PIN_GROUP(audio_clkout_c),
3884         SH_PFC_PIN_GROUP(audio_clkout_d),
3885         SH_PFC_PIN_GROUP(audio_clkout1_a),
3886         SH_PFC_PIN_GROUP(audio_clkout1_b),
3887         SH_PFC_PIN_GROUP(audio_clkout2_a),
3888         SH_PFC_PIN_GROUP(audio_clkout2_b),
3889         SH_PFC_PIN_GROUP(audio_clkout3_a),
3890         SH_PFC_PIN_GROUP(audio_clkout3_b),
3891         SH_PFC_PIN_GROUP(avb_link),
3892         SH_PFC_PIN_GROUP(avb_magic),
3893         SH_PFC_PIN_GROUP(avb_phy_int),
3894         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
3895         SH_PFC_PIN_GROUP(avb_mdio),
3896         SH_PFC_PIN_GROUP(avb_mii),
3897         SH_PFC_PIN_GROUP(avb_avtp_pps),
3898         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3899         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3900         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3901         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3902         SH_PFC_PIN_GROUP(can0_data_a),
3903         SH_PFC_PIN_GROUP(can0_data_b),
3904         SH_PFC_PIN_GROUP(can1_data),
3905         SH_PFC_PIN_GROUP(can_clk),
3906         SH_PFC_PIN_GROUP(canfd0_data_a),
3907         SH_PFC_PIN_GROUP(canfd0_data_b),
3908         SH_PFC_PIN_GROUP(canfd1_data),
3909         SH_PFC_PIN_GROUP(drif0_ctrl_a),
3910         SH_PFC_PIN_GROUP(drif0_data0_a),
3911         SH_PFC_PIN_GROUP(drif0_data1_a),
3912         SH_PFC_PIN_GROUP(drif0_ctrl_b),
3913         SH_PFC_PIN_GROUP(drif0_data0_b),
3914         SH_PFC_PIN_GROUP(drif0_data1_b),
3915         SH_PFC_PIN_GROUP(drif0_ctrl_c),
3916         SH_PFC_PIN_GROUP(drif0_data0_c),
3917         SH_PFC_PIN_GROUP(drif0_data1_c),
3918         SH_PFC_PIN_GROUP(drif1_ctrl_a),
3919         SH_PFC_PIN_GROUP(drif1_data0_a),
3920         SH_PFC_PIN_GROUP(drif1_data1_a),
3921         SH_PFC_PIN_GROUP(drif1_ctrl_b),
3922         SH_PFC_PIN_GROUP(drif1_data0_b),
3923         SH_PFC_PIN_GROUP(drif1_data1_b),
3924         SH_PFC_PIN_GROUP(drif1_ctrl_c),
3925         SH_PFC_PIN_GROUP(drif1_data0_c),
3926         SH_PFC_PIN_GROUP(drif1_data1_c),
3927         SH_PFC_PIN_GROUP(drif2_ctrl_a),
3928         SH_PFC_PIN_GROUP(drif2_data0_a),
3929         SH_PFC_PIN_GROUP(drif2_data1_a),
3930         SH_PFC_PIN_GROUP(drif2_ctrl_b),
3931         SH_PFC_PIN_GROUP(drif2_data0_b),
3932         SH_PFC_PIN_GROUP(drif2_data1_b),
3933         SH_PFC_PIN_GROUP(drif3_ctrl_a),
3934         SH_PFC_PIN_GROUP(drif3_data0_a),
3935         SH_PFC_PIN_GROUP(drif3_data1_a),
3936         SH_PFC_PIN_GROUP(drif3_ctrl_b),
3937         SH_PFC_PIN_GROUP(drif3_data0_b),
3938         SH_PFC_PIN_GROUP(drif3_data1_b),
3939         SH_PFC_PIN_GROUP(du_rgb666),
3940         SH_PFC_PIN_GROUP(du_rgb888),
3941         SH_PFC_PIN_GROUP(du_clk_out_0),
3942         SH_PFC_PIN_GROUP(du_clk_out_1),
3943         SH_PFC_PIN_GROUP(du_sync),
3944         SH_PFC_PIN_GROUP(du_oddf),
3945         SH_PFC_PIN_GROUP(du_cde),
3946         SH_PFC_PIN_GROUP(du_disp),
3947         SH_PFC_PIN_GROUP(hdmi0_cec),
3948         SH_PFC_PIN_GROUP(hdmi1_cec),
3949         SH_PFC_PIN_GROUP(hscif0_data),
3950         SH_PFC_PIN_GROUP(hscif0_clk),
3951         SH_PFC_PIN_GROUP(hscif0_ctrl),
3952         SH_PFC_PIN_GROUP(hscif1_data_a),
3953         SH_PFC_PIN_GROUP(hscif1_clk_a),
3954         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3955         SH_PFC_PIN_GROUP(hscif1_data_b),
3956         SH_PFC_PIN_GROUP(hscif1_clk_b),
3957         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3958         SH_PFC_PIN_GROUP(hscif2_data_a),
3959         SH_PFC_PIN_GROUP(hscif2_clk_a),
3960         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3961         SH_PFC_PIN_GROUP(hscif2_data_b),
3962         SH_PFC_PIN_GROUP(hscif2_clk_b),
3963         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3964         SH_PFC_PIN_GROUP(hscif3_data_a),
3965         SH_PFC_PIN_GROUP(hscif3_clk),
3966         SH_PFC_PIN_GROUP(hscif3_ctrl),
3967         SH_PFC_PIN_GROUP(hscif3_data_b),
3968         SH_PFC_PIN_GROUP(hscif3_data_c),
3969         SH_PFC_PIN_GROUP(hscif3_data_d),
3970         SH_PFC_PIN_GROUP(hscif4_data_a),
3971         SH_PFC_PIN_GROUP(hscif4_clk),
3972         SH_PFC_PIN_GROUP(hscif4_ctrl),
3973         SH_PFC_PIN_GROUP(hscif4_data_b),
3974         SH_PFC_PIN_GROUP(i2c0),
3975         SH_PFC_PIN_GROUP(i2c1_a),
3976         SH_PFC_PIN_GROUP(i2c1_b),
3977         SH_PFC_PIN_GROUP(i2c2_a),
3978         SH_PFC_PIN_GROUP(i2c2_b),
3979         SH_PFC_PIN_GROUP(i2c3),
3980         SH_PFC_PIN_GROUP(i2c5),
3981         SH_PFC_PIN_GROUP(i2c6_a),
3982         SH_PFC_PIN_GROUP(i2c6_b),
3983         SH_PFC_PIN_GROUP(i2c6_c),
3984         SH_PFC_PIN_GROUP(intc_ex_irq0),
3985         SH_PFC_PIN_GROUP(intc_ex_irq1),
3986         SH_PFC_PIN_GROUP(intc_ex_irq2),
3987         SH_PFC_PIN_GROUP(intc_ex_irq3),
3988         SH_PFC_PIN_GROUP(intc_ex_irq4),
3989         SH_PFC_PIN_GROUP(intc_ex_irq5),
3990         SH_PFC_PIN_GROUP(msiof0_clk),
3991         SH_PFC_PIN_GROUP(msiof0_sync),
3992         SH_PFC_PIN_GROUP(msiof0_ss1),
3993         SH_PFC_PIN_GROUP(msiof0_ss2),
3994         SH_PFC_PIN_GROUP(msiof0_txd),
3995         SH_PFC_PIN_GROUP(msiof0_rxd),
3996         SH_PFC_PIN_GROUP(msiof1_clk_a),
3997         SH_PFC_PIN_GROUP(msiof1_sync_a),
3998         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3999         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4000         SH_PFC_PIN_GROUP(msiof1_txd_a),
4001         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4002         SH_PFC_PIN_GROUP(msiof1_clk_b),
4003         SH_PFC_PIN_GROUP(msiof1_sync_b),
4004         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4005         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4006         SH_PFC_PIN_GROUP(msiof1_txd_b),
4007         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4008         SH_PFC_PIN_GROUP(msiof1_clk_c),
4009         SH_PFC_PIN_GROUP(msiof1_sync_c),
4010         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4011         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4012         SH_PFC_PIN_GROUP(msiof1_txd_c),
4013         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4014         SH_PFC_PIN_GROUP(msiof1_clk_d),
4015         SH_PFC_PIN_GROUP(msiof1_sync_d),
4016         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4017         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4018         SH_PFC_PIN_GROUP(msiof1_txd_d),
4019         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4020         SH_PFC_PIN_GROUP(msiof1_clk_e),
4021         SH_PFC_PIN_GROUP(msiof1_sync_e),
4022         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4023         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4024         SH_PFC_PIN_GROUP(msiof1_txd_e),
4025         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4026         SH_PFC_PIN_GROUP(msiof1_clk_f),
4027         SH_PFC_PIN_GROUP(msiof1_sync_f),
4028         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4029         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4030         SH_PFC_PIN_GROUP(msiof1_txd_f),
4031         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4032         SH_PFC_PIN_GROUP(msiof1_clk_g),
4033         SH_PFC_PIN_GROUP(msiof1_sync_g),
4034         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4035         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4036         SH_PFC_PIN_GROUP(msiof1_txd_g),
4037         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4038         SH_PFC_PIN_GROUP(msiof2_clk_a),
4039         SH_PFC_PIN_GROUP(msiof2_sync_a),
4040         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4041         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4042         SH_PFC_PIN_GROUP(msiof2_txd_a),
4043         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4044         SH_PFC_PIN_GROUP(msiof2_clk_b),
4045         SH_PFC_PIN_GROUP(msiof2_sync_b),
4046         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4047         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4048         SH_PFC_PIN_GROUP(msiof2_txd_b),
4049         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4050         SH_PFC_PIN_GROUP(msiof2_clk_c),
4051         SH_PFC_PIN_GROUP(msiof2_sync_c),
4052         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4053         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4054         SH_PFC_PIN_GROUP(msiof2_txd_c),
4055         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4056         SH_PFC_PIN_GROUP(msiof2_clk_d),
4057         SH_PFC_PIN_GROUP(msiof2_sync_d),
4058         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4059         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4060         SH_PFC_PIN_GROUP(msiof2_txd_d),
4061         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4062         SH_PFC_PIN_GROUP(msiof3_clk_a),
4063         SH_PFC_PIN_GROUP(msiof3_sync_a),
4064         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4065         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4066         SH_PFC_PIN_GROUP(msiof3_txd_a),
4067         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4068         SH_PFC_PIN_GROUP(msiof3_clk_b),
4069         SH_PFC_PIN_GROUP(msiof3_sync_b),
4070         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4071         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4072         SH_PFC_PIN_GROUP(msiof3_txd_b),
4073         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4074         SH_PFC_PIN_GROUP(msiof3_clk_c),
4075         SH_PFC_PIN_GROUP(msiof3_sync_c),
4076         SH_PFC_PIN_GROUP(msiof3_txd_c),
4077         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4078         SH_PFC_PIN_GROUP(msiof3_clk_d),
4079         SH_PFC_PIN_GROUP(msiof3_sync_d),
4080         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4081         SH_PFC_PIN_GROUP(msiof3_txd_d),
4082         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4083         SH_PFC_PIN_GROUP(pwm0),
4084         SH_PFC_PIN_GROUP(pwm1_a),
4085         SH_PFC_PIN_GROUP(pwm1_b),
4086         SH_PFC_PIN_GROUP(pwm2_a),
4087         SH_PFC_PIN_GROUP(pwm2_b),
4088         SH_PFC_PIN_GROUP(pwm3_a),
4089         SH_PFC_PIN_GROUP(pwm3_b),
4090         SH_PFC_PIN_GROUP(pwm4_a),
4091         SH_PFC_PIN_GROUP(pwm4_b),
4092         SH_PFC_PIN_GROUP(pwm5_a),
4093         SH_PFC_PIN_GROUP(pwm5_b),
4094         SH_PFC_PIN_GROUP(pwm6_a),
4095         SH_PFC_PIN_GROUP(pwm6_b),
4096         SH_PFC_PIN_GROUP(qspi0_ctrl),
4097         SH_PFC_PIN_GROUP(qspi0_data2),
4098         SH_PFC_PIN_GROUP(qspi0_data4),
4099         SH_PFC_PIN_GROUP(qspi1_ctrl),
4100         SH_PFC_PIN_GROUP(qspi1_data2),
4101         SH_PFC_PIN_GROUP(qspi1_data4),
4102         SH_PFC_PIN_GROUP(sata0_devslp_a),
4103         SH_PFC_PIN_GROUP(sata0_devslp_b),
4104         SH_PFC_PIN_GROUP(scif0_data),
4105         SH_PFC_PIN_GROUP(scif0_clk),
4106         SH_PFC_PIN_GROUP(scif0_ctrl),
4107         SH_PFC_PIN_GROUP(scif1_data_a),
4108         SH_PFC_PIN_GROUP(scif1_clk),
4109         SH_PFC_PIN_GROUP(scif1_ctrl),
4110         SH_PFC_PIN_GROUP(scif1_data_b),
4111         SH_PFC_PIN_GROUP(scif2_data_a),
4112         SH_PFC_PIN_GROUP(scif2_clk),
4113         SH_PFC_PIN_GROUP(scif2_data_b),
4114         SH_PFC_PIN_GROUP(scif3_data_a),
4115         SH_PFC_PIN_GROUP(scif3_clk),
4116         SH_PFC_PIN_GROUP(scif3_ctrl),
4117         SH_PFC_PIN_GROUP(scif3_data_b),
4118         SH_PFC_PIN_GROUP(scif4_data_a),
4119         SH_PFC_PIN_GROUP(scif4_clk_a),
4120         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4121         SH_PFC_PIN_GROUP(scif4_data_b),
4122         SH_PFC_PIN_GROUP(scif4_clk_b),
4123         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4124         SH_PFC_PIN_GROUP(scif4_data_c),
4125         SH_PFC_PIN_GROUP(scif4_clk_c),
4126         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4127         SH_PFC_PIN_GROUP(scif5_data),
4128         SH_PFC_PIN_GROUP(scif5_clk),
4129         SH_PFC_PIN_GROUP(scif_clk_a),
4130         SH_PFC_PIN_GROUP(scif_clk_b),
4131         SH_PFC_PIN_GROUP(sdhi0_data1),
4132         SH_PFC_PIN_GROUP(sdhi0_data4),
4133         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4134         SH_PFC_PIN_GROUP(sdhi0_cd),
4135         SH_PFC_PIN_GROUP(sdhi0_wp),
4136         SH_PFC_PIN_GROUP(sdhi1_data1),
4137         SH_PFC_PIN_GROUP(sdhi1_data4),
4138         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4139         SH_PFC_PIN_GROUP(sdhi1_cd),
4140         SH_PFC_PIN_GROUP(sdhi1_wp),
4141         SH_PFC_PIN_GROUP(sdhi2_data1),
4142         SH_PFC_PIN_GROUP(sdhi2_data4),
4143         SH_PFC_PIN_GROUP(sdhi2_data8),
4144         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4145         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4146         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4147         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4148         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4149         SH_PFC_PIN_GROUP(sdhi2_ds),
4150         SH_PFC_PIN_GROUP(sdhi3_data1),
4151         SH_PFC_PIN_GROUP(sdhi3_data4),
4152         SH_PFC_PIN_GROUP(sdhi3_data8),
4153         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4154         SH_PFC_PIN_GROUP(sdhi3_cd),
4155         SH_PFC_PIN_GROUP(sdhi3_wp),
4156         SH_PFC_PIN_GROUP(sdhi3_ds),
4157         SH_PFC_PIN_GROUP(ssi0_data),
4158         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4159         SH_PFC_PIN_GROUP(ssi1_data_a),
4160         SH_PFC_PIN_GROUP(ssi1_data_b),
4161         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4162         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4163         SH_PFC_PIN_GROUP(ssi2_data_a),
4164         SH_PFC_PIN_GROUP(ssi2_data_b),
4165         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4166         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4167         SH_PFC_PIN_GROUP(ssi3_data),
4168         SH_PFC_PIN_GROUP(ssi349_ctrl),
4169         SH_PFC_PIN_GROUP(ssi4_data),
4170         SH_PFC_PIN_GROUP(ssi4_ctrl),
4171         SH_PFC_PIN_GROUP(ssi5_data),
4172         SH_PFC_PIN_GROUP(ssi5_ctrl),
4173         SH_PFC_PIN_GROUP(ssi6_data),
4174         SH_PFC_PIN_GROUP(ssi6_ctrl),
4175         SH_PFC_PIN_GROUP(ssi7_data),
4176         SH_PFC_PIN_GROUP(ssi78_ctrl),
4177         SH_PFC_PIN_GROUP(ssi8_data),
4178         SH_PFC_PIN_GROUP(ssi9_data_a),
4179         SH_PFC_PIN_GROUP(ssi9_data_b),
4180         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4181         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4182         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4183         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4184         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4185         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4186         SH_PFC_PIN_GROUP(usb0),
4187         SH_PFC_PIN_GROUP(usb1),
4188         SH_PFC_PIN_GROUP(usb2),
4189         SH_PFC_PIN_GROUP(usb30),
4190         SH_PFC_PIN_GROUP(usb31),
4191 };
4192
4193 static const char * const audio_clk_groups[] = {
4194         "audio_clk_a_a",
4195         "audio_clk_a_b",
4196         "audio_clk_a_c",
4197         "audio_clk_b_a",
4198         "audio_clk_b_b",
4199         "audio_clk_c_a",
4200         "audio_clk_c_b",
4201         "audio_clkout_a",
4202         "audio_clkout_b",
4203         "audio_clkout_c",
4204         "audio_clkout_d",
4205         "audio_clkout1_a",
4206         "audio_clkout1_b",
4207         "audio_clkout2_a",
4208         "audio_clkout2_b",
4209         "audio_clkout3_a",
4210         "audio_clkout3_b",
4211 };
4212
4213 static const char * const avb_groups[] = {
4214         "avb_link",
4215         "avb_magic",
4216         "avb_phy_int",
4217         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4218         "avb_mdio",
4219         "avb_mii",
4220         "avb_avtp_pps",
4221         "avb_avtp_match_a",
4222         "avb_avtp_capture_a",
4223         "avb_avtp_match_b",
4224         "avb_avtp_capture_b",
4225 };
4226
4227 static const char * const can0_groups[] = {
4228         "can0_data_a",
4229         "can0_data_b",
4230 };
4231
4232 static const char * const can1_groups[] = {
4233         "can1_data",
4234 };
4235
4236 static const char * const can_clk_groups[] = {
4237         "can_clk",
4238 };
4239
4240 static const char * const canfd0_groups[] = {
4241         "canfd0_data_a",
4242         "canfd0_data_b",
4243 };
4244
4245 static const char * const canfd1_groups[] = {
4246         "canfd1_data",
4247 };
4248
4249 static const char * const drif0_groups[] = {
4250         "drif0_ctrl_a",
4251         "drif0_data0_a",
4252         "drif0_data1_a",
4253         "drif0_ctrl_b",
4254         "drif0_data0_b",
4255         "drif0_data1_b",
4256         "drif0_ctrl_c",
4257         "drif0_data0_c",
4258         "drif0_data1_c",
4259 };
4260
4261 static const char * const drif1_groups[] = {
4262         "drif1_ctrl_a",
4263         "drif1_data0_a",
4264         "drif1_data1_a",
4265         "drif1_ctrl_b",
4266         "drif1_data0_b",
4267         "drif1_data1_b",
4268         "drif1_ctrl_c",
4269         "drif1_data0_c",
4270         "drif1_data1_c",
4271 };
4272
4273 static const char * const drif2_groups[] = {
4274         "drif2_ctrl_a",
4275         "drif2_data0_a",
4276         "drif2_data1_a",
4277         "drif2_ctrl_b",
4278         "drif2_data0_b",
4279         "drif2_data1_b",
4280 };
4281
4282 static const char * const drif3_groups[] = {
4283         "drif3_ctrl_a",
4284         "drif3_data0_a",
4285         "drif3_data1_a",
4286         "drif3_ctrl_b",
4287         "drif3_data0_b",
4288         "drif3_data1_b",
4289 };
4290
4291 static const char * const du_groups[] = {
4292         "du_rgb666",
4293         "du_rgb888",
4294         "du_clk_out_0",
4295         "du_clk_out_1",
4296         "du_sync",
4297         "du_oddf",
4298         "du_cde",
4299         "du_disp",
4300 };
4301
4302 static const char * const hdmi0_groups[] = {
4303         "hdmi0_cec",
4304 };
4305
4306 static const char * const hdmi1_groups[] = {
4307         "hdmi1_cec",
4308 };
4309
4310 static const char * const hscif0_groups[] = {
4311         "hscif0_data",
4312         "hscif0_clk",
4313         "hscif0_ctrl",
4314 };
4315
4316 static const char * const hscif1_groups[] = {
4317         "hscif1_data_a",
4318         "hscif1_clk_a",
4319         "hscif1_ctrl_a",
4320         "hscif1_data_b",
4321         "hscif1_clk_b",
4322         "hscif1_ctrl_b",
4323 };
4324
4325 static const char * const hscif2_groups[] = {
4326         "hscif2_data_a",
4327         "hscif2_clk_a",
4328         "hscif2_ctrl_a",
4329         "hscif2_data_b",
4330         "hscif2_clk_b",
4331         "hscif2_ctrl_b",
4332 };
4333
4334 static const char * const hscif3_groups[] = {
4335         "hscif3_data_a",
4336         "hscif3_clk",
4337         "hscif3_ctrl",
4338         "hscif3_data_b",
4339         "hscif3_data_c",
4340         "hscif3_data_d",
4341 };
4342
4343 static const char * const hscif4_groups[] = {
4344         "hscif4_data_a",
4345         "hscif4_clk",
4346         "hscif4_ctrl",
4347         "hscif4_data_b",
4348 };
4349
4350 static const char * const i2c0_groups[] = {
4351         "i2c0",
4352 };
4353
4354 static const char * const i2c1_groups[] = {
4355         "i2c1_a",
4356         "i2c1_b",
4357 };
4358
4359 static const char * const i2c2_groups[] = {
4360         "i2c2_a",
4361         "i2c2_b",
4362 };
4363
4364 static const char * const i2c3_groups[] = {
4365         "i2c3",
4366 };
4367
4368 static const char * const i2c5_groups[] = {
4369         "i2c5",
4370 };
4371
4372 static const char * const i2c6_groups[] = {
4373         "i2c6_a",
4374         "i2c6_b",
4375         "i2c6_c",
4376 };
4377
4378 static const char * const intc_ex_groups[] = {
4379         "intc_ex_irq0",
4380         "intc_ex_irq1",
4381         "intc_ex_irq2",
4382         "intc_ex_irq3",
4383         "intc_ex_irq4",
4384         "intc_ex_irq5",
4385 };
4386
4387 static const char * const msiof0_groups[] = {
4388         "msiof0_clk",
4389         "msiof0_sync",
4390         "msiof0_ss1",
4391         "msiof0_ss2",
4392         "msiof0_txd",
4393         "msiof0_rxd",
4394 };
4395
4396 static const char * const msiof1_groups[] = {
4397         "msiof1_clk_a",
4398         "msiof1_sync_a",
4399         "msiof1_ss1_a",
4400         "msiof1_ss2_a",
4401         "msiof1_txd_a",
4402         "msiof1_rxd_a",
4403         "msiof1_clk_b",
4404         "msiof1_sync_b",
4405         "msiof1_ss1_b",
4406         "msiof1_ss2_b",
4407         "msiof1_txd_b",
4408         "msiof1_rxd_b",
4409         "msiof1_clk_c",
4410         "msiof1_sync_c",
4411         "msiof1_ss1_c",
4412         "msiof1_ss2_c",
4413         "msiof1_txd_c",
4414         "msiof1_rxd_c",
4415         "msiof1_clk_d",
4416         "msiof1_sync_d",
4417         "msiof1_ss1_d",
4418         "msiof1_ss2_d",
4419         "msiof1_txd_d",
4420         "msiof1_rxd_d",
4421         "msiof1_clk_e",
4422         "msiof1_sync_e",
4423         "msiof1_ss1_e",
4424         "msiof1_ss2_e",
4425         "msiof1_txd_e",
4426         "msiof1_rxd_e",
4427         "msiof1_clk_f",
4428         "msiof1_sync_f",
4429         "msiof1_ss1_f",
4430         "msiof1_ss2_f",
4431         "msiof1_txd_f",
4432         "msiof1_rxd_f",
4433         "msiof1_clk_g",
4434         "msiof1_sync_g",
4435         "msiof1_ss1_g",
4436         "msiof1_ss2_g",
4437         "msiof1_txd_g",
4438         "msiof1_rxd_g",
4439 };
4440
4441 static const char * const msiof2_groups[] = {
4442         "msiof2_clk_a",
4443         "msiof2_sync_a",
4444         "msiof2_ss1_a",
4445         "msiof2_ss2_a",
4446         "msiof2_txd_a",
4447         "msiof2_rxd_a",
4448         "msiof2_clk_b",
4449         "msiof2_sync_b",
4450         "msiof2_ss1_b",
4451         "msiof2_ss2_b",
4452         "msiof2_txd_b",
4453         "msiof2_rxd_b",
4454         "msiof2_clk_c",
4455         "msiof2_sync_c",
4456         "msiof2_ss1_c",
4457         "msiof2_ss2_c",
4458         "msiof2_txd_c",
4459         "msiof2_rxd_c",
4460         "msiof2_clk_d",
4461         "msiof2_sync_d",
4462         "msiof2_ss1_d",
4463         "msiof2_ss2_d",
4464         "msiof2_txd_d",
4465         "msiof2_rxd_d",
4466 };
4467
4468 static const char * const msiof3_groups[] = {
4469         "msiof3_clk_a",
4470         "msiof3_sync_a",
4471         "msiof3_ss1_a",
4472         "msiof3_ss2_a",
4473         "msiof3_txd_a",
4474         "msiof3_rxd_a",
4475         "msiof3_clk_b",
4476         "msiof3_sync_b",
4477         "msiof3_ss1_b",
4478         "msiof3_ss2_b",
4479         "msiof3_txd_b",
4480         "msiof3_rxd_b",
4481         "msiof3_clk_c",
4482         "msiof3_sync_c",
4483         "msiof3_txd_c",
4484         "msiof3_rxd_c",
4485         "msiof3_clk_d",
4486         "msiof3_sync_d",
4487         "msiof3_ss1_d",
4488         "msiof3_txd_d",
4489         "msiof3_rxd_d",
4490 };
4491
4492 static const char * const pwm0_groups[] = {
4493         "pwm0",
4494 };
4495
4496 static const char * const pwm1_groups[] = {
4497         "pwm1_a",
4498         "pwm1_b",
4499 };
4500
4501 static const char * const pwm2_groups[] = {
4502         "pwm2_a",
4503         "pwm2_b",
4504 };
4505
4506 static const char * const pwm3_groups[] = {
4507         "pwm3_a",
4508         "pwm3_b",
4509 };
4510
4511 static const char * const pwm4_groups[] = {
4512         "pwm4_a",
4513         "pwm4_b",
4514 };
4515
4516 static const char * const pwm5_groups[] = {
4517         "pwm5_a",
4518         "pwm5_b",
4519 };
4520
4521 static const char * const pwm6_groups[] = {
4522         "pwm6_a",
4523         "pwm6_b",
4524 };
4525
4526 static const char * const qspi0_groups[] = {
4527         "qspi0_ctrl",
4528         "qspi0_data2",
4529         "qspi0_data4",
4530 };
4531
4532 static const char * const qspi1_groups[] = {
4533         "qspi1_ctrl",
4534         "qspi1_data2",
4535         "qspi1_data4",
4536 };
4537
4538 static const char * const sata0_groups[] = {
4539         "sata0_devslp_a",
4540         "sata0_devslp_b",
4541 };
4542
4543 static const char * const scif0_groups[] = {
4544         "scif0_data",
4545         "scif0_clk",
4546         "scif0_ctrl",
4547 };
4548
4549 static const char * const scif1_groups[] = {
4550         "scif1_data_a",
4551         "scif1_clk",
4552         "scif1_ctrl",
4553         "scif1_data_b",
4554 };
4555
4556 static const char * const scif2_groups[] = {
4557         "scif2_data_a",
4558         "scif2_clk",
4559         "scif2_data_b",
4560 };
4561
4562 static const char * const scif3_groups[] = {
4563         "scif3_data_a",
4564         "scif3_clk",
4565         "scif3_ctrl",
4566         "scif3_data_b",
4567 };
4568
4569 static const char * const scif4_groups[] = {
4570         "scif4_data_a",
4571         "scif4_clk_a",
4572         "scif4_ctrl_a",
4573         "scif4_data_b",
4574         "scif4_clk_b",
4575         "scif4_ctrl_b",
4576         "scif4_data_c",
4577         "scif4_clk_c",
4578         "scif4_ctrl_c",
4579 };
4580
4581 static const char * const scif5_groups[] = {
4582         "scif5_data",
4583         "scif5_clk",
4584 };
4585
4586 static const char * const scif_clk_groups[] = {
4587         "scif_clk_a",
4588         "scif_clk_b",
4589 };
4590
4591 static const char * const sdhi0_groups[] = {
4592         "sdhi0_data1",
4593         "sdhi0_data4",
4594         "sdhi0_ctrl",
4595         "sdhi0_cd",
4596         "sdhi0_wp",
4597 };
4598
4599 static const char * const sdhi1_groups[] = {
4600         "sdhi1_data1",
4601         "sdhi1_data4",
4602         "sdhi1_ctrl",
4603         "sdhi1_cd",
4604         "sdhi1_wp",
4605 };
4606
4607 static const char * const sdhi2_groups[] = {
4608         "sdhi2_data1",
4609         "sdhi2_data4",
4610         "sdhi2_data8",
4611         "sdhi2_ctrl",
4612         "sdhi2_cd_a",
4613         "sdhi2_wp_a",
4614         "sdhi2_cd_b",
4615         "sdhi2_wp_b",
4616         "sdhi2_ds",
4617 };
4618
4619 static const char * const sdhi3_groups[] = {
4620         "sdhi3_data1",
4621         "sdhi3_data4",
4622         "sdhi3_data8",
4623         "sdhi3_ctrl",
4624         "sdhi3_cd",
4625         "sdhi3_wp",
4626         "sdhi3_ds",
4627 };
4628
4629 static const char * const ssi_groups[] = {
4630         "ssi0_data",
4631         "ssi01239_ctrl",
4632         "ssi1_data_a",
4633         "ssi1_data_b",
4634         "ssi1_ctrl_a",
4635         "ssi1_ctrl_b",
4636         "ssi2_data_a",
4637         "ssi2_data_b",
4638         "ssi2_ctrl_a",
4639         "ssi2_ctrl_b",
4640         "ssi3_data",
4641         "ssi349_ctrl",
4642         "ssi4_data",
4643         "ssi4_ctrl",
4644         "ssi5_data",
4645         "ssi5_ctrl",
4646         "ssi6_data",
4647         "ssi6_ctrl",
4648         "ssi7_data",
4649         "ssi78_ctrl",
4650         "ssi8_data",
4651         "ssi9_data_a",
4652         "ssi9_data_b",
4653         "ssi9_ctrl_a",
4654         "ssi9_ctrl_b",
4655 };
4656
4657 static const char * const tmu_groups[] = {
4658         "tmu_tclk1_a",
4659         "tmu_tclk1_b",
4660         "tmu_tclk2_a",
4661         "tmu_tclk2_b",
4662 };
4663
4664 static const char * const usb0_groups[] = {
4665         "usb0",
4666 };
4667
4668 static const char * const usb1_groups[] = {
4669         "usb1",
4670 };
4671
4672 static const char * const usb2_groups[] = {
4673         "usb2",
4674 };
4675
4676 static const char * const usb30_groups[] = {
4677         "usb30",
4678 };
4679
4680 static const char * const usb31_groups[] = {
4681         "usb31",
4682 };
4683
4684 static const struct sh_pfc_function pinmux_functions[] = {
4685         SH_PFC_FUNCTION(audio_clk),
4686         SH_PFC_FUNCTION(avb),
4687         SH_PFC_FUNCTION(can0),
4688         SH_PFC_FUNCTION(can1),
4689         SH_PFC_FUNCTION(can_clk),
4690         SH_PFC_FUNCTION(canfd0),
4691         SH_PFC_FUNCTION(canfd1),
4692         SH_PFC_FUNCTION(drif0),
4693         SH_PFC_FUNCTION(drif1),
4694         SH_PFC_FUNCTION(drif2),
4695         SH_PFC_FUNCTION(drif3),
4696         SH_PFC_FUNCTION(du),
4697         SH_PFC_FUNCTION(hdmi0),
4698         SH_PFC_FUNCTION(hdmi1),
4699         SH_PFC_FUNCTION(hscif0),
4700         SH_PFC_FUNCTION(hscif1),
4701         SH_PFC_FUNCTION(hscif2),
4702         SH_PFC_FUNCTION(hscif3),
4703         SH_PFC_FUNCTION(hscif4),
4704         SH_PFC_FUNCTION(i2c0),
4705         SH_PFC_FUNCTION(i2c1),
4706         SH_PFC_FUNCTION(i2c2),
4707         SH_PFC_FUNCTION(i2c3),
4708         SH_PFC_FUNCTION(i2c5),
4709         SH_PFC_FUNCTION(i2c6),
4710         SH_PFC_FUNCTION(intc_ex),
4711         SH_PFC_FUNCTION(msiof0),
4712         SH_PFC_FUNCTION(msiof1),
4713         SH_PFC_FUNCTION(msiof2),
4714         SH_PFC_FUNCTION(msiof3),
4715         SH_PFC_FUNCTION(pwm0),
4716         SH_PFC_FUNCTION(pwm1),
4717         SH_PFC_FUNCTION(pwm2),
4718         SH_PFC_FUNCTION(pwm3),
4719         SH_PFC_FUNCTION(pwm4),
4720         SH_PFC_FUNCTION(pwm5),
4721         SH_PFC_FUNCTION(pwm6),
4722         SH_PFC_FUNCTION(qspi0),
4723         SH_PFC_FUNCTION(qspi1),
4724         SH_PFC_FUNCTION(sata0),
4725         SH_PFC_FUNCTION(scif0),
4726         SH_PFC_FUNCTION(scif1),
4727         SH_PFC_FUNCTION(scif2),
4728         SH_PFC_FUNCTION(scif3),
4729         SH_PFC_FUNCTION(scif4),
4730         SH_PFC_FUNCTION(scif5),
4731         SH_PFC_FUNCTION(scif_clk),
4732         SH_PFC_FUNCTION(sdhi0),
4733         SH_PFC_FUNCTION(sdhi1),
4734         SH_PFC_FUNCTION(sdhi2),
4735         SH_PFC_FUNCTION(sdhi3),
4736         SH_PFC_FUNCTION(ssi),
4737         SH_PFC_FUNCTION(tmu),
4738         SH_PFC_FUNCTION(usb0),
4739         SH_PFC_FUNCTION(usb1),
4740         SH_PFC_FUNCTION(usb2),
4741         SH_PFC_FUNCTION(usb30),
4742         SH_PFC_FUNCTION(usb31),
4743 };
4744
4745 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4746 #define F_(x, y)        FN_##y
4747 #define FM(x)           FN_##x
4748         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4749                 0, 0,
4750                 0, 0,
4751                 0, 0,
4752                 0, 0,
4753                 0, 0,
4754                 0, 0,
4755                 0, 0,
4756                 0, 0,
4757                 0, 0,
4758                 0, 0,
4759                 0, 0,
4760                 0, 0,
4761                 0, 0,
4762                 0, 0,
4763                 0, 0,
4764                 0, 0,
4765                 GP_0_15_FN,     GPSR0_15,
4766                 GP_0_14_FN,     GPSR0_14,
4767                 GP_0_13_FN,     GPSR0_13,
4768                 GP_0_12_FN,     GPSR0_12,
4769                 GP_0_11_FN,     GPSR0_11,
4770                 GP_0_10_FN,     GPSR0_10,
4771                 GP_0_9_FN,      GPSR0_9,
4772                 GP_0_8_FN,      GPSR0_8,
4773                 GP_0_7_FN,      GPSR0_7,
4774                 GP_0_6_FN,      GPSR0_6,
4775                 GP_0_5_FN,      GPSR0_5,
4776                 GP_0_4_FN,      GPSR0_4,
4777                 GP_0_3_FN,      GPSR0_3,
4778                 GP_0_2_FN,      GPSR0_2,
4779                 GP_0_1_FN,      GPSR0_1,
4780                 GP_0_0_FN,      GPSR0_0, }
4781         },
4782         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4783                 0, 0,
4784                 0, 0,
4785                 0, 0,
4786                 0, 0,
4787                 GP_1_27_FN,     GPSR1_27,
4788                 GP_1_26_FN,     GPSR1_26,
4789                 GP_1_25_FN,     GPSR1_25,
4790                 GP_1_24_FN,     GPSR1_24,
4791                 GP_1_23_FN,     GPSR1_23,
4792                 GP_1_22_FN,     GPSR1_22,
4793                 GP_1_21_FN,     GPSR1_21,
4794                 GP_1_20_FN,     GPSR1_20,
4795                 GP_1_19_FN,     GPSR1_19,
4796                 GP_1_18_FN,     GPSR1_18,
4797                 GP_1_17_FN,     GPSR1_17,
4798                 GP_1_16_FN,     GPSR1_16,
4799                 GP_1_15_FN,     GPSR1_15,
4800                 GP_1_14_FN,     GPSR1_14,
4801                 GP_1_13_FN,     GPSR1_13,
4802                 GP_1_12_FN,     GPSR1_12,
4803                 GP_1_11_FN,     GPSR1_11,
4804                 GP_1_10_FN,     GPSR1_10,
4805                 GP_1_9_FN,      GPSR1_9,
4806                 GP_1_8_FN,      GPSR1_8,
4807                 GP_1_7_FN,      GPSR1_7,
4808                 GP_1_6_FN,      GPSR1_6,
4809                 GP_1_5_FN,      GPSR1_5,
4810                 GP_1_4_FN,      GPSR1_4,
4811                 GP_1_3_FN,      GPSR1_3,
4812                 GP_1_2_FN,      GPSR1_2,
4813                 GP_1_1_FN,      GPSR1_1,
4814                 GP_1_0_FN,      GPSR1_0, }
4815         },
4816         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4817                 0, 0,
4818                 0, 0,
4819                 0, 0,
4820                 0, 0,
4821                 0, 0,
4822                 0, 0,
4823                 0, 0,
4824                 0, 0,
4825                 0, 0,
4826                 0, 0,
4827                 0, 0,
4828                 0, 0,
4829                 0, 0,
4830                 0, 0,
4831                 0, 0,
4832                 0, 0,
4833                 0, 0,
4834                 GP_2_14_FN,     GPSR2_14,
4835                 GP_2_13_FN,     GPSR2_13,
4836                 GP_2_12_FN,     GPSR2_12,
4837                 GP_2_11_FN,     GPSR2_11,
4838                 GP_2_10_FN,     GPSR2_10,
4839                 GP_2_9_FN,      GPSR2_9,
4840                 GP_2_8_FN,      GPSR2_8,
4841                 GP_2_7_FN,      GPSR2_7,
4842                 GP_2_6_FN,      GPSR2_6,
4843                 GP_2_5_FN,      GPSR2_5,
4844                 GP_2_4_FN,      GPSR2_4,
4845                 GP_2_3_FN,      GPSR2_3,
4846                 GP_2_2_FN,      GPSR2_2,
4847                 GP_2_1_FN,      GPSR2_1,
4848                 GP_2_0_FN,      GPSR2_0, }
4849         },
4850         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4851                 0, 0,
4852                 0, 0,
4853                 0, 0,
4854                 0, 0,
4855                 0, 0,
4856                 0, 0,
4857                 0, 0,
4858                 0, 0,
4859                 0, 0,
4860                 0, 0,
4861                 0, 0,
4862                 0, 0,
4863                 0, 0,
4864                 0, 0,
4865                 0, 0,
4866                 0, 0,
4867                 GP_3_15_FN,     GPSR3_15,
4868                 GP_3_14_FN,     GPSR3_14,
4869                 GP_3_13_FN,     GPSR3_13,
4870                 GP_3_12_FN,     GPSR3_12,
4871                 GP_3_11_FN,     GPSR3_11,
4872                 GP_3_10_FN,     GPSR3_10,
4873                 GP_3_9_FN,      GPSR3_9,
4874                 GP_3_8_FN,      GPSR3_8,
4875                 GP_3_7_FN,      GPSR3_7,
4876                 GP_3_6_FN,      GPSR3_6,
4877                 GP_3_5_FN,      GPSR3_5,
4878                 GP_3_4_FN,      GPSR3_4,
4879                 GP_3_3_FN,      GPSR3_3,
4880                 GP_3_2_FN,      GPSR3_2,
4881                 GP_3_1_FN,      GPSR3_1,
4882                 GP_3_0_FN,      GPSR3_0, }
4883         },
4884         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4885                 0, 0,
4886                 0, 0,
4887                 0, 0,
4888                 0, 0,
4889                 0, 0,
4890                 0, 0,
4891                 0, 0,
4892                 0, 0,
4893                 0, 0,
4894                 0, 0,
4895                 0, 0,
4896                 0, 0,
4897                 0, 0,
4898                 0, 0,
4899                 GP_4_17_FN,     GPSR4_17,
4900                 GP_4_16_FN,     GPSR4_16,
4901                 GP_4_15_FN,     GPSR4_15,
4902                 GP_4_14_FN,     GPSR4_14,
4903                 GP_4_13_FN,     GPSR4_13,
4904                 GP_4_12_FN,     GPSR4_12,
4905                 GP_4_11_FN,     GPSR4_11,
4906                 GP_4_10_FN,     GPSR4_10,
4907                 GP_4_9_FN,      GPSR4_9,
4908                 GP_4_8_FN,      GPSR4_8,
4909                 GP_4_7_FN,      GPSR4_7,
4910                 GP_4_6_FN,      GPSR4_6,
4911                 GP_4_5_FN,      GPSR4_5,
4912                 GP_4_4_FN,      GPSR4_4,
4913                 GP_4_3_FN,      GPSR4_3,
4914                 GP_4_2_FN,      GPSR4_2,
4915                 GP_4_1_FN,      GPSR4_1,
4916                 GP_4_0_FN,      GPSR4_0, }
4917         },
4918         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4919                 0, 0,
4920                 0, 0,
4921                 0, 0,
4922                 0, 0,
4923                 0, 0,
4924                 0, 0,
4925                 GP_5_25_FN,     GPSR5_25,
4926                 GP_5_24_FN,     GPSR5_24,
4927                 GP_5_23_FN,     GPSR5_23,
4928                 GP_5_22_FN,     GPSR5_22,
4929                 GP_5_21_FN,     GPSR5_21,
4930                 GP_5_20_FN,     GPSR5_20,
4931                 GP_5_19_FN,     GPSR5_19,
4932                 GP_5_18_FN,     GPSR5_18,
4933                 GP_5_17_FN,     GPSR5_17,
4934                 GP_5_16_FN,     GPSR5_16,
4935                 GP_5_15_FN,     GPSR5_15,
4936                 GP_5_14_FN,     GPSR5_14,
4937                 GP_5_13_FN,     GPSR5_13,
4938                 GP_5_12_FN,     GPSR5_12,
4939                 GP_5_11_FN,     GPSR5_11,
4940                 GP_5_10_FN,     GPSR5_10,
4941                 GP_5_9_FN,      GPSR5_9,
4942                 GP_5_8_FN,      GPSR5_8,
4943                 GP_5_7_FN,      GPSR5_7,
4944                 GP_5_6_FN,      GPSR5_6,
4945                 GP_5_5_FN,      GPSR5_5,
4946                 GP_5_4_FN,      GPSR5_4,
4947                 GP_5_3_FN,      GPSR5_3,
4948                 GP_5_2_FN,      GPSR5_2,
4949                 GP_5_1_FN,      GPSR5_1,
4950                 GP_5_0_FN,      GPSR5_0, }
4951         },
4952         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4953                 GP_6_31_FN,     GPSR6_31,
4954                 GP_6_30_FN,     GPSR6_30,
4955                 GP_6_29_FN,     GPSR6_29,
4956                 GP_6_28_FN,     GPSR6_28,
4957                 GP_6_27_FN,     GPSR6_27,
4958                 GP_6_26_FN,     GPSR6_26,
4959                 GP_6_25_FN,     GPSR6_25,
4960                 GP_6_24_FN,     GPSR6_24,
4961                 GP_6_23_FN,     GPSR6_23,
4962                 GP_6_22_FN,     GPSR6_22,
4963                 GP_6_21_FN,     GPSR6_21,
4964                 GP_6_20_FN,     GPSR6_20,
4965                 GP_6_19_FN,     GPSR6_19,
4966                 GP_6_18_FN,     GPSR6_18,
4967                 GP_6_17_FN,     GPSR6_17,
4968                 GP_6_16_FN,     GPSR6_16,
4969                 GP_6_15_FN,     GPSR6_15,
4970                 GP_6_14_FN,     GPSR6_14,
4971                 GP_6_13_FN,     GPSR6_13,
4972                 GP_6_12_FN,     GPSR6_12,
4973                 GP_6_11_FN,     GPSR6_11,
4974                 GP_6_10_FN,     GPSR6_10,
4975                 GP_6_9_FN,      GPSR6_9,
4976                 GP_6_8_FN,      GPSR6_8,
4977                 GP_6_7_FN,      GPSR6_7,
4978                 GP_6_6_FN,      GPSR6_6,
4979                 GP_6_5_FN,      GPSR6_5,
4980                 GP_6_4_FN,      GPSR6_4,
4981                 GP_6_3_FN,      GPSR6_3,
4982                 GP_6_2_FN,      GPSR6_2,
4983                 GP_6_1_FN,      GPSR6_1,
4984                 GP_6_0_FN,      GPSR6_0, }
4985         },
4986         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4987                 0, 0,
4988                 0, 0,
4989                 0, 0,
4990                 0, 0,
4991                 0, 0,
4992                 0, 0,
4993                 0, 0,
4994                 0, 0,
4995                 0, 0,
4996                 0, 0,
4997                 0, 0,
4998                 0, 0,
4999                 0, 0,
5000                 0, 0,
5001                 0, 0,
5002                 0, 0,
5003                 0, 0,
5004                 0, 0,
5005                 0, 0,
5006                 0, 0,
5007                 0, 0,
5008                 0, 0,
5009                 0, 0,
5010                 0, 0,
5011                 0, 0,
5012                 0, 0,
5013                 0, 0,
5014                 0, 0,
5015                 GP_7_3_FN, GPSR7_3,
5016                 GP_7_2_FN, GPSR7_2,
5017                 GP_7_1_FN, GPSR7_1,
5018                 GP_7_0_FN, GPSR7_0, }
5019         },
5020 #undef F_
5021 #undef FM
5022
5023 #define F_(x, y)        x,
5024 #define FM(x)           FN_##x,
5025         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5026                 IP0_31_28
5027                 IP0_27_24
5028                 IP0_23_20
5029                 IP0_19_16
5030                 IP0_15_12
5031                 IP0_11_8
5032                 IP0_7_4
5033                 IP0_3_0 }
5034         },
5035         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5036                 IP1_31_28
5037                 IP1_27_24
5038                 IP1_23_20
5039                 IP1_19_16
5040                 IP1_15_12
5041                 IP1_11_8
5042                 IP1_7_4
5043                 IP1_3_0 }
5044         },
5045         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5046                 IP2_31_28
5047                 IP2_27_24
5048                 IP2_23_20
5049                 IP2_19_16
5050                 IP2_15_12
5051                 IP2_11_8
5052                 IP2_7_4
5053                 IP2_3_0 }
5054         },
5055         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5056                 IP3_31_28
5057                 IP3_27_24
5058                 IP3_23_20
5059                 IP3_19_16
5060                 IP3_15_12
5061                 IP3_11_8
5062                 IP3_7_4
5063                 IP3_3_0 }
5064         },
5065         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5066                 IP4_31_28
5067                 IP4_27_24
5068                 IP4_23_20
5069                 IP4_19_16
5070                 IP4_15_12
5071                 IP4_11_8
5072                 IP4_7_4
5073                 IP4_3_0 }
5074         },
5075         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5076                 IP5_31_28
5077                 IP5_27_24
5078                 IP5_23_20
5079                 IP5_19_16
5080                 IP5_15_12
5081                 IP5_11_8
5082                 IP5_7_4
5083                 IP5_3_0 }
5084         },
5085         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5086                 IP6_31_28
5087                 IP6_27_24
5088                 IP6_23_20
5089                 IP6_19_16
5090                 IP6_15_12
5091                 IP6_11_8
5092                 IP6_7_4
5093                 IP6_3_0 }
5094         },
5095         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5096                 IP7_31_28
5097                 IP7_27_24
5098                 IP7_23_20
5099                 IP7_19_16
5100                 IP7_15_12
5101                 IP7_11_8
5102                 IP7_7_4
5103                 IP7_3_0 }
5104         },
5105         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5106                 IP8_31_28
5107                 IP8_27_24
5108                 IP8_23_20
5109                 IP8_19_16
5110                 IP8_15_12
5111                 IP8_11_8
5112                 IP8_7_4
5113                 IP8_3_0 }
5114         },
5115         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5116                 IP9_31_28
5117                 IP9_27_24
5118                 IP9_23_20
5119                 IP9_19_16
5120                 IP9_15_12
5121                 IP9_11_8
5122                 IP9_7_4
5123                 IP9_3_0 }
5124         },
5125         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5126                 IP10_31_28
5127                 IP10_27_24
5128                 IP10_23_20
5129                 IP10_19_16
5130                 IP10_15_12
5131                 IP10_11_8
5132                 IP10_7_4
5133                 IP10_3_0 }
5134         },
5135         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5136                 IP11_31_28
5137                 IP11_27_24
5138                 IP11_23_20
5139                 IP11_19_16
5140                 IP11_15_12
5141                 IP11_11_8
5142                 IP11_7_4
5143                 IP11_3_0 }
5144         },
5145         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5146                 IP12_31_28
5147                 IP12_27_24
5148                 IP12_23_20
5149                 IP12_19_16
5150                 IP12_15_12
5151                 IP12_11_8
5152                 IP12_7_4
5153                 IP12_3_0 }
5154         },
5155         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5156                 IP13_31_28
5157                 IP13_27_24
5158                 IP13_23_20
5159                 IP13_19_16
5160                 IP13_15_12
5161                 IP13_11_8
5162                 IP13_7_4
5163                 IP13_3_0 }
5164         },
5165         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5166                 IP14_31_28
5167                 IP14_27_24
5168                 IP14_23_20
5169                 IP14_19_16
5170                 IP14_15_12
5171                 IP14_11_8
5172                 IP14_7_4
5173                 IP14_3_0 }
5174         },
5175         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5176                 IP15_31_28
5177                 IP15_27_24
5178                 IP15_23_20
5179                 IP15_19_16
5180                 IP15_15_12
5181                 IP15_11_8
5182                 IP15_7_4
5183                 IP15_3_0 }
5184         },
5185         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5186                 IP16_31_28
5187                 IP16_27_24
5188                 IP16_23_20
5189                 IP16_19_16
5190                 IP16_15_12
5191                 IP16_11_8
5192                 IP16_7_4
5193                 IP16_3_0 }
5194         },
5195         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5196                 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5197                 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5198                 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5199                 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5200                 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5201                 /* IP17_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5202                 IP17_7_4
5203                 IP17_3_0 }
5204         },
5205 #undef F_
5206 #undef FM
5207
5208 #define F_(x, y)        x,
5209 #define FM(x)           FN_##x,
5210         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5211                              1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
5212                              2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
5213                 0, 0, /* RESERVED 31 */
5214                 MOD_SEL0_30_29
5215                 MOD_SEL0_28_27
5216                 MOD_SEL0_26_25_24
5217                 MOD_SEL0_23
5218                 MOD_SEL0_22
5219                 MOD_SEL0_21_20
5220                 MOD_SEL0_19
5221                 MOD_SEL0_18
5222                 MOD_SEL0_17
5223                 MOD_SEL0_16_15
5224                 MOD_SEL0_14
5225                 MOD_SEL0_13
5226                 MOD_SEL0_12
5227                 MOD_SEL0_11
5228                 MOD_SEL0_10
5229                 MOD_SEL0_9
5230                 MOD_SEL0_8
5231                 MOD_SEL0_7_6
5232                 MOD_SEL0_5_4
5233                 MOD_SEL0_3
5234                 MOD_SEL0_2_1
5235                 0, 0, /* RESERVED 0 */ }
5236         },
5237         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5238                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5239                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5240                 MOD_SEL1_31_30
5241                 MOD_SEL1_29_28_27
5242                 MOD_SEL1_26
5243                 MOD_SEL1_25_24
5244                 MOD_SEL1_23_22_21
5245                 MOD_SEL1_20
5246                 MOD_SEL1_19
5247                 MOD_SEL1_18_17
5248                 MOD_SEL1_16
5249                 MOD_SEL1_15_14
5250                 MOD_SEL1_13
5251                 MOD_SEL1_12
5252                 MOD_SEL1_11
5253                 MOD_SEL1_10
5254                 MOD_SEL1_9
5255                 0, 0, 0, 0, /* RESERVED 8, 7 */
5256                 MOD_SEL1_6
5257                 MOD_SEL1_5
5258                 MOD_SEL1_4
5259                 MOD_SEL1_3
5260                 MOD_SEL1_2
5261                 MOD_SEL1_1
5262                 MOD_SEL1_0 }
5263         },
5264         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5265                              1, 1, 1, 1, 4, 4, 4,
5266                              4, 4, 4, 1, 2, 1) {
5267                 MOD_SEL2_31
5268                 MOD_SEL2_30
5269                 MOD_SEL2_29
5270                 /* RESERVED 28 */
5271                 0, 0,
5272                 /* RESERVED 27, 26, 25, 24 */
5273                 0, 0, 0, 0, 0, 0, 0, 0,
5274                 0, 0, 0, 0, 0, 0, 0, 0,
5275                 /* RESERVED 23, 22, 21, 20 */
5276                 0, 0, 0, 0, 0, 0, 0, 0,
5277                 0, 0, 0, 0, 0, 0, 0, 0,
5278                 /* RESERVED 19, 18, 17, 16 */
5279                 0, 0, 0, 0, 0, 0, 0, 0,
5280                 0, 0, 0, 0, 0, 0, 0, 0,
5281                 /* RESERVED 15, 14, 13, 12 */
5282                 0, 0, 0, 0, 0, 0, 0, 0,
5283                 0, 0, 0, 0, 0, 0, 0, 0,
5284                 /* RESERVED 11, 10, 9, 8 */
5285                 0, 0, 0, 0, 0, 0, 0, 0,
5286                 0, 0, 0, 0, 0, 0, 0, 0,
5287                 /* RESERVED 7, 6, 5, 4 */
5288                 0, 0, 0, 0, 0, 0, 0, 0,
5289                 0, 0, 0, 0, 0, 0, 0, 0,
5290                 /* RESERVED 3 */
5291                 0, 0,
5292                 /* RESERVED 2, 1 */
5293                 0, 0, 0, 0,
5294                 MOD_SEL2_0 }
5295         },
5296         { },
5297 };
5298
5299 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5300         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5301                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5302                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5303                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5304                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5305                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5306                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5307                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5308                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5309         } },
5310         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5311                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5312                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5313                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5314                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5315                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5316                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5317                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5318                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5319         } },
5320         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5321                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5322                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5323                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5324                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5325                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5326                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5327                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5328                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5329         } },
5330         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5331                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5332                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5333                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5334                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5335                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5336                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5337                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5338                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5339         } },
5340         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5341                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5342                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5343                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5344                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5345                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5346                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5347                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5348                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5349         } },
5350         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5351                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5352                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5353                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5354                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5355                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5356                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5357                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5358                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5359         } },
5360         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5361                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5362                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5363                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5364                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5365                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5366                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5367                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5368                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5369         } },
5370         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5371                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5372                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5373                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5374                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5375                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5376                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5377                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5378                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5379         } },
5380         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5381                 { PIN_NUMBER('F', 1), 28, 3 },  /* CLKOUT */
5382                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5383                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5384                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5385                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5386                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5387                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5388                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5389         } },
5390         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5391                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5392                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5393                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5394                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5395                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5396                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5397                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5398                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5399         } },
5400         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5401                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5402                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5403                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5404                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5405                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5406                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5407                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5408                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5409         } },
5410         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5411                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5412                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5413                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5414                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5415                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5416                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* HDMI1_CEC */
5417                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5418                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5419         } },
5420         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5421                 { PIN_A_NUMBER('R', 7),  28, 2 },       /* DU_DOTCLKIN2 */
5422                 { PIN_A_NUMBER('R', 8),  24, 2 },       /* DU_DOTCLKIN3 */
5423                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST# */
5424                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5425         } },
5426         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5427                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5428                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5429                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5430                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5431                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5432                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5433                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5434                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5435         } },
5436         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5437                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5438                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5439                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5440                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5441                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5442                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5443                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5444                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5445         } },
5446         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5447                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5448                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5449                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5450                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5451                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5452                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5453                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5454                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5455         } },
5456         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5457                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5458                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5459                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5460                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5461                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5462                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5463                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5464                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5465         } },
5466         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5467                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5468                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5469                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5470                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5471                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5472                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5473                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5474                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5475         } },
5476         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5477                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0_TANS */
5478                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5479                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5480                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5481                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1_TANS */
5482                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5483                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5484                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5485         } },
5486         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5487                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5488                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5489                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5490                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5491                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5492                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5493                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5494                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5495         } },
5496         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5497                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5498                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5499                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5500                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5501                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5502                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5503                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5504                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5505         } },
5506         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5507                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5508                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5509                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5510                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5511                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5512                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5513                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5514                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5515         } },
5516         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5517                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5518                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5519                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5520                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5521                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5522                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5523                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5524                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5525         } },
5526         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5527                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5528                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5529                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5530                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5531                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5532                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5533                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5534                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5535         } },
5536         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5537                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5538                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5539                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5540                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5541                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5542                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* USB31_PWEN */
5543                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* USB31_OVC */
5544         } },
5545         { },
5546 };
5547
5548 enum ioctrl_regs {
5549         POCCTRL,
5550         TDSELCTRL,
5551 };
5552
5553 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5554         [POCCTRL] = { 0xe6060380, },
5555         [TDSELCTRL] = { 0xe60603c0, },
5556         { /* sentinel */ },
5557 };
5558
5559 static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5560                                      u32 *pocctrl)
5561 {
5562         int bit = -EINVAL;
5563
5564         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5565
5566         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5567                 bit = pin & 0x1f;
5568
5569         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5570                 bit = (pin & 0x1f) + 12;
5571
5572         return bit;
5573 }
5574
5575 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5576         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5577                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5578                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5579                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5580                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5581                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5582                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5583                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5584                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5585                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5586                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5587                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5588                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5589                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5590                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5591                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5592                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5593                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5594                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5595                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5596                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5597                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5598                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5599                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5600                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5601                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5602                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5603                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5604                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5605                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5606                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5607                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5608                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5609         } },
5610         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5611                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5612                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5613                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5614                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5615                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5616                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5617                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5618                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5619                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5620                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5621                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5622                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5623                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5624                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5625                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5626                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5627                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5628                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5629                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5630                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5631                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5632                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5633                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5634                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5635                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5636                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5637                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5638                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5639                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5640                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5641                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5642                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5643         } },
5644         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5645                 [ 0] = PIN_NUMBER('F', 1),      /* CLKOUT */
5646                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5647                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N_A26 */
5648                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5649                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5650                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5651                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5652                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5653                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5654                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5655                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5656                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5657                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5658                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5659                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5660                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5661                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5662                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5663                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5664                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5665                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5666                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5667                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5668                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5669                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5670                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5671                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5672                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5673                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5674                 [29] = RCAR_GP_PIN(7,  3),      /* HDMI1_CEC */
5675                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5676                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5677         } },
5678         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5679                 [ 0] = PIN_A_NUMBER('R', 7),    /* DU_DOTCLKIN2 */
5680                 [ 1] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
5681                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST# */
5682                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5683                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5684                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5685                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5686                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5687                 [ 8] = PIN_NONE,
5688                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5689                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5690                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5691                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5692                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5693                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5694                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5695                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5696                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5697                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5698                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5699                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5700                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5701                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5702                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5703                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5704                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5705                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5706                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5707                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5708                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5709                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5710                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5711         } },
5712         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5713                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5714                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5715                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5716                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5717                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5718                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5719                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5720                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5721                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5722                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5723                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5724                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5725                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5726                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5727                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5728                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5729                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N_TANS */
5730                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5731                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5732                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5733                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N_TANS */
5734                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5735                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5736                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5737                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5738                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5739                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5740                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5741                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5742                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5743                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5744                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5745         } },
5746         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5747                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5748                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5749                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5750                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5751                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5752                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5753                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5754                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5755                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5756                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5757                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5758                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5759                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5760                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5761                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5762                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5763                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5764                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5765                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5766                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5767                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5768                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5769                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5770                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5771                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5772                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5773                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5774                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5775                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5776                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5777                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5778                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5779         } },
5780         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5781                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5782                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5783                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5784                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5785                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5786                 [ 5] = RCAR_GP_PIN(6, 30),      /* USB31_PWEN */
5787                 [ 6] = RCAR_GP_PIN(6, 31),      /* USB31_OVC */
5788                 [ 7] = PIN_NONE,
5789                 [ 8] = PIN_NONE,
5790                 [ 9] = PIN_NONE,
5791                 [10] = PIN_NONE,
5792                 [11] = PIN_NONE,
5793                 [12] = PIN_NONE,
5794                 [13] = PIN_NONE,
5795                 [14] = PIN_NONE,
5796                 [15] = PIN_NONE,
5797                 [16] = PIN_NONE,
5798                 [17] = PIN_NONE,
5799                 [18] = PIN_NONE,
5800                 [19] = PIN_NONE,
5801                 [20] = PIN_NONE,
5802                 [21] = PIN_NONE,
5803                 [22] = PIN_NONE,
5804                 [23] = PIN_NONE,
5805                 [24] = PIN_NONE,
5806                 [25] = PIN_NONE,
5807                 [26] = PIN_NONE,
5808                 [27] = PIN_NONE,
5809                 [28] = PIN_NONE,
5810                 [29] = PIN_NONE,
5811                 [30] = PIN_NONE,
5812                 [31] = PIN_NONE,
5813         } },
5814         { /* sentinel */ },
5815 };
5816
5817 static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
5818                                                unsigned int pin)
5819 {
5820         const struct pinmux_bias_reg *reg;
5821         unsigned int bit;
5822
5823         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5824         if (!reg)
5825                 return PIN_CONFIG_BIAS_DISABLE;
5826
5827         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5828                 return PIN_CONFIG_BIAS_DISABLE;
5829         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5830                 return PIN_CONFIG_BIAS_PULL_UP;
5831         else
5832                 return PIN_CONFIG_BIAS_PULL_DOWN;
5833 }
5834
5835 static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5836                                        unsigned int bias)
5837 {
5838         const struct pinmux_bias_reg *reg;
5839         u32 enable, updown;
5840         unsigned int bit;
5841
5842         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5843         if (!reg)
5844                 return;
5845
5846         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5847         if (bias != PIN_CONFIG_BIAS_DISABLE)
5848                 enable |= BIT(bit);
5849
5850         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5851         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5852                 updown |= BIT(bit);
5853
5854         sh_pfc_write(pfc, reg->pud, updown);
5855         sh_pfc_write(pfc, reg->puen, enable);
5856 }
5857
5858 static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
5859         .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,
5860         .get_bias = r8a7795es1_pinmux_get_bias,
5861         .set_bias = r8a7795es1_pinmux_set_bias,
5862 };
5863
5864 const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
5865         .name = "r8a77950_pfc",
5866         .ops = &r8a7795es1_pinmux_ops,
5867         .unlock_reg = 0xe6060000, /* PMMR */
5868
5869         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5870
5871         .pins = pinmux_pins,
5872         .nr_pins = ARRAY_SIZE(pinmux_pins),
5873         .groups = pinmux_groups,
5874         .nr_groups = ARRAY_SIZE(pinmux_groups),
5875         .functions = pinmux_functions,
5876         .nr_functions = ARRAY_SIZE(pinmux_functions),
5877
5878         .cfg_regs = pinmux_config_regs,
5879         .drive_regs = pinmux_drive_regs,
5880         .bias_regs = pinmux_bias_regs,
5881         .ioctrl_regs = pinmux_ioctrl_regs,
5882
5883         .pinmux_data = pinmux_data,
5884         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5885 };