drivers/pinctrl/sh-pfc/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control and GPIO driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  */
  10
  11 #define DRV_NAME "sh-pfc"
  12
  13 #include <linux/bitops.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/psci.h>
  25 #include <linux/slab.h>
  26
  27 #include "core.h"
  28
  29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  30                                 struct platform_device *pdev)
  31 {
  32         struct sh_pfc_window *windows;
  33         unsigned int *irqs = NULL;
  34         unsigned int num_windows;
  35         struct resource *res;
  36         unsigned int i;
  37         int num_irqs;
  38
  39         /* Count the MEM and IRQ resources. */
  40         for (num_windows = 0;; num_windows++) {
  41                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
  42                 if (!res)
  43                         break;
  44         }
  45         if (num_windows == 0)
  46                 return -EINVAL;
  47
  48         num_irqs = platform_irq_count(pdev);
  49         if (num_irqs < 0)
  50                 return num_irqs;
  51
  52         /* Allocate memory windows and IRQs arrays. */
  53         windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
  54                                GFP_KERNEL);
  55         if (windows == NULL)
  56                 return -ENOMEM;
  57
  58         pfc->num_windows = num_windows;
  59         pfc->windows = windows;
  60
  61         if (num_irqs) {
  62                 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
  63                                     GFP_KERNEL);
  64                 if (irqs == NULL)
  65                         return -ENOMEM;
  66
  67                 pfc->num_irqs = num_irqs;
  68                 pfc->irqs = irqs;
  69         }
  70
  71         /* Fill them. */
  72         for (i = 0; i < num_windows; i++) {
  73                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  74                 windows->phys = res->start;
  75                 windows->size = resource_size(res);
  76                 windows->virt = devm_ioremap_resource(pfc->dev, res);
  77                 if (IS_ERR(windows->virt))
  78                         return -ENOMEM;
  79                 windows++;
  80         }
  81         for (i = 0; i < num_irqs; i++)
  82                 *irqs++ = platform_get_irq(pdev, i);
  83
  84         return 0;
  85 }
  86
  87 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
  88 {
  89         struct sh_pfc_window *window;
  90         phys_addr_t address = reg;
  91         unsigned int i;
  92
  93         /* scan through physical windows and convert address */
  94         for (i = 0; i < pfc->num_windows; i++) {
  95                 window = pfc->windows + i;
  96
  97                 if (address < window->phys)
  98                         continue;
  99
 100                 if (address >= (window->phys + window->size))
 101                         continue;
 102
 103                 return window->virt + (address - window->phys);
 104         }
 105
 106         BUG();
 107         return NULL;
 108 }
 109
 110 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 111 {
 112         unsigned int offset;
 113         unsigned int i;
 114
 115         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 116                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 117
 118                 if (pin <= range->end)
 119                         return pin >= range->start
 120                              ? offset + pin - range->start : -1;
 121
 122                 offset += range->end - range->start + 1;
 123         }
 124
 125         return -EINVAL;
 126 }
 127
 128 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 129 {
 130         if (enum_id < r->begin)
 131                 return 0;
 132
 133         if (enum_id > r->end)
 134                 return 0;
 135
 136         return 1;
 137 }
 138
 139 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
 140 {
 141         switch (reg_width) {
 142         case 8:
 143                 return ioread8(mapped_reg);
 144         case 16:
 145                 return ioread16(mapped_reg);
 146         case 32:
 147                 return ioread32(mapped_reg);
 148         }
 149
 150         BUG();
 151         return 0;
 152 }
 153
 154 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 155                           u32 data)
 156 {
 157         switch (reg_width) {
 158         case 8:
 159                 iowrite8(data, mapped_reg);
 160                 return;
 161         case 16:
 162                 iowrite16(data, mapped_reg);
 163                 return;
 164         case 32:
 165                 iowrite32(data, mapped_reg);
 166                 return;
 167         }
 168
 169         BUG();
 170 }
 171
 172 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 173 {
 174         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
 175 }
 176
 177 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 178 {
 179         if (pfc->info->unlock_reg)
 180                 sh_pfc_write_raw_reg(
 181                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 182                         ~data);
 183
 184         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
 185 }
 186
 187 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 188                                      const struct pinmux_cfg_reg *crp,
 189                                      unsigned int in_pos,
 190                                      void __iomem **mapped_regp, u32 *maskp,
 191                                      unsigned int *posp)
 192 {
 193         unsigned int k;
 194
 195         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 196
 197         if (crp->field_width) {
 198                 *maskp = (1 << crp->field_width) - 1;
 199                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 200         } else {
 201                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 202                 *posp = crp->reg_width;
 203                 for (k = 0; k <= in_pos; k++)
 204                         *posp -= crp->var_field_width[k];
 205         }
 206 }
 207
 208 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 209                                     const struct pinmux_cfg_reg *crp,
 210                                     unsigned int field, u32 value)
 211 {
 212         void __iomem *mapped_reg;
 213         unsigned int pos;
 214         u32 mask, data;
 215
 216         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 217
 218         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 219                 "r_width = %u, f_width = %u\n",
 220                 crp->reg, value, field, crp->reg_width, hweight32(mask));
 221
 222         mask = ~(mask << pos);
 223         value = value << pos;
 224
 225         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 226         data &= mask;
 227         data |= value;
 228
 229         if (pfc->info->unlock_reg)
 230                 sh_pfc_write_raw_reg(
 231                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 232                         ~data);
 233
 234         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 235 }
 236
 237 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 238                                  const struct pinmux_cfg_reg **crp,
 239                                  unsigned int *fieldp, u32 *valuep)
 240 {
 241         unsigned int k = 0;
 242
 243         while (1) {
 244                 const struct pinmux_cfg_reg *config_reg =
 245                         pfc->info->cfg_regs + k;
 246                 unsigned int r_width = config_reg->reg_width;
 247                 unsigned int f_width = config_reg->field_width;
 248                 unsigned int curr_width;
 249                 unsigned int bit_pos;
 250                 unsigned int pos = 0;
 251                 unsigned int m = 0;
 252
 253                 if (!r_width)
 254                         break;
 255
 256                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 257                         u32 ncomb;
 258                         u32 n;
 259
 260                         if (f_width)
 261                                 curr_width = f_width;
 262                         else
 263                                 curr_width = config_reg->var_field_width[m];
 264
 265                         ncomb = 1 << curr_width;
 266                         for (n = 0; n < ncomb; n++) {
 267                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 268                                         *crp = config_reg;
 269                                         *fieldp = m;
 270                                         *valuep = n;
 271                                         return 0;
 272                                 }
 273                         }
 274                         pos += ncomb;
 275                         m++;
 276                 }
 277                 k++;
 278         }
 279
 280         return -EINVAL;
 281 }
 282
 283 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 284                               u16 *enum_idp)
 285 {
 286         const u16 *data = pfc->info->pinmux_data;
 287         unsigned int k;
 288
 289         if (pos) {
 290                 *enum_idp = data[pos + 1];
 291                 return pos + 1;
 292         }
 293
 294         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 295                 if (data[k] == mark) {
 296                         *enum_idp = data[k + 1];
 297                         return k + 1;
 298                 }
 299         }
 300
 301         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 302                 mark);
 303         return -EINVAL;
 304 }
 305
 306 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 307 {
 308         const struct pinmux_range *range;
 309         int pos = 0;
 310
 311         switch (pinmux_type) {
 312         case PINMUX_TYPE_GPIO:
 313         case PINMUX_TYPE_FUNCTION:
 314                 range = NULL;
 315                 break;
 316
 317         case PINMUX_TYPE_OUTPUT:
 318                 range = &pfc->info->output;
 319                 break;
 320
 321         case PINMUX_TYPE_INPUT:
 322                 range = &pfc->info->input;
 323                 break;
 324
 325         default:
 326                 return -EINVAL;
 327         }
 328
 329         /* Iterate over all the configuration fields we need to update. */
 330         while (1) {
 331                 const struct pinmux_cfg_reg *cr;
 332                 unsigned int field;
 333                 u16 enum_id;
 334                 u32 value;
 335                 int in_range;
 336                 int ret;
 337
 338                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 339                 if (pos < 0)
 340                         return pos;
 341
 342                 if (!enum_id)
 343                         break;
 344
 345                 /* Check if the configuration field selects a function. If it
 346                  * doesn't, skip the field if it's not applicable to the
 347                  * requested pinmux type.
 348                  */
 349                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 350                 if (!in_range) {
 351                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 352                                 /* Functions are allowed to modify all
 353                                  * fields.
 354                                  */
 355                                 in_range = 1;
 356                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 357                                 /* Input/output types can only modify fields
 358                                  * that correspond to their respective ranges.
 359                                  */
 360                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 361
 362                                 /*
 363                                  * special case pass through for fixed
 364                                  * input-only or output-only pins without
 365                                  * function enum register association.
 366                                  */
 367                                 if (in_range && enum_id == range->force)
 368                                         continue;
 369                         }
 370                         /* GPIOs are only allowed to modify function fields. */
 371                 }
 372
 373                 if (!in_range)
 374                         continue;
 375
 376                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 377                 if (ret < 0)
 378                         return ret;
 379
 380                 sh_pfc_write_config_reg(pfc, cr, field, value);
 381         }
 382
 383         return 0;
 384 }
 385
 386 const struct pinmux_bias_reg *
 387 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 388                        unsigned int *bit)
 389 {
 390         unsigned int i, j;
 391
 392         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 393                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 394                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 395                                 *bit = j;
 396                                 return &pfc->info->bias_regs[i];
 397                         }
 398                 }
 399         }
 400
 401         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 402
 403         return NULL;
 404 }
 405
 406 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 407 {
 408         struct sh_pfc_pin_range *range;
 409         unsigned int nr_ranges;
 410         unsigned int i;
 411
 412         if (pfc->info->pins[0].pin == (u16)-1) {
 413                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 414                  * in its pin arrays yet. Consider the pin numbers range as
 415                  * continuous and allocate a single range.
 416                  */
 417                 pfc->nr_ranges = 1;
 418                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 419                                            GFP_KERNEL);
 420                 if (pfc->ranges == NULL)
 421                         return -ENOMEM;
 422
 423                 pfc->ranges->start = 0;
 424                 pfc->ranges->end = pfc->info->nr_pins - 1;
 425                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 426
 427                 return 0;
 428         }
 429
 430         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 431          * be sorted by pin numbers, and pins without a GPIO port must come
 432          * last.
 433          */
 434         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 435                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 436                         nr_ranges++;
 437         }
 438
 439         pfc->nr_ranges = nr_ranges;
 440         pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
 441                                    GFP_KERNEL);
 442         if (pfc->ranges == NULL)
 443                 return -ENOMEM;
 444
 445         range = pfc->ranges;
 446         range->start = pfc->info->pins[0].pin;
 447
 448         for (i = 1; i < pfc->info->nr_pins; ++i) {
 449                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 450                         continue;
 451
 452                 range->end = pfc->info->pins[i-1].pin;
 453                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 454                         pfc->nr_gpio_pins = range->end + 1;
 455
 456                 range++;
 457                 range->start = pfc->info->pins[i].pin;
 458         }
 459
 460         range->end = pfc->info->pins[i-1].pin;
 461         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 462                 pfc->nr_gpio_pins = range->end + 1;
 463
 464         return 0;
 465 }
 466
 467 #ifdef CONFIG_OF
 468 static const struct of_device_id sh_pfc_of_table[] = {
 469 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 470         {
 471                 .compatible = "renesas,pfc-emev2",
 472                 .data = &emev2_pinmux_info,
 473         },
 474 #endif
 475 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 476         {
 477                 .compatible = "renesas,pfc-r8a73a4",
 478                 .data = &r8a73a4_pinmux_info,
 479         },
 480 #endif
 481 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 482         {
 483                 .compatible = "renesas,pfc-r8a7740",
 484                 .data = &r8a7740_pinmux_info,
 485         },
 486 #endif
 487 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 488         {
 489                 .compatible = "renesas,pfc-r8a7743",
 490                 .data = &r8a7743_pinmux_info,
 491         },
 492 #endif
 493 #ifdef CONFIG_PINCTRL_PFC_R8A7744
 494         {
 495                 .compatible = "renesas,pfc-r8a7744",
 496                 .data = &r8a7744_pinmux_info,
 497         },
 498 #endif
 499 #ifdef CONFIG_PINCTRL_PFC_R8A7745
 500         {
 501                 .compatible = "renesas,pfc-r8a7745",
 502                 .data = &r8a7745_pinmux_info,
 503         },
 504 #endif
 505 #ifdef CONFIG_PINCTRL_PFC_R8A77470
 506         {
 507                 .compatible = "renesas,pfc-r8a77470",
 508                 .data = &r8a77470_pinmux_info,
 509         },
 510 #endif
 511 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 512         {
 513                 .compatible = "renesas,pfc-r8a774a1",
 514                 .data = &r8a774a1_pinmux_info,
 515         },
 516 #endif
 517 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
 518         {
 519                 .compatible = "renesas,pfc-r8a774b1",
 520                 .data = &r8a774b1_pinmux_info,
 521         },
 522 #endif
 523 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
 524         {
 525                 .compatible = "renesas,pfc-r8a774c0",
 526                 .data = &r8a774c0_pinmux_info,
 527         },
 528 #endif
 529 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 530         {
 531                 .compatible = "renesas,pfc-r8a7778",
 532                 .data = &r8a7778_pinmux_info,
 533         },
 534 #endif
 535 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 536         {
 537                 .compatible = "renesas,pfc-r8a7779",
 538                 .data = &r8a7779_pinmux_info,
 539         },
 540 #endif
 541 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 542         {
 543                 .compatible = "renesas,pfc-r8a7790",
 544                 .data = &r8a7790_pinmux_info,
 545         },
 546 #endif
 547 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 548         {
 549                 .compatible = "renesas,pfc-r8a7791",
 550                 .data = &r8a7791_pinmux_info,
 551         },
 552 #endif
 553 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 554         {
 555                 .compatible = "renesas,pfc-r8a7792",
 556                 .data = &r8a7792_pinmux_info,
 557         },
 558 #endif
 559 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 560         {
 561                 .compatible = "renesas,pfc-r8a7793",
 562                 .data = &r8a7793_pinmux_info,
 563         },
 564 #endif
 565 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 566         {
 567                 .compatible = "renesas,pfc-r8a7794",
 568                 .data = &r8a7794_pinmux_info,
 569         },
 570 #endif
 571 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 572         {
 573                 .compatible = "renesas,pfc-r8a7795",
 574                 .data = &r8a7795_pinmux_info,
 575         },
 576 #ifdef DEBUG
 577         {
 578                 /* For sanity checks only (nothing matches against this) */
 579                 .compatible = "renesas,pfc-r8a77950",   /* R-Car H3 ES1.0 */
 580                 .data = &r8a7795es1_pinmux_info,
 581         },
 582 #endif /* DEBUG */
 583 #endif
 584 #ifdef CONFIG_PINCTRL_PFC_R8A77960
 585         {
 586                 .compatible = "renesas,pfc-r8a7796",
 587                 .data = &r8a77960_pinmux_info,
 588         },
 589 #endif
 590 #ifdef CONFIG_PINCTRL_PFC_R8A77961
 591         {
 592                 .compatible = "renesas,pfc-r8a77961",
 593                 .data = &r8a77961_pinmux_info,
 594         },
 595 #endif
 596 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 597         {
 598                 .compatible = "renesas,pfc-r8a77965",
 599                 .data = &r8a77965_pinmux_info,
 600         },
 601 #endif
 602 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 603         {
 604                 .compatible = "renesas,pfc-r8a77970",
 605                 .data = &r8a77970_pinmux_info,
 606         },
 607 #endif
 608 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 609         {
 610                 .compatible = "renesas,pfc-r8a77980",
 611                 .data = &r8a77980_pinmux_info,
 612         },
 613 #endif
 614 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 615         {
 616                 .compatible = "renesas,pfc-r8a77990",
 617                 .data = &r8a77990_pinmux_info,
 618         },
 619 #endif
 620 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 621         {
 622                 .compatible = "renesas,pfc-r8a77995",
 623                 .data = &r8a77995_pinmux_info,
 624         },
 625 #endif
 626 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 627         {
 628                 .compatible = "renesas,pfc-sh73a0",
 629                 .data = &sh73a0_pinmux_info,
 630         },
 631 #endif
 632         { },
 633 };
 634 #endif
 635
 636 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 637 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 638 {
 639 }
 640
 641 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 642 {
 643         pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
 644 }
 645
 646 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 647 {
 648         sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
 649 }
 650
 651 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
 652         void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
 653 {
 654         unsigned int i, n = 0;
 655
 656         if (pfc->info->cfg_regs)
 657                 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
 658                         do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
 659
 660         if (pfc->info->drive_regs)
 661                 for (i = 0; pfc->info->drive_regs[i].reg; i++)
 662                         do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
 663
 664         if (pfc->info->bias_regs)
 665                 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 666                         do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
 667                         if (pfc->info->bias_regs[i].pud)
 668                                 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
 669                 }
 670
 671         if (pfc->info->ioctrl_regs)
 672                 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
 673                         do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
 674
 675         return n;
 676 }
 677
 678 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
 679 {
 680         unsigned int n;
 681
 682         /* This is the best we can do to check for the presence of PSCI */
 683         if (!psci_ops.cpu_suspend)
 684                 return 0;
 685
 686         n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
 687         if (!n)
 688                 return 0;
 689
 690         pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
 691                                              sizeof(*pfc->saved_regs),
 692                                              GFP_KERNEL);
 693         if (!pfc->saved_regs)
 694                 return -ENOMEM;
 695
 696         dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
 697         return 0;
 698 }
 699
 700 static int sh_pfc_suspend_noirq(struct device *dev)
 701 {
 702         struct sh_pfc *pfc = dev_get_drvdata(dev);
 703
 704         if (pfc->saved_regs)
 705                 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
 706         return 0;
 707 }
 708
 709 static int sh_pfc_resume_noirq(struct device *dev)
 710 {
 711         struct sh_pfc *pfc = dev_get_drvdata(dev);
 712
 713         if (pfc->saved_regs)
 714                 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
 715         return 0;
 716 }
 717
 718 static const struct dev_pm_ops sh_pfc_pm  = {
 719         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
 720 };
 721 #define DEV_PM_OPS      &sh_pfc_pm
 722 #else
 723 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
 724 #define DEV_PM_OPS      NULL
 725 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 726
 727 #ifdef DEBUG
 728 static bool __init is0s(const u16 *enum_ids, unsigned int n)
 729 {
 730         unsigned int i;
 731
 732         for (i = 0; i < n; i++)
 733                 if (enum_ids[i])
 734                         return false;
 735
 736         return true;
 737 }
 738
 739 static unsigned int sh_pfc_errors __initdata = 0;
 740 static unsigned int sh_pfc_warnings __initdata = 0;
 741
 742 static void __init sh_pfc_check_cfg_reg(const char *drvname,
 743                                         const struct pinmux_cfg_reg *cfg_reg)
 744 {
 745         unsigned int i, n, rw, fw;
 746
 747         if (cfg_reg->field_width) {
 748                 /* Checked at build time */
 749                 return;
 750         }
 751
 752         for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
 753                 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
 754                         pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
 755                                 drvname, cfg_reg->reg, rw, rw + fw - 1);
 756                         sh_pfc_warnings++;
 757                 }
 758                 n += 1 << fw;
 759                 rw += fw;
 760         }
 761
 762         if (rw != cfg_reg->reg_width) {
 763                 pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
 764                        drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
 765                 sh_pfc_errors++;
 766         }
 767
 768         if (n != cfg_reg->nr_enum_ids) {
 769                 pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
 770                        drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
 771                 sh_pfc_errors++;
 772         }
 773 }
 774
 775 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
 776 {
 777         const struct sh_pfc_function *func;
 778         const char *drvname = info->name;
 779         unsigned int *refcnts;
 780         unsigned int i, j, k;
 781
 782         pr_info("Checking %s\n", drvname);
 783
 784         /* Check pins */
 785         for (i = 0; i < info->nr_pins; i++) {
 786                 for (j = 0; j < i; j++) {
 787                         if (!strcmp(info->pins[i].name, info->pins[j].name)) {
 788                                 pr_err("%s: pin %s/%s: name conflict\n",
 789                                        drvname, info->pins[i].name,
 790                                        info->pins[j].name);
 791                                 sh_pfc_errors++;
 792                         }
 793
 794                         if (info->pins[i].pin != (u16)-1 &&
 795                             info->pins[i].pin == info->pins[j].pin) {
 796                                 pr_err("%s: pin %s/%s: pin %u conflict\n",
 797                                        drvname, info->pins[i].name,
 798                                        info->pins[j].name, info->pins[i].pin);
 799                                 sh_pfc_errors++;
 800                         }
 801
 802                         if (info->pins[i].enum_id &&
 803                             info->pins[i].enum_id == info->pins[j].enum_id) {
 804                                 pr_err("%s: pin %s/%s: enum_id %u conflict\n",
 805                                        drvname, info->pins[i].name,
 806                                        info->pins[j].name,
 807                                        info->pins[i].enum_id);
 808                                 sh_pfc_errors++;
 809                         }
 810                 }
 811         }
 812
 813         /* Check groups and functions */
 814         refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
 815         if (!refcnts)
 816                 return;
 817
 818         for (i = 0; i < info->nr_functions; i++) {
 819                 func = &info->functions[i];
 820                 if (!func->name) {
 821                         pr_err("%s: empty function %u\n", drvname, i);
 822                         sh_pfc_errors++;
 823                         continue;
 824                 }
 825                 for (j = 0; j < func->nr_groups; j++) {
 826                         for (k = 0; k < info->nr_groups; k++) {
 827                                 if (info->groups[k].name &&
 828                                     !strcmp(func->groups[j],
 829                                             info->groups[k].name)) {
 830                                         refcnts[k]++;
 831                                         break;
 832                                 }
 833                         }
 834
 835                         if (k == info->nr_groups) {
 836                                 pr_err("%s: function %s: group %s not found\n",
 837                                        drvname, func->name, func->groups[j]);
 838                                 sh_pfc_errors++;
 839                         }
 840                 }
 841         }
 842
 843         for (i = 0; i < info->nr_groups; i++) {
 844                 if (!info->groups[i].name) {
 845                         pr_err("%s: empty group %u\n", drvname, i);
 846                         sh_pfc_errors++;
 847                         continue;
 848                 }
 849                 if (!refcnts[i]) {
 850                         pr_err("%s: orphan group %s\n", drvname,
 851                                info->groups[i].name);
 852                         sh_pfc_errors++;
 853                 } else if (refcnts[i] > 1) {
 854                         pr_warn("%s: group %s referenced by %u functions\n",
 855                                 drvname, info->groups[i].name, refcnts[i]);
 856                         sh_pfc_warnings++;
 857                 }
 858         }
 859
 860         kfree(refcnts);
 861
 862         /* Check config register descriptions */
 863         for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
 864                 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
 865 }
 866
 867 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
 868 {
 869         unsigned int i;
 870
 871         pr_warn("Checking builtin pinmux tables\n");
 872
 873         for (i = 0; pdrv->id_table[i].name[0]; i++)
 874                 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
 875
 876 #ifdef CONFIG_OF
 877         for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
 878                 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
 879 #endif
 880
 881         pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
 882                 sh_pfc_warnings);
 883 }
 884
 885 #else /* !DEBUG */
 886 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
 887 #endif /* !DEBUG */
 888
 889 static int sh_pfc_probe(struct platform_device *pdev)
 890 {
 891 #ifdef CONFIG_OF
 892         struct device_node *np = pdev->dev.of_node;
 893 #endif
 894         const struct sh_pfc_soc_info *info;
 895         struct sh_pfc *pfc;
 896         int ret;
 897
 898 #ifdef CONFIG_OF
 899         if (np)
 900                 info = of_device_get_match_data(&pdev->dev);
 901         else
 902 #endif
 903                 info = (const void *)platform_get_device_id(pdev)->driver_data;
 904
 905         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
 906         if (pfc == NULL)
 907                 return -ENOMEM;
 908
 909         pfc->info = info;
 910         pfc->dev = &pdev->dev;
 911
 912         ret = sh_pfc_map_resources(pfc, pdev);
 913         if (unlikely(ret < 0))
 914                 return ret;
 915
 916         spin_lock_init(&pfc->lock);
 917
 918         if (info->ops && info->ops->init) {
 919                 ret = info->ops->init(pfc);
 920                 if (ret < 0)
 921                         return ret;
 922
 923                 /* .init() may have overridden pfc->info */
 924                 info = pfc->info;
 925         }
 926
 927         ret = sh_pfc_suspend_init(pfc);
 928         if (ret)
 929                 return ret;
 930
 931         /* Enable dummy states for those platforms without pinctrl support */
 932         if (!of_have_populated_dt())
 933                 pinctrl_provide_dummies();
 934
 935         ret = sh_pfc_init_ranges(pfc);
 936         if (ret < 0)
 937                 return ret;
 938
 939         /*
 940          * Initialize pinctrl bindings first
 941          */
 942         ret = sh_pfc_register_pinctrl(pfc);
 943         if (unlikely(ret != 0))
 944                 return ret;
 945
 946 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 947         /*
 948          * Then the GPIO chip
 949          */
 950         ret = sh_pfc_register_gpiochip(pfc);
 951         if (unlikely(ret != 0)) {
 952                 /*
 953                  * If the GPIO chip fails to come up we still leave the
 954                  * PFC state as it is, given that there are already
 955                  * extant users of it that have succeeded by this point.
 956                  */
 957                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
 958         }
 959 #endif
 960
 961         platform_set_drvdata(pdev, pfc);
 962
 963         dev_info(pfc->dev, "%s support registered\n", info->name);
 964
 965         return 0;
 966 }
 967
 968 static const struct platform_device_id sh_pfc_id_table[] = {
 969 #ifdef CONFIG_PINCTRL_PFC_SH7203
 970         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 971 #endif
 972 #ifdef CONFIG_PINCTRL_PFC_SH7264
 973         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
 974 #endif
 975 #ifdef CONFIG_PINCTRL_PFC_SH7269
 976         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
 977 #endif
 978 #ifdef CONFIG_PINCTRL_PFC_SH7720
 979         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
 980 #endif
 981 #ifdef CONFIG_PINCTRL_PFC_SH7722
 982         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
 983 #endif
 984 #ifdef CONFIG_PINCTRL_PFC_SH7723
 985         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
 986 #endif
 987 #ifdef CONFIG_PINCTRL_PFC_SH7724
 988         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
 989 #endif
 990 #ifdef CONFIG_PINCTRL_PFC_SH7734
 991         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
 992 #endif
 993 #ifdef CONFIG_PINCTRL_PFC_SH7757
 994         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
 995 #endif
 996 #ifdef CONFIG_PINCTRL_PFC_SH7785
 997         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
 998 #endif
 999 #ifdef CONFIG_PINCTRL_PFC_SH7786
1000         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1001 #endif
1002 #ifdef CONFIG_PINCTRL_PFC_SHX3
1003         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1004 #endif
1005         { },
1006 };
1007
1008 static struct platform_driver sh_pfc_driver = {
1009         .probe          = sh_pfc_probe,
1010         .id_table       = sh_pfc_id_table,
1011         .driver         = {
1012                 .name   = DRV_NAME,
1013                 .of_match_table = of_match_ptr(sh_pfc_of_table),
1014                 .pm     = DEV_PM_OPS,
1015         },
1016 };
1017
1018 static int __init sh_pfc_init(void)
1019 {
1020         sh_pfc_check_driver(&sh_pfc_driver);
1021         return platform_driver_register(&sh_pfc_driver);
1022 }
1023 postcore_initcall(sh_pfc_init);